\n

DAC

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x400 byte (0x0)
mem_usage : registers
protection :

Registers

CTLR

R8BDHR1

R12BDHR2

L12BDHR2

R8BDHR2

RD12BDHR

LD12BDHR

RD8BDHR

DOR1

DOR2

SWTR

R12BDHR1

L12BDHR1


CTLR

Control register (DAC_CR)
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CTLR CTLR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EN1 BOFF1 TEN1 TSEL1 WAVE1 MAMP1 DMAEN1 EN2 BOFF2 TEN2 TSEL2 WAVE2 MAMP2 DMAEN2

EN1 : DAC channel1 enable
bits : 0 - 0 (1 bit)

BOFF1 : DAC channel1 output buffer disable
bits : 1 - 1 (1 bit)

TEN1 : DAC channel1 trigger enable
bits : 2 - 2 (1 bit)

TSEL1 : DAC channel1 trigger selection
bits : 3 - 5 (3 bit)

WAVE1 : DAC channel1 noise/triangle wave generation enable
bits : 6 - 7 (2 bit)

MAMP1 : DAC channel1 mask/amplitude selector
bits : 8 - 11 (4 bit)

DMAEN1 : DAC channel1 DMA enable
bits : 12 - 12 (1 bit)

EN2 : DAC channel2 enable
bits : 16 - 16 (1 bit)

BOFF2 : DAC channel2 output buffer disable
bits : 17 - 17 (1 bit)

TEN2 : DAC channel2 trigger enable
bits : 18 - 18 (1 bit)

TSEL2 : DAC channel2 trigger selection
bits : 19 - 21 (3 bit)

WAVE2 : DAC channel2 noise/triangle wave generation enable
bits : 22 - 23 (2 bit)

MAMP2 : DAC channel2 mask/amplitude selector
bits : 24 - 27 (4 bit)

DMAEN2 : DAC channel2 DMA enable
bits : 28 - 28 (1 bit)


R8BDHR1

DAC channel1 8-bit right aligned data holding register (DAC_DHR8R1)
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

R8BDHR1 R8BDHR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DACC1DHR

DACC1DHR : DAC channel1 8-bit right-aligned data
bits : 0 - 7 (8 bit)


R12BDHR2

DAC channel2 12-bit right aligned data holding register (DAC_DHR12R2)
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

R12BDHR2 R12BDHR2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DACC2DHR

DACC2DHR : DAC channel2 12-bit right-aligned data
bits : 0 - 11 (12 bit)


L12BDHR2

DAC channel2 12-bit left aligned data holding register (DAC_DHR12L2)
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

L12BDHR2 L12BDHR2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DACC2DHR

DACC2DHR : DAC channel2 12-bit left-aligned data
bits : 4 - 15 (12 bit)


R8BDHR2

DAC channel2 8-bit right-aligned data holding register (DAC_DHR8R2)
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

R8BDHR2 R8BDHR2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DACC2DHR

DACC2DHR : DAC channel2 8-bit right-aligned data
bits : 0 - 7 (8 bit)


RD12BDHR

Dual DAC 12-bit right-aligned data holding register (DAC_DHR12RD), Bits 31:28 Reserved, Bits 15:12 Reserved
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RD12BDHR RD12BDHR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DACC1DHR DACC2DHR

DACC1DHR : DAC channel1 12-bit right-aligned data
bits : 0 - 11 (12 bit)

DACC2DHR : DAC channel2 12-bit right-aligned data
bits : 16 - 27 (12 bit)


LD12BDHR

DUAL DAC 12-bit left aligned data holding register (DAC_DHR12LD), Bits 19:16 Reserved, Bits 3:0 Reserved
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

LD12BDHR LD12BDHR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DACC1DHR DACC2DHR

DACC1DHR : DAC channel1 12-bit left-aligned data
bits : 4 - 15 (12 bit)

DACC2DHR : DAC channel2 12-bit right-aligned data
bits : 20 - 31 (12 bit)


RD8BDHR

DUAL DAC 8-bit right aligned data holding register (DAC_DHR8RD), Bits 31:16 Reserved
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RD8BDHR RD8BDHR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DACC1DHR DACC2DHR

DACC1DHR : DAC channel1 8-bit right-aligned data
bits : 0 - 7 (8 bit)

DACC2DHR : DAC channel2 8-bit right-aligned data
bits : 8 - 15 (8 bit)


DOR1

DAC channel1 data output register (DAC_DOR1)
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DOR1 DOR1 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DACC1DOR

DACC1DOR : DAC channel1 data output
bits : 0 - 11 (12 bit)


DOR2

DAC channel2 data output register (DAC_DOR2)
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

DOR2 DOR2 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DACC2DOR

DACC2DOR : DAC channel2 data output
bits : 0 - 11 (12 bit)


SWTR

DAC software trigger register (DAC_SWTRIGR)
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

SWTR SWTR write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SWTRIG1 SWTRIG2

SWTRIG1 : DAC channel1 software trigger
bits : 0 - 0 (1 bit)

SWTRIG2 : DAC channel2 software trigger
bits : 1 - 1 (1 bit)


R12BDHR1

DAC channel1 12-bit right-aligned data holding register(DAC_DHR12R1)
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

R12BDHR1 R12BDHR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DACC1DHR

DACC1DHR : DAC channel1 12-bit right-aligned data
bits : 0 - 11 (12 bit)


L12BDHR1

DAC channel1 12-bit left aligned data holding register (DAC_DHR12L1)
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

L12BDHR1 L12BDHR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DACC1DHR

DACC1DHR : DAC channel1 12-bit left-aligned data
bits : 4 - 15 (12 bit)



Is something missing? Is something wrong? can you help correct it ? Please contact us at info@chipselect.org !

This website is sponsored by EmbeetleEmbeetle, an IDE designed from scratch for embedded software developers.