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PWR

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x400 byte (0x0)
mem_usage : registers
protection :

Registers

CTLR

CSR


CTLR

Power control register (PWR_CTRL)
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CTLR CTLR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LPDS PDDS CWUF CSBF PVDE PLS DBP R2K_STYEN R30K_STYEN R2K_VBATEN R30K_VBATEN RAM_LVEN

LPDS : Low Power Deep Sleep
bits : 0 - 0 (1 bit)

PDDS : Power Down Deep Sleep
bits : 1 - 1 (1 bit)

CWUF : Clear Wake-up Flag
bits : 2 - 2 (1 bit)

CSBF : Clear STANDBY Flag
bits : 3 - 3 (1 bit)

PVDE : Power Voltage Detector Enable
bits : 4 - 4 (1 bit)

PLS : PVD Level Selection
bits : 5 - 7 (3 bit)

DBP : Disable Backup Domain write protection
bits : 8 - 8 (1 bit)

R2K_STYEN : standby 2k ram enable
bits : 16 - 16 (1 bit)

R30K_STYEN : standby 30k ram enable
bits : 17 - 17 (1 bit)

R2K_VBATEN : VBAT 30k ram enable
bits : 18 - 18 (1 bit)

R30K_VBATEN : VBAT 30k ram enable
bits : 19 - 19 (1 bit)

RAM_LVEN : Ram LV Enable
bits : 20 - 20 (1 bit)


CSR

Power control register (PWR_CSR)
address_offset : 0x4 Bytes (0x0)
size : 32 bit
reset_value : 0x0
reset_Mask : 0x0

CSR CSR 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WUF SBF PVDO EWUP

WUF : Wake-Up Flag
bits : 0 - 0 (1 bit)
access : read-only

SBF : STANDBY Flag
bits : 1 - 1 (1 bit)
access : read-only

PVDO : PVD Output
bits : 2 - 2 (1 bit)
access : read-only

EWUP : Enable WKUP pin
bits : 8 - 8 (1 bit)
access : read-write



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