\n

AFIO

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x400 byte (0x0)
mem_usage : registers
protection :

Registers

ECR

EXTICR3

EXTICR4

PCFR2

PCFR

EXTICR1

EXTICR2


ECR

Event Control Register (AFIO_ECR)
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ECR ECR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PIN PORT EVOE

PIN : Pin selection
bits : 0 - 3 (4 bit)

PORT : Port selection
bits : 4 - 6 (3 bit)

EVOE : Event Output Enable
bits : 7 - 7 (1 bit)


EXTICR3

External interrupt configuration register 3 (AFIO_EXTICR3)
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EXTICR3 EXTICR3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EXTI8 EXTI9 EXTI10 EXTI11

EXTI8 : EXTI8 configuration
bits : 0 - 3 (4 bit)

EXTI9 : EXTI9 configuration
bits : 4 - 7 (4 bit)

EXTI10 : EXTI10 configuration
bits : 8 - 11 (4 bit)

EXTI11 : EXTI11 configuration
bits : 12 - 15 (4 bit)


EXTICR4

External interrupt configuration register 4 (AFIO_EXTICR4)
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EXTICR4 EXTICR4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EXTI12 EXTI13 EXTI14 EXTI15

EXTI12 : EXTI12 configuration
bits : 0 - 3 (4 bit)

EXTI13 : EXTI13 configuration
bits : 4 - 7 (4 bit)

EXTI14 : EXTI14 configuration
bits : 8 - 11 (4 bit)

EXTI15 : EXTI15 configuration
bits : 12 - 15 (4 bit)


PCFR2

AF remap and debug I/O configuration register (AFIO_PCFR2)
address_offset : 0x1C Bytes (0x0)
size : 32 bit
reset_value : 0x0
reset_Mask : 0x0

PCFR2 PCFR2 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TIM8_REMAP TIM9_REMAP TIM10_REMAP FSMC_NADV UART4_REMAP UART5_REMAP UART6_REMAP UART7_REMAP UART8_REMAP UART1_REMAP2

TIM8_REMAP : TIM8 remapping
bits : 2 - 2 (1 bit)
access : read-write

TIM9_REMAP : TIM9 remapping
bits : 3 - 4 (2 bit)
access : read-write

TIM10_REMAP : TIM10 remapping
bits : 5 - 6 (2 bit)
access : read-write

FSMC_NADV : FSMC_NADV
bits : 10 - 10 (1 bit)
access : read-write

UART4_REMAP : UART4 remapping
bits : 16 - 17 (2 bit)
access : read-write

UART5_REMAP : UART5 remapping
bits : 18 - 19 (2 bit)
access : read-write

UART6_REMAP : UART6 remapping
bits : 20 - 21 (2 bit)
access : read-write

UART7_REMAP : UART7 remapping
bits : 22 - 23 (2 bit)
access : read-write

UART8_REMAP : UART8 remapping
bits : 24 - 25 (2 bit)
access : read-write

UART1_REMAP2 : UART1 remapping
bits : 26 - 26 (1 bit)
access : read-write


PCFR

AF remap and debug I/O configuration register (AFIO_PCFR)
address_offset : 0x4 Bytes (0x0)
size : 32 bit
reset_value : 0x0
reset_Mask : 0x0

PCFR PCFR 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SPI1RM I2C1RM USART1RM USART2RM USART3RM TIM1RM TIM2RM TIM3RM TIM4RM CAN1RM PD01RM TIM5CH4RM ADC1_ETRGINJ_RM ADC1_ETRGREG_RM ADC2_ETRGINJ_RM ADC2_ETRGREG_RM ETHRM CAN2RM MII_RMII_SEL SWCFG SPI3_RM TIM2ITRA_RM PTP_PPSP_RM

SPI1RM : SPI1 remapping
bits : 0 - 0 (1 bit)
access : read-write

I2C1RM : I2C1 remapping
bits : 1 - 1 (1 bit)
access : read-write

USART1RM : USART1 remapping
bits : 2 - 2 (1 bit)
access : read-write

USART2RM : USART2 remapping
bits : 3 - 3 (1 bit)
access : read-write

USART3RM : USART3 remapping
bits : 4 - 5 (2 bit)
access : read-write

TIM1RM : TIM1 remapping
bits : 6 - 7 (2 bit)
access : read-write

TIM2RM : TIM2 remapping
bits : 8 - 9 (2 bit)
access : read-write

TIM3RM : TIM3 remapping
bits : 10 - 11 (2 bit)
access : read-write

TIM4RM : TIM4 remapping
bits : 12 - 12 (1 bit)
access : read-write

CAN1RM : CAN1 remapping
bits : 13 - 14 (2 bit)
access : read-write

PD01RM : Port D0/Port D1 mapping on OSCIN/OSCOUT
bits : 15 - 15 (1 bit)
access : read-write

TIM5CH4RM : TIM5 channel4 internal remap
bits : 16 - 16 (1 bit)
access : read-write

ADC1_ETRGINJ_RM : ADC 1 External trigger injected conversion remapping
bits : 17 - 17 (1 bit)
access : read-write

ADC1_ETRGREG_RM : ADC 1 external trigger regular conversion remapping
bits : 18 - 18 (1 bit)
access : read-write

ADC2_ETRGINJ_RM : ADC 2 External trigger injected conversion remapping
bits : 19 - 19 (1 bit)
access : read-write

ADC2_ETRGREG_RM : ADC 2 external trigger regular conversion remapping
bits : 20 - 20 (1 bit)
access : read-write

ETHRM : Ethernet remapping
bits : 21 - 21 (1 bit)
access : read-write

CAN2RM : CAN2 remapping
bits : 22 - 22 (1 bit)
access : read-write

MII_RMII_SEL : MII_RMII_SEL
bits : 23 - 23 (1 bit)
access : read-write

SWCFG : Serial wire JTAG configuration
bits : 24 - 26 (3 bit)
access : write-only

SPI3_RM : SPI3 remapping
bits : 28 - 28 (1 bit)
access : read-write

TIM2ITRA_RM : TIM2 internally triggers 1 remapping
bits : 29 - 29 (1 bit)
access : read-write

PTP_PPSP_RM : Ethernet PTP_PPS remapping
bits : 30 - 30 (1 bit)
access : read-write


EXTICR1

External interrupt configuration register 1 (AFIO_EXTICR1)
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EXTICR1 EXTICR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EXTI0 EXTI1 EXTI2 EXTI3

EXTI0 : EXTI0 configuration
bits : 0 - 3 (4 bit)

EXTI1 : EXTI1 configuration
bits : 4 - 7 (4 bit)

EXTI2 : EXTI2 configuration
bits : 8 - 11 (4 bit)

EXTI3 : EXTI3 configuration
bits : 12 - 15 (4 bit)


EXTICR2

External interrupt configuration register 2 (AFIO_EXTICR2)
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EXTICR2 EXTICR2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EXTI4 EXTI5 EXTI6 EXTI7

EXTI4 : EXTI4 configuration
bits : 0 - 3 (4 bit)

EXTI5 : EXTI5 configuration
bits : 4 - 7 (4 bit)

EXTI6 : EXTI6 configuration
bits : 8 - 11 (4 bit)

EXTI7 : EXTI7 configuration
bits : 12 - 15 (4 bit)



Is something missing? Is something wrong? can you help correct it ? Please contact us at info@chipselect.org !

This website is sponsored by EmbeetleEmbeetle, an IDE designed from scratch for embedded software developers.