\n

EXTI

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x400 byte (0x0)
mem_usage : registers
protection :

Registers

INTENR

SWIEVR

INTFR

EVENR

RTENR

FTENR


INTENR

Interrupt mask register (EXTI_INTENR)
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

INTENR INTENR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MR0 MR1 MR2 MR3 MR4 MR5 MR6 MR7 MR8 MR9 MR10 MR11 MR12 MR13 MR14 MR15 MR16 MR17 MR18 MR19

MR0 : Interrupt Mask on line 0
bits : 0 - 0 (1 bit)

MR1 : Interrupt Mask on line 1
bits : 1 - 1 (1 bit)

MR2 : Interrupt Mask on line 2
bits : 2 - 2 (1 bit)

MR3 : Interrupt Mask on line 3
bits : 3 - 3 (1 bit)

MR4 : Interrupt Mask on line 4
bits : 4 - 4 (1 bit)

MR5 : Interrupt Mask on line 5
bits : 5 - 5 (1 bit)

MR6 : Interrupt Mask on line 6
bits : 6 - 6 (1 bit)

MR7 : Interrupt Mask on line 7
bits : 7 - 7 (1 bit)

MR8 : Interrupt Mask on line 8
bits : 8 - 8 (1 bit)

MR9 : Interrupt Mask on line 9
bits : 9 - 9 (1 bit)

MR10 : Interrupt Mask on line 10
bits : 10 - 10 (1 bit)

MR11 : Interrupt Mask on line 11
bits : 11 - 11 (1 bit)

MR12 : Interrupt Mask on line 12
bits : 12 - 12 (1 bit)

MR13 : Interrupt Mask on line 13
bits : 13 - 13 (1 bit)

MR14 : Interrupt Mask on line 14
bits : 14 - 14 (1 bit)

MR15 : Interrupt Mask on line 15
bits : 15 - 15 (1 bit)

MR16 : Interrupt Mask on line 16
bits : 16 - 16 (1 bit)

MR17 : Interrupt Mask on line 17
bits : 17 - 17 (1 bit)

MR18 : Interrupt Mask on line 18
bits : 18 - 18 (1 bit)

MR19 : Interrupt Mask on line 19
bits : 19 - 19 (1 bit)


SWIEVR

Software interrupt event register (EXTI_SWIEVR)
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SWIEVR SWIEVR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SWIER0 SWIER1 SWIER2 SWIER3 SWIER4 SWIER5 SWIER6 SWIER7 SWIER8 SWIER9 SWIER10 SWIER11 SWIER12 SWIER13 SWIER14 SWIER15 SWIER16 SWIER17 SWIER18 SWIER19

SWIER0 : Software Interrupt on line 0
bits : 0 - 0 (1 bit)

SWIER1 : Software Interrupt on line 1
bits : 1 - 1 (1 bit)

SWIER2 : Software Interrupt on line 2
bits : 2 - 2 (1 bit)

SWIER3 : Software Interrupt on line 3
bits : 3 - 3 (1 bit)

SWIER4 : Software Interrupt on line 4
bits : 4 - 4 (1 bit)

SWIER5 : Software Interrupt on line 5
bits : 5 - 5 (1 bit)

SWIER6 : Software Interrupt on line 6
bits : 6 - 6 (1 bit)

SWIER7 : Software Interrupt on line 7
bits : 7 - 7 (1 bit)

SWIER8 : Software Interrupt on line 8
bits : 8 - 8 (1 bit)

SWIER9 : Software Interrupt on line 9
bits : 9 - 9 (1 bit)

SWIER10 : Software Interrupt on line 10
bits : 10 - 10 (1 bit)

SWIER11 : Software Interrupt on line 11
bits : 11 - 11 (1 bit)

SWIER12 : Software Interrupt on line 12
bits : 12 - 12 (1 bit)

SWIER13 : Software Interrupt on line 13
bits : 13 - 13 (1 bit)

SWIER14 : Software Interrupt on line 14
bits : 14 - 14 (1 bit)

SWIER15 : Software Interrupt on line 15
bits : 15 - 15 (1 bit)

SWIER16 : Software Interrupt on line 16
bits : 16 - 16 (1 bit)

SWIER17 : Software Interrupt on line 17
bits : 17 - 17 (1 bit)

SWIER18 : Software Interrupt on line 18
bits : 18 - 18 (1 bit)

SWIER19 : Software Interrupt on line 19
bits : 19 - 19 (1 bit)


INTFR

Pending register (EXTI_INTFR)
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

INTFR INTFR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PR0 PR1 PR2 PR3 PR4 PR5 PR6 PR7 PR8 PR9 PR10 PR11 PR12 PR13 PR14 PR15 PR16 PR17 PR18 PR19

PR0 : Pending bit 0
bits : 0 - 0 (1 bit)

PR1 : Pending bit 1
bits : 1 - 1 (1 bit)

PR2 : Pending bit 2
bits : 2 - 2 (1 bit)

PR3 : Pending bit 3
bits : 3 - 3 (1 bit)

PR4 : Pending bit 4
bits : 4 - 4 (1 bit)

PR5 : Pending bit 5
bits : 5 - 5 (1 bit)

PR6 : Pending bit 6
bits : 6 - 6 (1 bit)

PR7 : Pending bit 7
bits : 7 - 7 (1 bit)

PR8 : Pending bit 8
bits : 8 - 8 (1 bit)

PR9 : Pending bit 9
bits : 9 - 9 (1 bit)

PR10 : Pending bit 10
bits : 10 - 10 (1 bit)

PR11 : Pending bit 11
bits : 11 - 11 (1 bit)

PR12 : Pending bit 12
bits : 12 - 12 (1 bit)

PR13 : Pending bit 13
bits : 13 - 13 (1 bit)

PR14 : Pending bit 14
bits : 14 - 14 (1 bit)

PR15 : Pending bit 15
bits : 15 - 15 (1 bit)

PR16 : Pending bit 16
bits : 16 - 16 (1 bit)

PR17 : Pending bit 17
bits : 17 - 17 (1 bit)

PR18 : Pending bit 18
bits : 18 - 18 (1 bit)

PR19 : Pending bit 19
bits : 19 - 19 (1 bit)


EVENR

Event mask register (EXTI_EVENR)
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EVENR EVENR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MR0 MR1 MR2 MR3 MR4 MR5 MR6 MR7 MR8 MR9 MR10 MR11 MR12 MR13 MR14 MR15 MR16 MR17 MR18 MR19

MR0 : Event Mask on line 0
bits : 0 - 0 (1 bit)

MR1 : Event Mask on line 1
bits : 1 - 1 (1 bit)

MR2 : Event Mask on line 2
bits : 2 - 2 (1 bit)

MR3 : Event Mask on line 3
bits : 3 - 3 (1 bit)

MR4 : Event Mask on line 4
bits : 4 - 4 (1 bit)

MR5 : Event Mask on line 5
bits : 5 - 5 (1 bit)

MR6 : Event Mask on line 6
bits : 6 - 6 (1 bit)

MR7 : Event Mask on line 7
bits : 7 - 7 (1 bit)

MR8 : Event Mask on line 8
bits : 8 - 8 (1 bit)

MR9 : Event Mask on line 9
bits : 9 - 9 (1 bit)

MR10 : Event Mask on line 10
bits : 10 - 10 (1 bit)

MR11 : Event Mask on line 11
bits : 11 - 11 (1 bit)

MR12 : Event Mask on line 12
bits : 12 - 12 (1 bit)

MR13 : Event Mask on line 13
bits : 13 - 13 (1 bit)

MR14 : Event Mask on line 14
bits : 14 - 14 (1 bit)

MR15 : Event Mask on line 15
bits : 15 - 15 (1 bit)

MR16 : Event Mask on line 16
bits : 16 - 16 (1 bit)

MR17 : Event Mask on line 17
bits : 17 - 17 (1 bit)

MR18 : Event Mask on line 18
bits : 18 - 18 (1 bit)

MR19 : Event Mask on line 19
bits : 19 - 19 (1 bit)


RTENR

Rising Trigger selection register (EXTI_RTENR)
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RTENR RTENR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TR0 TR1 TR2 TR3 TR4 TR5 TR6 TR7 TR8 TR9 TR10 TR11 TR12 TR13 TR14 TR15 TR16 TR17 TR18 TR19

TR0 : Rising trigger event configuration of line 0
bits : 0 - 0 (1 bit)

TR1 : Rising trigger event configuration of line 1
bits : 1 - 1 (1 bit)

TR2 : Rising trigger event configuration of line 2
bits : 2 - 2 (1 bit)

TR3 : Rising trigger event configuration of line 3
bits : 3 - 3 (1 bit)

TR4 : Rising trigger event configuration of line 4
bits : 4 - 4 (1 bit)

TR5 : Rising trigger event configuration of line 5
bits : 5 - 5 (1 bit)

TR6 : Rising trigger event configuration of line 6
bits : 6 - 6 (1 bit)

TR7 : Rising trigger event configuration of line 7
bits : 7 - 7 (1 bit)

TR8 : Rising trigger event configuration of line 8
bits : 8 - 8 (1 bit)

TR9 : Rising trigger event configuration of line 9
bits : 9 - 9 (1 bit)

TR10 : Rising trigger event configuration of line 10
bits : 10 - 10 (1 bit)

TR11 : Rising trigger event configuration of line 11
bits : 11 - 11 (1 bit)

TR12 : Rising trigger event configuration of line 12
bits : 12 - 12 (1 bit)

TR13 : Rising trigger event configuration of line 13
bits : 13 - 13 (1 bit)

TR14 : Rising trigger event configuration of line 14
bits : 14 - 14 (1 bit)

TR15 : Rising trigger event configuration of line 15
bits : 15 - 15 (1 bit)

TR16 : Rising trigger event configuration of line 16
bits : 16 - 16 (1 bit)

TR17 : Rising trigger event configuration of line 17
bits : 17 - 17 (1 bit)

TR18 : Rising trigger event configuration of line 18
bits : 18 - 18 (1 bit)

TR19 : Rising trigger event configuration of line 19
bits : 19 - 19 (1 bit)


FTENR

Falling Trigger selection register (EXTI_FTENR)
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FTENR FTENR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TR0 TR1 TR2 TR3 TR4 TR5 TR6 TR7 TR8 TR9 TR10 TR11 TR12 TR13 TR14 TR15 TR16 TR17 TR18 TR19

TR0 : Falling trigger event configuration of line 0
bits : 0 - 0 (1 bit)

TR1 : Falling trigger event configuration of line 1
bits : 1 - 1 (1 bit)

TR2 : Falling trigger event configuration of line 2
bits : 2 - 2 (1 bit)

TR3 : Falling trigger event configuration of line 3
bits : 3 - 3 (1 bit)

TR4 : Falling trigger event configuration of line 4
bits : 4 - 4 (1 bit)

TR5 : Falling trigger event configuration of line 5
bits : 5 - 5 (1 bit)

TR6 : Falling trigger event configuration of line 6
bits : 6 - 6 (1 bit)

TR7 : Falling trigger event configuration of line 7
bits : 7 - 7 (1 bit)

TR8 : Falling trigger event configuration of line 8
bits : 8 - 8 (1 bit)

TR9 : Falling trigger event configuration of line 9
bits : 9 - 9 (1 bit)

TR10 : Falling trigger event configuration of line 10
bits : 10 - 10 (1 bit)

TR11 : Falling trigger event configuration of line 11
bits : 11 - 11 (1 bit)

TR12 : Falling trigger event configuration of line 12
bits : 12 - 12 (1 bit)

TR13 : Falling trigger event configuration of line 13
bits : 13 - 13 (1 bit)

TR14 : Falling trigger event configuration of line 14
bits : 14 - 14 (1 bit)

TR15 : Falling trigger event configuration of line 15
bits : 15 - 15 (1 bit)

TR16 : Falling trigger event configuration of line 16
bits : 16 - 16 (1 bit)

TR17 : Falling trigger event configuration of line 17
bits : 17 - 17 (1 bit)

TR18 : Falling trigger event configuration of line 18
bits : 18 - 18 (1 bit)

TR19 : Falling trigger event configuration of line 19
bits : 19 - 19 (1 bit)



Is something missing? Is something wrong? can you help correct it ? Please contact us at info@chipselect.org !

This website is sponsored by EmbeetleEmbeetle, an IDE designed from scratch for embedded software developers.