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I2C

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x400 byte (0x0)
mem_usage : registers
protection :

Registers

CTLR1

DATAR

STAR1

STAR2

CKCFGR

RTR

CTLR2

OADDR1

OADDR2


CTLR1

Control register 1
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CTLR1 CTLR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PE SMBUS SMBTYPE ENARP ENPEC ENGC NOSTRETCH START STOP ACK POS PEC ALERT SWRST

PE : Peripheral enable
bits : 0 - 0 (1 bit)

SMBUS : SMBus mode
bits : 1 - 1 (1 bit)

SMBTYPE : SMBus type
bits : 3 - 3 (1 bit)

ENARP : ARP enable
bits : 4 - 4 (1 bit)

ENPEC : PEC enable
bits : 5 - 5 (1 bit)

ENGC : General call enable
bits : 6 - 6 (1 bit)

NOSTRETCH : Clock stretching disable (Slave mode)
bits : 7 - 7 (1 bit)

START : Start generation
bits : 8 - 8 (1 bit)

STOP : Stop generation
bits : 9 - 9 (1 bit)

ACK : Acknowledge enable
bits : 10 - 10 (1 bit)

POS : Acknowledge/PEC Position (for data reception)
bits : 11 - 11 (1 bit)

PEC : Packet error checking
bits : 12 - 12 (1 bit)

ALERT : SMBus alert
bits : 13 - 13 (1 bit)

SWRST : Software reset
bits : 15 - 15 (1 bit)


DATAR

Data register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DATAR DATAR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATAR

DATAR : 8-bit data register
bits : 0 - 7 (8 bit)


STAR1

Status register 1
address_offset : 0x14 Bytes (0x0)
size : 32 bit
reset_value : 0x0
reset_Mask : 0x0

STAR1 STAR1 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SB ADDR BTF ADD10 STOPF RxNE TxE BERR ARLO AF OVR PECERR TIMEOUT SMBALERT

SB : Start bit (Master mode)
bits : 0 - 0 (1 bit)
access : read-only

ADDR : Address sent (master mode)/matched (slave mode)
bits : 1 - 1 (1 bit)
access : read-only

BTF : Byte transfer finished
bits : 2 - 2 (1 bit)
access : read-only

ADD10 : 10-bit header sent (Master mode)
bits : 3 - 3 (1 bit)
access : read-only

STOPF : Stop detection (slave mode)
bits : 4 - 4 (1 bit)
access : read-only

RxNE : Data register not empty (receivers)
bits : 6 - 6 (1 bit)
access : read-only

TxE : Data register empty (transmitters)
bits : 7 - 7 (1 bit)
access : read-only

BERR : Bus error
bits : 8 - 8 (1 bit)
access : read-write

ARLO : Arbitration lost (master mode)
bits : 9 - 9 (1 bit)
access : read-write

AF : Acknowledge failure
bits : 10 - 10 (1 bit)
access : read-write

OVR : Overrun/Underrun
bits : 11 - 11 (1 bit)
access : read-write

PECERR : PEC Error in reception
bits : 12 - 12 (1 bit)
access : read-write

TIMEOUT : Timeout or Tlow error
bits : 14 - 14 (1 bit)
access : read-write

SMBALERT : SMBus alert
bits : 15 - 15 (1 bit)
access : read-write


STAR2

Status register 2
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

STAR2 STAR2 read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MSL BUSY TRA GENCALL SMBDEFAULT SMBHOST DUALF PEC

MSL : Master/slave
bits : 0 - 0 (1 bit)

BUSY : Bus busy
bits : 1 - 1 (1 bit)

TRA : Transmitter/receiver
bits : 2 - 2 (1 bit)

GENCALL : General call address (Slave mode)
bits : 4 - 4 (1 bit)

SMBDEFAULT : SMBus device default address (Slave mode)
bits : 5 - 5 (1 bit)

SMBHOST : SMBus host header (Slave mode)
bits : 6 - 6 (1 bit)

DUALF : Dual flag (Slave mode)
bits : 7 - 7 (1 bit)

PEC : acket error checking register
bits : 8 - 15 (8 bit)


CKCFGR

Clock control register
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CKCFGR CKCFGR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CCR DUTY F_S

CCR : Clock control register in Fast/Standard mode (Master mode)
bits : 0 - 11 (12 bit)

DUTY : Fast mode duty cycle
bits : 14 - 14 (1 bit)

F_S : I2C master mode selection
bits : 15 - 15 (1 bit)


RTR

Raise time register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RTR RTR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TRISE

TRISE : Maximum rise time in Fast/Standard mode (Master mode)
bits : 0 - 5 (6 bit)


CTLR2

Control register 2
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CTLR2 CTLR2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FREQ ITERREN ITEVTEN ITBUFEN DMAEN LAST

FREQ : Peripheral clock frequency
bits : 0 - 5 (6 bit)

ITERREN : Error interrupt enable
bits : 8 - 8 (1 bit)

ITEVTEN : Event interrupt enable
bits : 9 - 9 (1 bit)

ITBUFEN : Buffer interrupt enable
bits : 10 - 10 (1 bit)

DMAEN : DMA requests enable
bits : 11 - 11 (1 bit)

LAST : DMA last transfer
bits : 12 - 12 (1 bit)


OADDR1

Own address register 1
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OADDR1 OADDR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADD0 ADD7_1 ADD9_8 MUST1 ADDMODE

ADD0 : Interface address
bits : 0 - 0 (1 bit)

ADD7_1 : Interface address
bits : 1 - 7 (7 bit)

ADD9_8 : Interface address
bits : 8 - 9 (2 bit)

MUST1 : Must be 1
bits : 14 - 14 (1 bit)

ADDMODE : Addressing mode (slave mode)
bits : 15 - 15 (1 bit)


OADDR2

Own address register 2
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OADDR2 OADDR2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ENDUAL ADD2

ENDUAL : Dual addressing mode enable
bits : 0 - 0 (1 bit)

ADD2 : Interface address
bits : 1 - 7 (7 bit)



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