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SPI

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x400 byte (0x0)
mem_usage : registers
protection :

Registers

CTLR1

CRCR

RCRCR

TCRCR

SPI_I2S_CFGR

HSCR

CTLR2

STATR

DATAR


CTLR1

control register 1
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CTLR1 CTLR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CPHA CPOL MSTR BR SPE LSBFIRST SSI SSM RXONLY DFF CRCNEXT CRCEN BIDIOE BIDIMODE

CPHA : Clock phase
bits : 0 - 0 (1 bit)

CPOL : Clock polarity
bits : 1 - 1 (1 bit)

MSTR : Master selection
bits : 2 - 2 (1 bit)

BR : Baud rate control
bits : 3 - 5 (3 bit)

SPE : SPI enable
bits : 6 - 6 (1 bit)

LSBFIRST : Frame format
bits : 7 - 7 (1 bit)

SSI : Internal slave select
bits : 8 - 8 (1 bit)

SSM : Software slave management
bits : 9 - 9 (1 bit)

RXONLY : Receive only
bits : 10 - 10 (1 bit)

DFF : Data frame format
bits : 11 - 11 (1 bit)

CRCNEXT : CRC transfer next
bits : 12 - 12 (1 bit)

CRCEN : Hardware CRC calculation enable
bits : 13 - 13 (1 bit)

BIDIOE : Output enable in bidirectional mode
bits : 14 - 14 (1 bit)

BIDIMODE : Bidirectional data mode enable
bits : 15 - 15 (1 bit)


CRCR

CRCR polynomial register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CRCR CRCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CRCPOLY

CRCPOLY : CRC polynomial register
bits : 0 - 15 (16 bit)


RCRCR

RX CRC register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

RCRCR RCRCR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RXCRC

RXCRC : Rx CRC register
bits : 0 - 15 (16 bit)


TCRCR

TX CRC register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

TCRCR TCRCR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TXCRC

TXCRC : Tx CRC register
bits : 0 - 15 (16 bit)


SPI_I2S_CFGR

SPI_I2S configure register
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SPI_I2S_CFGR SPI_I2S_CFGR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CHLEN DATLEN CKPOL I2SSTD PCMSYNC I2SCFG I2SE I2SMOD

CHLEN : Channel length (number of bits per audio channel)
bits : 0 - 0 (1 bit)

DATLEN : DATLEN[1:0] bits (Data length to be transferred)
bits : 1 - 2 (2 bit)

CKPOL : steady state clock polarity
bits : 3 - 3 (1 bit)

I2SSTD : I2SSTD[1:0] bits (I2S standard selection)
bits : 4 - 5 (2 bit)

PCMSYNC : PCM frame synchronization
bits : 7 - 7 (1 bit)

I2SCFG : I2SCFG[1:0] bits (I2S configuration mode)
bits : 8 - 9 (2 bit)

I2SE : I2S Enable
bits : 10 - 10 (1 bit)

I2SMOD : I2S mode selection
bits : 11 - 11 (1 bit)


HSCR

high speed control register
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HSCR HSCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HSRXEN

HSRXEN : High speed mode read enable
bits : 0 - 0 (1 bit)


CTLR2

control register 2
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CTLR2 CTLR2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RXDMAEN TXDMAEN SSOE ERRIE RXNEIE TXEIE

RXDMAEN : Rx buffer DMA enable
bits : 0 - 0 (1 bit)

TXDMAEN : Tx buffer DMA enable
bits : 1 - 1 (1 bit)

SSOE : SS output enable
bits : 2 - 2 (1 bit)

ERRIE : Error interrupt enable
bits : 5 - 5 (1 bit)

RXNEIE : RX buffer not empty interrupt enable
bits : 6 - 6 (1 bit)

TXEIE : Tx buffer empty interrupt enable
bits : 7 - 7 (1 bit)


STATR

status register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
reset_value : 0x0
reset_Mask : 0x0

STATR STATR 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RXNE TXE CHSID UDR CRCERR MODF OVR BSY

RXNE : Receive buffer not empty
bits : 0 - 0 (1 bit)
access : read-only

TXE : Transmit buffer empty
bits : 1 - 1 (1 bit)
access : read-only

CHSID : Channel side
bits : 2 - 2 (1 bit)
access : read-only

UDR : Underrun flag
bits : 3 - 3 (1 bit)
access : read-only

CRCERR : CRC error flag
bits : 4 - 4 (1 bit)
access : read-write

MODF : Mode fault
bits : 5 - 5 (1 bit)
access : read-only

OVR : Overrun flag
bits : 6 - 6 (1 bit)
access : read-only

BSY : Busy flag
bits : 7 - 7 (1 bit)
access : read-only


DATAR

data register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DATAR DATAR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATAR

DATAR : Data register
bits : 0 - 15 (16 bit)



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