\n

DBG

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x400 byte (0x0)
mem_usage : registers
protection :

Registers

CFGR1

CFGR2


CFGR1

DBGMCU_CFGR1
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CFGR1 CFGR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DEG_IWDG DEG_WWDG DEG_I2C1 DEG_I2C2 DEG_TIM1 DEG_TIM2 DEG_TIM3 DEG_TIM4

DEG_IWDG : DEG_IWDG
bits : 0 - 0 (1 bit)

DEG_WWDG : DEG_WWDG
bits : 1 - 1 (1 bit)

DEG_I2C1 : DEG_I2C1
bits : 2 - 2 (1 bit)

DEG_I2C2 : DEG_I2C2
bits : 3 - 3 (1 bit)

DEG_TIM1 : DEG_TIM1
bits : 4 - 4 (1 bit)

DEG_TIM2 : DEG_TIM2
bits : 5 - 5 (1 bit)

DEG_TIM3 : DEG_TIM3
bits : 6 - 6 (1 bit)

DEG_TIM4 : DEG_TIM4
bits : 7 - 7 (1 bit)


CFGR2

DBGMCU_CFGR2
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CFGR2 CFGR2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DBG_SLEEP DBG_STOP DBG_STANDBY

DBG_SLEEP : DBG_SLEEP
bits : 0 - 0 (1 bit)

DBG_STOP : DBG_STOP
bits : 1 - 1 (1 bit)

DBG_STANDBY : DBG_STANDBY
bits : 2 - 2 (1 bit)



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