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USBHD

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x400 byte (0x0)
mem_usage : registers
protection :

Registers

USB_CTRL

UHOST_CTRL

UEP_CONFIG

UEP10_T_LEN

UEP10_T_CTRL

UEP10_R_CTRL

UEP11_T_LEN

UEP11_T_CTRL

UEP11_R_CTRL

UEP12_T_LEN

UEP12_T_CTRL

UEP12_R_CTRL

UEP13_T_LEN

UEP13_T_CTRL

UEP13_R_CTRL

UEP14_T_LEN

UEP14_T_CTRL

UEP14_R_CTRL

UEP15_T_LEN

UEP15_T_CTRL

UEP15_R_CTRL

UEP_TYPE

UEP_BUF_MOD

UEP0_DMA

USB_INT_EN

UEP1_RX_DMA

UEP2_RX_DMA__UH_RX_DMA

UEP3_RX_DMA

UEP4_RX_DMA

USB_DEV_AD

UEP5_RX_DMA

UEP6_RX_DMA

UEP7_RX_DMA

UEP8_RX_DMA

USB_FRAME_NO

UEP9_RX_DMA

UEP10_RX_DMA

UEP11_RX_DMA

UEP12_RX_DMA

UEP13_RX_DMA

UEP14_RX_DMA

UEP15_RX_DMA

UEP1_TX_DMA

USB_USB_SUSPEND

UEP2_TX_DMA

UEP3_TX_DMA__UH_TX_DMA

UEP4_TX_DMA

UEP5_TX_DMA

UEP6_TX_DMA

UEP7_TX_DMA

UEP8_TX_DMA

UEP9_TX_DMA

USB_SPEED_TYPE

UEP10_TX_DMA

UEP11_TX_DMA

UEP12_TX_DMA____UH_SPLIT_DATA

UEP13_TX_DMA

USB_MIS_ST

UEP14_TX_DMA

UEP15_TX_DMA

UEP0_MAX_LEN

UEP1_MAX_LEN

USB_INT_FG

UEP2_MAX_LEN__UH_RX_MAX_LEN

UEP3_MAX_LEN

UEP4_MAX_LEN

UEP5_MAX_LEN

USB_INT_ST

UEP6_MAX_LEN

UEP7_MAX_LEN

UEP8_MAX_LEN

UEP9_MAX_LEN

USB_RX_LEN

UEP10_MAX_LEN

UEP11_MAX_LEN

UEP12_MAX_LEN

UEP13_MAX_LEN

UEP14_MAX_LEN

UEP15_MAX_LEN

UEP0_T_LEN

UEP0_T_CTRL

UEP0_R_CTRL

UEP1_T_LEN

UEP1_T_CTRL

UEP1_R_CTRL

UEP2_T_LEN__UH_EP_PID

UEP2_T_CTRL

UEP2_R_CTRL__UH_RX_CTRL

UEP3_T_LEN___UH_TX_LEN_H

UEP3_T_CTRL___UH_TX_CTRL

UEP3_R_CTRL

UEP4_T_LEN

UEP4_T_CTRL

UEP4_R_CTRL

UEP5_T_LEN

UEP5_T_CTRL

UEP5_R_CTRL

UEP6_T_LEN

UEP6_T_CTRL

UEP6_R_CTRL

UEP7_T_LEN

UEP7_T_CTRL

UEP7_R_CTRL

UEP8_T_LEN

UEP8_T_CTRL

UEP8_R_CTRL

UEP9_T_LEN

UEP9_T_CTRL

UEP9_R_CTRL


USB_CTRL

USB base control
address_offset : 0x0 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USB_CTRL USB_CTRL read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 RB_UC_DMA_EN RB_UC_CLR_ALL RB_UC_RESET_SIE RB_UC_INT_BUSY RB_UC_DEV_PU_EN RB_UC_SPEED_TYPE RB_UC_HOST_MODE

RB_UC_DMA_EN : DMA enable and DMA interrupt enable for USB
bits : 0 - 0 (1 bit)

RB_UC_CLR_ALL : force clear FIFO and count of USB
bits : 1 - 1 (1 bit)

RB_UC_RESET_SIE : force reset USB SIE, need software clear
bits : 2 - 2 (1 bit)

RB_UC_INT_BUSY : enable automatic responding busy for device mode or automatic pause for host mode during interrupt flag UIF_TRANSFER valid
bits : 3 - 3 (1 bit)

RB_UC_DEV_PU_EN : USB device enable and internal pullup resistance enable
bits : 4 - 4 (1 bit)

RB_UC_SPEED_TYPE : enable USB low speed: 00=full speed, 01=high speed, 10 =low speed
bits : 5 - 6 (2 bit)

RB_UC_HOST_MODE : enable USB host mode: 0=device mode, 1=host mode
bits : 7 - 7 (1 bit)


UHOST_CTRL

USB HOST control
address_offset : 0x1 Bytes (0x0)
size : 8 bit
reset_value : 0x0
reset_Mask : 0x0

UHOST_CTRL UHOST_CTRL 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 bUH_TX_BUS_RESET bUH_TX_BUS_SUSPEND bUH_TX_BUS_RESUME bUH_REMOTE_WKUP bUH_PHY_SUSPENDM bUH_SOF_FREE bUH_SOF_EN

bUH_TX_BUS_RESET : USB host bus reset status
bits : 0 - 0 (1 bit)
access : read-write

bUH_TX_BUS_SUSPEND : the host sends hang sigal
bits : 1 - 1 (1 bit)
access : read-write

bUH_TX_BUS_RESUME : host wake up device
bits : 2 - 2 (1 bit)
access : read-write

bUH_REMOTE_WKUP : the remoke wake-up
bits : 3 - 3 (1 bit)
access : read-write

bUH_PHY_SUSPENDM : USB-PHY thesuspended state the internal USB-PLL is turned off
bits : 4 - 4 (1 bit)
access : read-write

bUH_SOF_FREE : the bus is idle
bits : 6 - 6 (1 bit)
access : read-only

bUH_SOF_EN : automatically generate the SOF packet enabling control bit
bits : 7 - 7 (1 bit)
access : read-write


UEP_CONFIG

USB endpoint configuration
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

UEP_CONFIG UEP_CONFIG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bUEP_T_EN_bUH_TX_EN bUEP_R_EN__UH_EP_MOD

bUEP_T_EN_bUH_TX_EN : endpoint TX enable/bUH_TX_EN
bits : 1 - 15 (15 bit)
access : read-write

bUEP_R_EN__UH_EP_MOD : endpoint RX enable/bUH_TX_EN
bits : 17 - 31 (15 bit)
access : read-write


UEP10_T_LEN

endpoint 10 send the length
address_offset : 0x100 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

UEP10_T_LEN UEP10_T_LEN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 UEP10_T_LEN

UEP10_T_LEN : endpoint 10 send the length
bits : 0 - 10 (11 bit)
access : read-write


UEP10_T_CTRL

endpoint 10 send control
address_offset : 0x102 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

UEP10_T_CTRL UEP10_T_CTRL read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 MASK_UEP_T_RES MASK_UEP_T_TOG bUEP_T_TOG_AUTO

MASK_UEP_T_RES : endpoint 10 control of the send response to IN transactions
bits : 0 - 1 (2 bit)
access : read-write

MASK_UEP_T_TOG : endpoint 10 synchronous trigger bit for the sender to prepare
bits : 3 - 4 (2 bit)
access : read-write

bUEP_T_TOG_AUTO : endpoint 10 synchronous trigger bit automatic filp enables the control bit
bits : 5 - 5 (1 bit)
access : read-write


UEP10_R_CTRL

endpoint 10 send control
address_offset : 0x103 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

UEP10_R_CTRL UEP10_R_CTRL read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 MASK_UEP_R_RES MASK_UEP_R_TOG bUEP_R_TOG_AUTO

MASK_UEP_R_RES : endpoint 10 control of the accept response to OUT transactions
bits : 0 - 1 (2 bit)
access : read-write

MASK_UEP_R_TOG : endpoint 10 synchronous trigger bit for the accept to prepare
bits : 3 - 4 (2 bit)
access : read-write

bUEP_R_TOG_AUTO : endpoint 10 synchronous trigger bit automatic filp enables the control bit
bits : 5 - 5 (1 bit)
access : read-only


UEP11_T_LEN

endpoint 11 send the length
address_offset : 0x104 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

UEP11_T_LEN UEP11_T_LEN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 UEP0_T_LEN

UEP0_T_LEN : endpoint 11 send the length
bits : 0 - 10 (11 bit)
access : read-write


UEP11_T_CTRL

endpoint 11 send control
address_offset : 0x106 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

UEP11_T_CTRL UEP11_T_CTRL read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 MASK_UEP_T_RES MASK_UEP_T_TOG bUEP_T_TOG_AUTO

MASK_UEP_T_RES : endpoint 11 control of the send response to IN transactions
bits : 0 - 1 (2 bit)
access : read-write

MASK_UEP_T_TOG : endpoint 11 synchronous trigger bit for the sender to prepare
bits : 3 - 4 (2 bit)
access : read-write

bUEP_T_TOG_AUTO : endpoint 11 synchronous trigger bit automatic filp enables the control bit
bits : 5 - 5 (1 bit)
access : read-write


UEP11_R_CTRL

endpoint 11 send control
address_offset : 0x107 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

UEP11_R_CTRL UEP11_R_CTRL read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 MASK_UEP_R_RES MASK_UEP_R_TOG bUEP_R_TOG_AUTO

MASK_UEP_R_RES : endpoint 11 control of the accept response to OUT transactions
bits : 0 - 1 (2 bit)
access : read-write

MASK_UEP_R_TOG : endpoint 11 synchronous trigger bit for the accept to prepare
bits : 3 - 4 (2 bit)
access : read-write

bUEP_R_TOG_AUTO : endpoint 11 synchronous trigger bit automatic filp enables the control bit
bits : 5 - 5 (1 bit)
access : read-only


UEP12_T_LEN

endpoint 12 send the length
address_offset : 0x108 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

UEP12_T_LEN UEP12_T_LEN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 UEP0_T_LEN

UEP0_T_LEN : endpoint 12 send the length
bits : 0 - 10 (11 bit)
access : read-write


UEP12_T_CTRL

endpoint 12 send control
address_offset : 0x10A Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

UEP12_T_CTRL UEP12_T_CTRL read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 MASK_UEP_T_RES MASK_UEP_T_TOG bUEP_T_TOG_AUTO

MASK_UEP_T_RES : endpoint 12 control of the send response to IN transactions
bits : 0 - 1 (2 bit)
access : read-write

MASK_UEP_T_TOG : endpoint 12 synchronous trigger bit for the sender to prepare
bits : 3 - 4 (2 bit)
access : read-write

bUEP_T_TOG_AUTO : endpoint 12 synchronous trigger bit automatic filp enables the control bit
bits : 5 - 5 (1 bit)
access : read-write


UEP12_R_CTRL

endpoint 12 send control
address_offset : 0x10B Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

UEP12_R_CTRL UEP12_R_CTRL read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 MASK_UEP_R_RES MASK_UEP_R_TOG bUEP_R_TOG_AUTO

MASK_UEP_R_RES : endpoint 12 control of the accept response to OUT transactions
bits : 0 - 1 (2 bit)
access : read-write

MASK_UEP_R_TOG : endpoint 12 synchronous trigger bit for the accept to prepare
bits : 3 - 4 (2 bit)
access : read-write

bUEP_R_TOG_AUTO : endpoint 12 synchronous trigger bit automatic filp enables the control bit
bits : 5 - 5 (1 bit)
access : read-only


UEP13_T_LEN

endpoint 13 send the length
address_offset : 0x10C Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

UEP13_T_LEN UEP13_T_LEN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 UEP13_T_LEN

UEP13_T_LEN : endpoint 13 send the length
bits : 0 - 10 (11 bit)
access : read-write


UEP13_T_CTRL

endpoint 13 send control
address_offset : 0x10E Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

UEP13_T_CTRL UEP13_T_CTRL read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 MASK_UEP_T_RES MASK_UEP_T_TOG bUEP_T_TOG_AUTO

MASK_UEP_T_RES : endpoint 13 control of the send response to IN transactions
bits : 0 - 1 (2 bit)
access : read-write

MASK_UEP_T_TOG : endpoint 13 synchronous trigger bit for the sender to prepare
bits : 3 - 4 (2 bit)
access : read-write

bUEP_T_TOG_AUTO : endpoint 13 synchronous trigger bit automatic filp enables the control bit
bits : 5 - 5 (1 bit)
access : read-write


UEP13_R_CTRL

endpoint 13 send control
address_offset : 0x10F Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

UEP13_R_CTRL UEP13_R_CTRL read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 MASK_UEP_R_RES MASK_UEP_R_TOG bUEP_R_TOG_AUTO

MASK_UEP_R_RES : endpoint 13 control of the accept response to OUT transactions
bits : 0 - 1 (2 bit)
access : read-write

MASK_UEP_R_TOG : endpoint 13 synchronous trigger bit for the accept to prepare
bits : 3 - 4 (2 bit)
access : read-write

bUEP_R_TOG_AUTO : endpoint 13 synchronous trigger bit automatic filp enables the control bit
bits : 5 - 5 (1 bit)
access : read-only


UEP14_T_LEN

endpoint 14 send the length
address_offset : 0x110 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

UEP14_T_LEN UEP14_T_LEN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 UEP14_T_LEN

UEP14_T_LEN : endpoint 14 send the length
bits : 0 - 10 (11 bit)
access : read-write


UEP14_T_CTRL

endpoint 14 send control
address_offset : 0x112 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

UEP14_T_CTRL UEP14_T_CTRL read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 MASK_UEP_T_RES MASK_UEP_T_TOG bUEP_T_TOG_AUTO

MASK_UEP_T_RES : endpoint 14 control of the send response to IN transactions
bits : 0 - 1 (2 bit)
access : read-write

MASK_UEP_T_TOG : endpoint 14 synchronous trigger bit for the sender to prepare
bits : 3 - 4 (2 bit)
access : read-write

bUEP_T_TOG_AUTO : endpoint 14 synchronous trigger bit automatic filp enables the control bit
bits : 5 - 5 (1 bit)
access : read-write


UEP14_R_CTRL

endpoint 14 send control
address_offset : 0x113 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

UEP14_R_CTRL UEP14_R_CTRL read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 MASK_UEP_R_RES MASK_UEP_R_TOG bUEP_R_TOG_AUTO

MASK_UEP_R_RES : endpoint 14 control of the accept response to OUT transactions
bits : 0 - 1 (2 bit)
access : read-write

MASK_UEP_R_TOG : endpoint 14 synchronous trigger bit for the accept to prepare
bits : 3 - 4 (2 bit)
access : read-write

bUEP_R_TOG_AUTO : endpoint 14 synchronous trigger bit automatic filp enables the control bit
bits : 5 - 5 (1 bit)
access : read-only


UEP15_T_LEN

endpoint 15 send the length
address_offset : 0x114 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

UEP15_T_LEN UEP15_T_LEN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 UEP0_T_LEN

UEP0_T_LEN : endpoint 15 send the length
bits : 0 - 10 (11 bit)
access : read-write


UEP15_T_CTRL

endpoint 15 send control
address_offset : 0x116 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

UEP15_T_CTRL UEP15_T_CTRL read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 MASK_UEP_T_RES MASK_UEP_T_TOG bUEP_T_TOG_AUTO

MASK_UEP_T_RES : endpoint 15 control of the send response to IN transactions
bits : 0 - 1 (2 bit)
access : read-write

MASK_UEP_T_TOG : endpoint 15 synchronous trigger bit for the sender to prepare
bits : 3 - 4 (2 bit)
access : read-write

bUEP_T_TOG_AUTO : endpoint 15 synchronous trigger bit automatic filp enables the control bit
bits : 5 - 5 (1 bit)
access : read-write


UEP15_R_CTRL

endpoint 15 send control
address_offset : 0x117 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

UEP15_R_CTRL UEP15_R_CTRL read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 MASK_UEP_R_RES MASK_UEP_R_TOG bUEP_R_TOG_AUTO

MASK_UEP_R_RES : endpoint 15 control of the accept response to OUT transactions
bits : 0 - 1 (2 bit)
access : read-write

MASK_UEP_R_TOG : endpoint 15 synchronous trigger bit for the accept to prepare
bits : 3 - 4 (2 bit)
access : read-write

bUEP_R_TOG_AUTO : endpoint 15 synchronous trigger bit automatic filp enables the control bit
bits : 5 - 5 (1 bit)
access : read-only


UEP_TYPE

USB endpoint type
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

UEP_TYPE UEP_TYPE read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bUEP_T_TYPE bUEP_R_TYPE

bUEP_T_TYPE : endpoint TX type
bits : 1 - 15 (15 bit)
access : read-write

bUEP_R_TYPE : endpoint RX type
bits : 17 - 31 (15 bit)
access : read-write


UEP_BUF_MOD

USB endpoint buffer mode
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

UEP_BUF_MOD UEP_BUF_MOD read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bUEP_BUF_MOD bUEP_ISO_BUF_MOD

bUEP_BUF_MOD : buffer mode of USB endpoint
bits : 0 - 15 (16 bit)
access : read-write

bUEP_ISO_BUF_MOD : buffer mode of USB endpoint
bits : 16 - 31 (16 bit)
access : read-write


UEP0_DMA

B endpoint 0 DMA buffer address
address_offset : 0x1C Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

UEP0_DMA UEP0_DMA read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 UEP0_DMA

UEP0_DMA : endpoint 0 DMA buffer address
bits : 0 - 15 (16 bit)
access : read-write


USB_INT_EN

USB interrupt enable
address_offset : 0x2 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USB_INT_EN USB_INT_EN read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 RB_UIE_BUS_RST__RB_UIE_DETECT RB_UIE_TRANSFER RB_UIE_SUSPEND RB_UIE_SOF_ACT RB_UIE_FIFO_OV RB_UIE_SETUP_ACT RB_UIE_ISO_ACT RB_UIE_DEV_NAK

RB_UIE_BUS_RST__RB_UIE_DETECT : enable interrupt for USB bus reset event for USB device mode enable interrupt for USB device detected event for USB host mode
bits : 0 - 0 (1 bit)

RB_UIE_TRANSFER : enable interrupt for USB transfer completion
bits : 1 - 1 (1 bit)

RB_UIE_SUSPEND : enable interrupt for USB suspend or resume event
bits : 2 - 2 (1 bit)

RB_UIE_SOF_ACT : indicate host SOF timer action status for USB host
bits : 3 - 3 (1 bit)

RB_UIE_FIFO_OV : enable interrupt for FIFO overflow
bits : 4 - 4 (1 bit)

RB_UIE_SETUP_ACT : indicate host SETUP timer action status for USB host
bits : 5 - 5 (1 bit)

RB_UIE_ISO_ACT : enable interrupt for NAK responded for USB device mode
bits : 6 - 6 (1 bit)

RB_UIE_DEV_NAK : enable interrupt for NAK responded for USB device mode
bits : 7 - 7 (1 bit)


UEP1_RX_DMA

endpoint 1 DMA RX buffer address
address_offset : 0x20 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

UEP1_RX_DMA UEP1_RX_DMA read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 UEP1_RX_DMA

UEP1_RX_DMA : endpoint 1 DMA buffer address
bits : 0 - 15 (16 bit)
access : read-write


UEP2_RX_DMA__UH_RX_DMA

endpoint 2 DMA RX buffer address/UH_RX_DMA
address_offset : 0x24 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

UEP2_RX_DMA__UH_RX_DMA UEP2_RX_DMA__UH_RX_DMA read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 UEP2_RX_DMA__UH_RX_DMA

UEP2_RX_DMA__UH_RX_DMA : endpoint 2 DMA buffer address
bits : 0 - 15 (16 bit)
access : read-write


UEP3_RX_DMA

endpoint 3 DMA RX buffer address
address_offset : 0x28 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

UEP3_RX_DMA UEP3_RX_DMA read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 UEP3_RX_DMA

UEP3_RX_DMA : endpoint 3 DMA buffer address
bits : 0 - 15 (16 bit)
access : read-write


UEP4_RX_DMA

endpoint 4 DMA RX buffer address
address_offset : 0x2C Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

UEP4_RX_DMA UEP4_RX_DMA read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 UEP4_RX_DMA

UEP4_RX_DMA : endpoint 4 DMA buffer address
bits : 0 - 15 (16 bit)
access : read-write


USB_DEV_AD

USB device address
address_offset : 0x3 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USB_DEV_AD USB_DEV_AD read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 MASK_USB_ADDR RB_UDA_GP_BIT

MASK_USB_ADDR : bit mask for USB device address
bits : 0 - 6 (7 bit)

RB_UDA_GP_BIT : general purpose bit
bits : 7 - 7 (1 bit)


UEP5_RX_DMA

endpoint 5 DMA RX buffer address
address_offset : 0x30 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

UEP5_RX_DMA UEP5_RX_DMA read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 UEP5_DMA

UEP5_DMA : endpoint 5 DMA buffer address
bits : 0 - 15 (16 bit)
access : read-write


UEP6_RX_DMA

endpoint 6 DMA RX buffer address
address_offset : 0x34 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

UEP6_RX_DMA UEP6_RX_DMA read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 UEP6_RX_DMA

UEP6_RX_DMA : endpoint 6 DMA buffer address
bits : 0 - 15 (16 bit)
access : read-write


UEP7_RX_DMA

endpoint 7 DMA RX buffer address
address_offset : 0x38 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

UEP7_RX_DMA UEP7_RX_DMA read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 UEP7_RX_DMA

UEP7_RX_DMA : endpoint 7 DMA buffer address
bits : 0 - 15 (16 bit)
access : read-write


UEP8_RX_DMA

endpoint 8 DMA RX buffer address
address_offset : 0x3C Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

UEP8_RX_DMA UEP8_RX_DMA read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 UEP8_RX_DMA

UEP8_RX_DMA : endpoint 8 DMA buffer address
bits : 0 - 15 (16 bit)
access : read-write


USB_FRAME_NO

USB_FRAME_NO
address_offset : 0x4 Bytes (0x0)
size : 16 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

USB_FRAME_NO USB_FRAME_NO read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 USB_FRAME_NO

USB_FRAME_NO : USB_FRAME_NO
bits : 0 - 15 (16 bit)


UEP9_RX_DMA

endpoint 9 DMA RX buffer address
address_offset : 0x40 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

UEP9_RX_DMA UEP9_RX_DMA read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 UEP9_RX_DMA

UEP9_RX_DMA : endpoint 9 DMA buffer address
bits : 0 - 15 (16 bit)
access : read-write


UEP10_RX_DMA

endpoint 10 DMA RX buffer address
address_offset : 0x44 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

UEP10_RX_DMA UEP10_RX_DMA read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 UEP10_RX_DMA

UEP10_RX_DMA : endpoint 10 DMA buffer address
bits : 0 - 15 (16 bit)
access : read-write


UEP11_RX_DMA

endpoint 11 DMA RX buffer address
address_offset : 0x48 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

UEP11_RX_DMA UEP11_RX_DMA read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 UEP11_RX_DMA

UEP11_RX_DMA : endpoint 11 DMA buffer address
bits : 0 - 15 (16 bit)
access : read-write


UEP12_RX_DMA

endpoint 12 DMA RX buffer address
address_offset : 0x4C Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

UEP12_RX_DMA UEP12_RX_DMA read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 UEP12_RX_DMA

UEP12_RX_DMA : endpoint 12 DMA buffer address
bits : 0 - 15 (16 bit)
access : read-write


UEP13_RX_DMA

endpoint 13 DMA RX buffer address
address_offset : 0x50 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

UEP13_RX_DMA UEP13_RX_DMA read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 UEP13_RX_DMA

UEP13_RX_DMA : endpoint 13 DMA buffer address
bits : 0 - 15 (16 bit)
access : read-write


UEP14_RX_DMA

endpoint 14 DMA RX buffer address
address_offset : 0x54 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

UEP14_RX_DMA UEP14_RX_DMA read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 UEP14_RX_DMA

UEP14_RX_DMA : endpoint 14 DMA buffer address
bits : 0 - 15 (16 bit)
access : read-write


UEP15_RX_DMA

endpoint 15 DMA RX buffer address
address_offset : 0x58 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

UEP15_RX_DMA UEP15_RX_DMA read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 UEP15_RX_DMA

UEP15_RX_DMA : endpoint 15 DMA buffer address
bits : 0 - 15 (16 bit)
access : read-write


UEP1_TX_DMA

endpoint 1 DMA TX buffer address
address_offset : 0x5C Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

UEP1_TX_DMA UEP1_TX_DMA read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 UEP1_TX_DMA

UEP1_TX_DMA : endpoint 1 DMA buffer address
bits : 0 - 15 (16 bit)
access : read-write


USB_USB_SUSPEND

indicate USB suspend status
address_offset : 0x6 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USB_USB_SUSPEND USB_USB_SUSPEND read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 USB_SYS_MOD USB_WAKEUP USB_LINESTATE

USB_SYS_MOD : USB_SYS_MOD
bits : 0 - 1 (2 bit)

USB_WAKEUP : remote resume
bits : 2 - 2 (1 bit)

USB_LINESTATE : USB_LINESTATE
bits : 4 - 5 (2 bit)


UEP2_TX_DMA

endpoint 2 DMA TX buffer address
address_offset : 0x60 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

UEP2_TX_DMA UEP2_TX_DMA read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 UEP2_TX_DMA

UEP2_TX_DMA : endpoint 2 DMA buffer address
bits : 0 - 15 (16 bit)
access : read-write


UEP3_TX_DMA__UH_TX_DMA

endpoint 3 DMA TX buffer address
address_offset : 0x64 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

UEP3_TX_DMA__UH_TX_DMA UEP3_TX_DMA__UH_TX_DMA read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 UEP3_TX_DMA__UH_TX_DMA

UEP3_TX_DMA__UH_TX_DMA : endpoint 3 DMA buffer address
bits : 0 - 15 (16 bit)
access : read-write


UEP4_TX_DMA

endpoint 4 DMA TX buffer address
address_offset : 0x68 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

UEP4_TX_DMA UEP4_TX_DMA read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 UEP4_TX_DMA

UEP4_TX_DMA : endpoint 4 DMA buffer address
bits : 0 - 15 (16 bit)
access : read-write


UEP5_TX_DMA

endpoint 5 DMA TX buffer address
address_offset : 0x6C Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

UEP5_TX_DMA UEP5_TX_DMA read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 UEP5_TX_DMA

UEP5_TX_DMA : endpoint 5 DMA buffer address
bits : 0 - 15 (16 bit)
access : read-write


UEP6_TX_DMA

endpoint 6 DMA TX buffer address
address_offset : 0x70 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

UEP6_TX_DMA UEP6_TX_DMA read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 UEP6_TX_DMA

UEP6_TX_DMA : endpoint 6 DMA buffer address
bits : 0 - 15 (16 bit)
access : read-write


UEP7_TX_DMA

endpoint 7 DMA TX buffer address
address_offset : 0x74 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

UEP7_TX_DMA UEP7_TX_DMA read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 UEP7_TX_DMA

UEP7_TX_DMA : endpoint 7 DMA buffer address
bits : 0 - 15 (16 bit)
access : read-write


UEP8_TX_DMA

endpoint 8 DMA TX buffer address
address_offset : 0x78 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

UEP8_TX_DMA UEP8_TX_DMA read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 UEP8_TX_DMA

UEP8_TX_DMA : endpoint 8 DMA buffer address
bits : 0 - 15 (16 bit)
access : read-write


UEP9_TX_DMA

endpoint 9 DMA TX buffer address
address_offset : 0x7C Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

UEP9_TX_DMA UEP9_TX_DMA read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 UEP9_TX_DMA

UEP9_TX_DMA : endpoint 9 DMA buffer address
bits : 0 - 15 (16 bit)
access : read-write


USB_SPEED_TYPE

USB_SPEED_TYPE
address_offset : 0x8 Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

USB_SPEED_TYPE USB_SPEED_TYPE read-only 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 USB_SPEED_TYPE

USB_SPEED_TYPE : USB_SPEED_TYPE
bits : 0 - 1 (2 bit)


UEP10_TX_DMA

endpoint 10 DMA TX buffer address
address_offset : 0x80 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

UEP10_TX_DMA UEP10_TX_DMA read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 UEP10_TX_DMA

UEP10_TX_DMA : endpoint 10 DMA buffer address
bits : 0 - 15 (16 bit)
access : read-write


UEP11_TX_DMA

endpoint 11 DMA TX buffer address
address_offset : 0x84 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

UEP11_TX_DMA UEP11_TX_DMA read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 UEP11_TX_DMA

UEP11_TX_DMA : endpoint 11 DMA buffer address
bits : 0 - 15 (16 bit)
access : read-write


UEP12_TX_DMA____UH_SPLIT_DATA

endpoint 12 DMA TX buffer address
address_offset : 0x88 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

UEP12_TX_DMA____UH_SPLIT_DATA UEP12_TX_DMA____UH_SPLIT_DATA read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 UEP12_TX_DMA___UH_SPLIT_DATA

UEP12_TX_DMA___UH_SPLIT_DATA : endpoint 12 DMA buffer address
bits : 0 - 15 (16 bit)
access : read-write


UEP13_TX_DMA

endpoint 13 DMA TX buffer address
address_offset : 0x8C Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

UEP13_TX_DMA UEP13_TX_DMA read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 UEP13_TX_DMA

UEP13_TX_DMA : endpoint 13 DMA buffer address
bits : 0 - 15 (16 bit)
access : read-write


USB_MIS_ST

USB miscellaneous status
address_offset : 0x9 Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

USB_MIS_ST USB_MIS_ST read-only 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 RB_UMS_SPLIT_CAN RB_UMS_ATTACH RB_UMS_SUSPEND RB_UMS_BUS_RESET RB_UMS_R_FIFO_RDY RB_UMS_SIE_FREE RB_UMS_SOF_ACT RB_UMS_SOF_PRES

RB_UMS_SPLIT_CAN : RO, indicate device attached status on USB host
bits : 0 - 0 (1 bit)

RB_UMS_ATTACH : RO, indicate UDM level saved at device attached to USB host
bits : 1 - 1 (1 bit)

RB_UMS_SUSPEND : RO, indicate USB suspend status
bits : 2 - 2 (1 bit)

RB_UMS_BUS_RESET : RO, indicate USB bus reset status
bits : 3 - 3 (1 bit)

RB_UMS_R_FIFO_RDY : RO, indicate USB receiving FIFO ready status (not empty)
bits : 4 - 4 (1 bit)

RB_UMS_SIE_FREE : RO, indicate USB SIE free status
bits : 5 - 5 (1 bit)

RB_UMS_SOF_ACT : RO, indicate host SOF timer action status for USB host
bits : 6 - 6 (1 bit)

RB_UMS_SOF_PRES : RO, indicate host SOF timer presage status
bits : 7 - 7 (1 bit)


UEP14_TX_DMA

endpoint 14 DMA TX buffer address
address_offset : 0x90 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

UEP14_TX_DMA UEP14_TX_DMA read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 UEP14_TX_DMA

UEP14_TX_DMA : endpoint 14 DMA buffer address
bits : 0 - 15 (16 bit)
access : read-write


UEP15_TX_DMA

endpoint 15 DMA TX buffer address
address_offset : 0x94 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

UEP15_TX_DMA UEP15_TX_DMA read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 UEP15_TX_DMA

UEP15_TX_DMA : endpoint 15 DMA buffer address
bits : 0 - 15 (16 bit)
access : read-write


UEP0_MAX_LEN

endpoint 0 max acceptable length
address_offset : 0x98 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

UEP0_MAX_LEN UEP0_MAX_LEN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 UEP0_MAX_LEN

UEP0_MAX_LEN : endpoint 0 max acceptable length
bits : 0 - 10 (11 bit)
access : read-write


UEP1_MAX_LEN

endpoint 1 max acceptable length
address_offset : 0x9C Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

UEP1_MAX_LEN UEP1_MAX_LEN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 UEP1_MAX_LEN

UEP1_MAX_LEN : endpoint 1 max acceptable length
bits : 0 - 10 (11 bit)
access : read-write


USB_INT_FG

USB interrupt flag
address_offset : 0xA Bytes (0x0)
size : 8 bit
reset_value : 0x0
reset_Mask : 0x0

USB_INT_FG USB_INT_FG 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 RB_UIF_BUS_RST RB_UIF_TRANSFER RB_UIF_SUSPEND RB_UIF_HST_SOF RB_UIF_FIFO_OV RB_U_SETUP_ACT UIF_ISO_ACT RB_U_IS_NAK

RB_UIF_BUS_RST : RB_UIF_BUS_RST
bits : 0 - 0 (1 bit)
access : read-write

RB_UIF_TRANSFER : USB transfer completion interrupt flag, direct bit address clear or write 1 to clear
bits : 1 - 1 (1 bit)
access : read-write

RB_UIF_SUSPEND : USB suspend or resume event interrupt flag, direct bit address clear or write 1 to clear
bits : 2 - 2 (1 bit)
access : read-write

RB_UIF_HST_SOF : host SOF timer interrupt flag for USB host, direct bit address clear or write 1 to clear
bits : 3 - 3 (1 bit)
access : read-write

RB_UIF_FIFO_OV : FIFO overflow interrupt flag for USB, direct bit address clear or write 1 to clear
bits : 4 - 4 (1 bit)
access : read-write

RB_U_SETUP_ACT : USB_SETUP_ACT
bits : 5 - 5 (1 bit)
access : read-only

UIF_ISO_ACT : UIF_ISO_ACT
bits : 6 - 6 (1 bit)
access : read-only

RB_U_IS_NAK : RO, indicate current USB transfer is NAK received
bits : 7 - 7 (1 bit)
access : read-only


UEP2_MAX_LEN__UH_RX_MAX_LEN

endpoint 2 max acceptable length
address_offset : 0xA0 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

UEP2_MAX_LEN__UH_RX_MAX_LEN UEP2_MAX_LEN__UH_RX_MAX_LEN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 UEP2_MAX_LEN__UH_RX_MAX_LEN

UEP2_MAX_LEN__UH_RX_MAX_LEN : endpoint 2 max acceptable length
bits : 0 - 10 (11 bit)
access : read-write


UEP3_MAX_LEN

endpoint 3 MAX_LEN TX
address_offset : 0xA4 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

UEP3_MAX_LEN UEP3_MAX_LEN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 UEP3_MAX_LEN

UEP3_MAX_LEN : endpoint 3 max acceptable length
bits : 0 - 10 (11 bit)
access : read-write


UEP4_MAX_LEN

endpoint 4 max acceptable length
address_offset : 0xA8 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

UEP4_MAX_LEN UEP4_MAX_LEN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 UEP4_MAX_LEN

UEP4_MAX_LEN : endpoint 4 max acceptable length
bits : 0 - 10 (11 bit)
access : read-write


UEP5_MAX_LEN

endpoint 5 max acceptable length
address_offset : 0xAC Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

UEP5_MAX_LEN UEP5_MAX_LEN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 UEP5_MAX_LEN

UEP5_MAX_LEN : endpoint 5 max acceptable length
bits : 0 - 10 (11 bit)
access : read-write


USB_INT_ST

USB interrupt status
address_offset : 0xB Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

USB_INT_ST USB_INT_ST read-only 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 MASK_UIS_H_RES__MASK_UIS_ENDP MASK_UIS_TOKEN RB_UIS_TOG_OK RB_UIS_IS_NAK

MASK_UIS_H_RES__MASK_UIS_ENDP : RO, bit mask of current transfer handshake response for USB host mode: 0000=no response, time out from device, others=handshake response PID received RO, bit mask of current transfer endpoint number for USB device mode
bits : 0 - 3 (4 bit)

MASK_UIS_TOKEN : RO, bit mask of current token PID code received for USB device mode
bits : 4 - 5 (2 bit)

RB_UIS_TOG_OK : RO, indicate current USB transfer toggle is OK
bits : 6 - 6 (1 bit)

RB_UIS_IS_NAK : RO, indicate current USB transfer is NAK received for USB device mode
bits : 7 - 7 (1 bit)


UEP6_MAX_LEN

endpoint 6 max acceptable length
address_offset : 0xB0 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

UEP6_MAX_LEN UEP6_MAX_LEN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 UEP6_MAX_LEN

UEP6_MAX_LEN : endpoint 6 max acceptable length
bits : 0 - 10 (11 bit)
access : read-write


UEP7_MAX_LEN

endpoint 7 max acceptable length
address_offset : 0xB4 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

UEP7_MAX_LEN UEP7_MAX_LEN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 UEP7_MAX_LEN

UEP7_MAX_LEN : endpoint 7 max acceptable length
bits : 0 - 10 (11 bit)
access : read-write


UEP8_MAX_LEN

endpoint 8 max acceptable length
address_offset : 0xB8 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

UEP8_MAX_LEN UEP8_MAX_LEN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 UEP8_MAX_LEN

UEP8_MAX_LEN : endpoint 8 max acceptable length
bits : 0 - 10 (11 bit)
access : read-write


UEP9_MAX_LEN

endpoint 9 max acceptable length
address_offset : 0xBC Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

UEP9_MAX_LEN UEP9_MAX_LEN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 UEP9_MAX_LEN

UEP9_MAX_LEN : endpoint 9 max acceptable length
bits : 0 - 10 (11 bit)
access : read-write


USB_RX_LEN

USB receiving length
address_offset : 0xC Bytes (0x0)
size : 16 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

USB_RX_LEN USB_RX_LEN read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R16_USB_RX_LEN

R16_USB_RX_LEN : length of received bytes
bits : 0 - 15 (16 bit)


UEP10_MAX_LEN

endpoint 10 max acceptable length
address_offset : 0xC0 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

UEP10_MAX_LEN UEP10_MAX_LEN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 UEP10_MAX_LEN

UEP10_MAX_LEN : endpoint 10 max acceptable length
bits : 0 - 10 (11 bit)
access : read-write


UEP11_MAX_LEN

endpoint 11 max acceptable length
address_offset : 0xC4 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

UEP11_MAX_LEN UEP11_MAX_LEN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 UEP11_MAX_LEN

UEP11_MAX_LEN : endpoint 11 max acceptable length
bits : 0 - 10 (11 bit)
access : read-write


UEP12_MAX_LEN

endpoint 12 max acceptable length
address_offset : 0xC8 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

UEP12_MAX_LEN UEP12_MAX_LEN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 UEP12_MAX_LEN

UEP12_MAX_LEN : endpoint 12 max acceptable length
bits : 0 - 10 (11 bit)
access : read-write


UEP13_MAX_LEN

endpoint 13 max acceptable length
address_offset : 0xCC Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

UEP13_MAX_LEN UEP13_MAX_LEN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 UEP13_MAX_LEN

UEP13_MAX_LEN : endpoint 13 max acceptable length
bits : 0 - 10 (11 bit)
access : read-write


UEP14_MAX_LEN

endpoint 14 max acceptable length
address_offset : 0xD0 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

UEP14_MAX_LEN UEP14_MAX_LEN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 UEP14_MAX_LEN

UEP14_MAX_LEN : endpoint 14 max acceptable length
bits : 0 - 10 (11 bit)
access : read-write


UEP15_MAX_LEN

endpoint 15 max acceptable length
address_offset : 0xD4 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

UEP15_MAX_LEN UEP15_MAX_LEN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 UEP15_MAX_LEN

UEP15_MAX_LEN : endpoint 15 max acceptable length
bits : 0 - 10 (11 bit)
access : read-write


UEP0_T_LEN

endpoint 0 send the length
address_offset : 0xD8 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

UEP0_T_LEN UEP0_T_LEN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 UEP0_T_LEN

UEP0_T_LEN : endpoint 0 send the length
bits : 0 - 10 (11 bit)
access : read-write


UEP0_T_CTRL

endpoint 0 send control
address_offset : 0xDA Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

UEP0_T_CTRL UEP0_T_CTRL read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 MASK_UEP_T_RES MASK_UEP_T_TOG bUEP_T_TOG_AUTO

MASK_UEP_T_RES : endpoint 0 control of the send response to IN transactions
bits : 0 - 1 (2 bit)
access : read-write

MASK_UEP_T_TOG : endpoint 0 synchronous trigger bit for the sender to prepare
bits : 3 - 4 (2 bit)
access : read-write

bUEP_T_TOG_AUTO : endpoint 0 synchronous trigger bit automatic filp enables the control bit
bits : 5 - 5 (1 bit)
access : read-write


UEP0_R_CTRL

endpoint 0 send control
address_offset : 0xDB Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

UEP0_R_CTRL UEP0_R_CTRL read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 MASK_UEP_R_RES MASK_UEP_R_TOG bUEP_R_TOG_AUTO

MASK_UEP_R_RES : endpoint 0 control of the accept response to OUT transactions
bits : 0 - 1 (2 bit)
access : read-write

MASK_UEP_R_TOG : endpoint 0 synchronous trigger bit for the accept to prepare
bits : 3 - 4 (2 bit)
access : read-write

bUEP_R_TOG_AUTO : endpoint 0 synchronous trigger bit automatic filp enables the control bit
bits : 5 - 5 (1 bit)
access : read-only


UEP1_T_LEN

endpoint 1 send the length
address_offset : 0xDC Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

UEP1_T_LEN UEP1_T_LEN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 UEP1_T_LEN

UEP1_T_LEN : endpoint 1 send the length
bits : 0 - 10 (11 bit)
access : read-write


UEP1_T_CTRL

endpoint 1 send control
address_offset : 0xDE Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

UEP1_T_CTRL UEP1_T_CTRL read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 MASK_UEP_T_RES MASK_UEP_T_TOG bUEP_T_TOG_AUTO

MASK_UEP_T_RES : endpoint 1 control of the send response to IN transactions
bits : 0 - 1 (2 bit)
access : read-write

MASK_UEP_T_TOG : endpoint 1 synchronous trigger bit for the sender to prepare
bits : 3 - 4 (2 bit)
access : read-write

bUEP_T_TOG_AUTO : endpoint 1 synchronous trigger bit automatic filp enables the control bit
bits : 5 - 5 (1 bit)
access : read-write


UEP1_R_CTRL

endpoint 1 send control
address_offset : 0xDF Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

UEP1_R_CTRL UEP1_R_CTRL read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 MASK_UEP_R_RES MASK_UEP_R_TOG bUEP_R_TOG_AUTO

MASK_UEP_R_RES : endpoint 1 control of the accept response to OUT transactions
bits : 0 - 1 (2 bit)
access : read-write

MASK_UEP_R_TOG : endpoint 1 synchronous trigger bit for the accept to prepare
bits : 3 - 4 (2 bit)
access : read-write

bUEP_R_TOG_AUTO : endpoint 1 synchronous trigger bit automatic filp enables the control bit
bits : 5 - 5 (1 bit)
access : read-only


UEP2_T_LEN__UH_EP_PID

endpoint 2 send the length
address_offset : 0xE0 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

UEP2_T_LEN__UH_EP_PID UEP2_T_LEN__UH_EP_PID read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 UEP2_T_LEN__MASK_UH_ENDP__MASK_UH_TOKEN

UEP2_T_LEN__MASK_UH_ENDP__MASK_UH_TOKEN : endpoint 2 send the length
bits : 0 - 10 (11 bit)
access : read-write


UEP2_T_CTRL

endpoint 2 send control
address_offset : 0xE2 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

UEP2_T_CTRL UEP2_T_CTRL read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 MASK_UEP_T_RES MASK_UEP_T_TOG bUEP_T_TOG_AUTO

MASK_UEP_T_RES : endpoint 2 control of the send response to IN transactions
bits : 0 - 1 (2 bit)
access : read-write

MASK_UEP_T_TOG : endpoint 2 synchronous trigger bit for the sender to prepare
bits : 3 - 4 (2 bit)
access : read-write

bUEP_T_TOG_AUTO : endpoint 2 synchronous trigger bit automatic filp enables the control bit
bits : 5 - 5 (1 bit)
access : read-write


UEP2_R_CTRL__UH_RX_CTRL

endpoint 2 send control
address_offset : 0xE3 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

UEP2_R_CTRL__UH_RX_CTRL UEP2_R_CTRL__UH_RX_CTRL read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 MASK_UEP_R_RES__MASK_UH_R_RES bUH_R_RES_NO MASK_UEP_R_TOG__MASK_UH_R_TOG bUEP_R_TOG_AUTO__bUH_R_AUTO_TOG bUH_R_DATA_NO

MASK_UEP_R_RES__MASK_UH_R_RES : endpoint 2 control of the accept response to OUT transactions
bits : 0 - 1 (2 bit)
access : read-write

bUH_R_RES_NO : bUH_R_RES_NO
bits : 2 - 2 (1 bit)
access : read-write

MASK_UEP_R_TOG__MASK_UH_R_TOG : endpoint 2 synchronous trigger bit for the accept to prepare
bits : 3 - 4 (2 bit)
access : read-write

bUEP_R_TOG_AUTO__bUH_R_AUTO_TOG : endpoint 2 synchronous trigger bit automatic filp enables the control bit
bits : 5 - 5 (1 bit)
access : read-only

bUH_R_DATA_NO : bUH_R_DATA_NO
bits : 6 - 6 (1 bit)
access : read-write


UEP3_T_LEN___UH_TX_LEN_H

endpoint 3 send the length
address_offset : 0xE4 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

UEP3_T_LEN___UH_TX_LEN_H UEP3_T_LEN___UH_TX_LEN_H read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 UEP3_T_LEN___UH_TX_LEN_H

UEP3_T_LEN___UH_TX_LEN_H : endpoint 3 send the length
bits : 0 - 10 (11 bit)
access : read-write


UEP3_T_CTRL___UH_TX_CTRL

endpoint 3 send control
address_offset : 0xE6 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

UEP3_T_CTRL___UH_TX_CTRL UEP3_T_CTRL___UH_TX_CTRL read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 MASK_UEP_T_RES_____MASK_UH_T_RES bUH_T_RES_NO MASK_UEP_T_TOG____MASK_UH_T_TOG bUEP_T_TOG_AUTO____bUH_T_AUTO_TOG bUH_T_DATA_NO

MASK_UEP_T_RES_____MASK_UH_T_RES : endpoint 3 control of the send response to IN transactions
bits : 0 - 1 (2 bit)
access : read-write

bUH_T_RES_NO : bUH_T_RES_NO
bits : 2 - 2 (1 bit)
access : read-write

MASK_UEP_T_TOG____MASK_UH_T_TOG : endpoint 3 synchronous trigger bit for the sender to prepare
bits : 3 - 4 (2 bit)
access : read-write

bUEP_T_TOG_AUTO____bUH_T_AUTO_TOG : endpoint 3 synchronous trigger bit automatic filp enables the control bit
bits : 5 - 5 (1 bit)
access : read-write

bUH_T_DATA_NO : bUH_T_DATA_NO
bits : 6 - 6 (1 bit)
access : read-write


UEP3_R_CTRL

endpoint 3 send control
address_offset : 0xE7 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

UEP3_R_CTRL UEP3_R_CTRL read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 MASK_UEP_R_RES MASK_UEP_R_TOG bUEP_R_TOG_AUTO

MASK_UEP_R_RES : endpoint 3 control of the accept response to OUT transactions
bits : 0 - 1 (2 bit)
access : read-write

MASK_UEP_R_TOG : endpoint 3 synchronous trigger bit for the accept to prepare
bits : 3 - 4 (2 bit)
access : read-write

bUEP_R_TOG_AUTO : endpoint 3 synchronous trigger bit automatic filp enables the control bit
bits : 5 - 5 (1 bit)
access : read-only


UEP4_T_LEN

endpoint 4 send the length
address_offset : 0xE8 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

UEP4_T_LEN UEP4_T_LEN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 UEP4_T_LEN

UEP4_T_LEN : endpoint 0 send the length
bits : 0 - 10 (11 bit)
access : read-write


UEP4_T_CTRL

endpoint 4 send control
address_offset : 0xEA Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

UEP4_T_CTRL UEP4_T_CTRL read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 MASK_UEP_T_RES MASK_UEP_T_TOG bUEP_T_TOG_AUTO

MASK_UEP_T_RES : endpoint 4 control of the send response to IN transactions
bits : 0 - 1 (2 bit)
access : read-write

MASK_UEP_T_TOG : endpoint 4 synchronous trigger bit for the sender to prepare
bits : 3 - 4 (2 bit)
access : read-write

bUEP_T_TOG_AUTO : endpoint 4 synchronous trigger bit automatic filp enables the control bit
bits : 5 - 5 (1 bit)
access : read-write


UEP4_R_CTRL

endpoint 4 send control
address_offset : 0xEB Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

UEP4_R_CTRL UEP4_R_CTRL read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 MASK_UEP_R_RES MASK_UEP_R_TOG bUEP_R_TOG_AUTO

MASK_UEP_R_RES : endpoint 4 control of the accept response to OUT transactions
bits : 0 - 1 (2 bit)
access : read-write

MASK_UEP_R_TOG : endpoint 4 synchronous trigger bit for the accept to prepare
bits : 3 - 4 (2 bit)
access : read-write

bUEP_R_TOG_AUTO : endpoint 4 synchronous trigger bit automatic filp enables the control bit
bits : 5 - 5 (1 bit)
access : read-only


UEP5_T_LEN

endpoint 5 send the length
address_offset : 0xEC Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

UEP5_T_LEN UEP5_T_LEN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 UEP5_T_LEN

UEP5_T_LEN : endpoint 5 send the length
bits : 0 - 10 (11 bit)
access : read-write


UEP5_T_CTRL

endpoint 5 send control
address_offset : 0xEE Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

UEP5_T_CTRL UEP5_T_CTRL read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 MASK_UEP_T_RES MASK_UEP_T_TOG bUEP_T_TOG_AUTO

MASK_UEP_T_RES : endpoint 5 control of the send response to IN transactions
bits : 0 - 1 (2 bit)
access : read-write

MASK_UEP_T_TOG : endpoint 5 synchronous trigger bit for the sender to prepare
bits : 3 - 4 (2 bit)
access : read-write

bUEP_T_TOG_AUTO : endpoint 5 synchronous trigger bit automatic filp enables the control bit
bits : 5 - 5 (1 bit)
access : read-write


UEP5_R_CTRL

endpoint 5 send control
address_offset : 0xEF Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

UEP5_R_CTRL UEP5_R_CTRL read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 MASK_UEP_R_RES MASK_UEP_R_TOG bUEP_R_TOG_AUTO

MASK_UEP_R_RES : endpoint 5 control of the accept response to OUT transactions
bits : 0 - 1 (2 bit)
access : read-write

MASK_UEP_R_TOG : endpoint 5 synchronous trigger bit for the accept to prepare
bits : 3 - 4 (2 bit)
access : read-write

bUEP_R_TOG_AUTO : endpoint 5 synchronous trigger bit automatic filp enables the control bit
bits : 5 - 5 (1 bit)
access : read-only


UEP6_T_LEN

endpoint 6 send the length
address_offset : 0xF0 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

UEP6_T_LEN UEP6_T_LEN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 UEP6_T_LEN

UEP6_T_LEN : endpoint 6 send the length
bits : 0 - 10 (11 bit)
access : read-write


UEP6_T_CTRL

endpoint 6 send control
address_offset : 0xF2 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

UEP6_T_CTRL UEP6_T_CTRL read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 MASK_UEP_T_RES MASK_UEP_T_TOG bUEP_T_TOG_AUTO

MASK_UEP_T_RES : endpoint 6 control of the send response to IN transactions
bits : 0 - 1 (2 bit)
access : read-write

MASK_UEP_T_TOG : endpoint 6 synchronous trigger bit for the sender to prepare
bits : 3 - 4 (2 bit)
access : read-write

bUEP_T_TOG_AUTO : endpoint 6 synchronous trigger bit automatic filp enables the control bit
bits : 5 - 5 (1 bit)
access : read-write


UEP6_R_CTRL

endpoint 6 send control
address_offset : 0xF3 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

UEP6_R_CTRL UEP6_R_CTRL read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 MASK_UEP_R_RES MASK_UEP_R_TOG bUEP_R_TOG_AUTO

MASK_UEP_R_RES : endpoint 6 control of the accept response to OUT transactions
bits : 0 - 1 (2 bit)
access : read-write

MASK_UEP_R_TOG : endpoint 6 synchronous trigger bit for the accept to prepare
bits : 3 - 4 (2 bit)
access : read-write

bUEP_R_TOG_AUTO : endpoint 6 synchronous trigger bit automatic filp enables the control bit
bits : 5 - 5 (1 bit)
access : read-only


UEP7_T_LEN

endpoint 7 send the length
address_offset : 0xF4 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

UEP7_T_LEN UEP7_T_LEN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 UEP7_T_LEN

UEP7_T_LEN : endpoint 7 send the length
bits : 0 - 10 (11 bit)
access : read-write


UEP7_T_CTRL

endpoint 7 send control
address_offset : 0xF6 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

UEP7_T_CTRL UEP7_T_CTRL read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 MASK_UEP_T_RES MASK_UEP_T_TOG bUEP_T_TOG_AUTO

MASK_UEP_T_RES : endpoint 7 control of the send response to IN transactions
bits : 0 - 1 (2 bit)
access : read-write

MASK_UEP_T_TOG : endpoint 7 synchronous trigger bit for the sender to prepare
bits : 3 - 4 (2 bit)
access : read-write

bUEP_T_TOG_AUTO : endpoint 7 synchronous trigger bit automatic filp enables the control bit
bits : 5 - 5 (1 bit)
access : read-write


UEP7_R_CTRL

endpoint 7 send control
address_offset : 0xF7 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

UEP7_R_CTRL UEP7_R_CTRL read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 MASK_UEP_R_RES MASK_UEP_R_TOG bUEP_R_TOG_AUTO

MASK_UEP_R_RES : endpoint 7 control of the accept response to OUT transactions
bits : 0 - 1 (2 bit)
access : read-write

MASK_UEP_R_TOG : endpoint 7 synchronous trigger bit for the accept to prepare
bits : 3 - 4 (2 bit)
access : read-write

bUEP_R_TOG_AUTO : endpoint 7 synchronous trigger bit automatic filp enables the control bit
bits : 5 - 5 (1 bit)
access : read-only


UEP8_T_LEN

endpoint 8 send the length
address_offset : 0xF8 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

UEP8_T_LEN UEP8_T_LEN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 UEP8_T_LEN

UEP8_T_LEN : endpoint 8 send the length
bits : 0 - 10 (11 bit)
access : read-write


UEP8_T_CTRL

endpoint 8 send control
address_offset : 0xFA Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

UEP8_T_CTRL UEP8_T_CTRL read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 MASK_UEP_T_RES MASK_UEP_T_TOG bUEP_T_TOG_AUTO

MASK_UEP_T_RES : endpoint 8 control of the send response to IN transactions
bits : 0 - 1 (2 bit)
access : read-write

MASK_UEP_T_TOG : endpoint 8 synchronous trigger bit for the sender to prepare
bits : 3 - 4 (2 bit)
access : read-write

bUEP_T_TOG_AUTO : endpoint 8 synchronous trigger bit automatic filp enables the control bit
bits : 5 - 5 (1 bit)
access : read-write


UEP8_R_CTRL

endpoint 8 send control
address_offset : 0xFB Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

UEP8_R_CTRL UEP8_R_CTRL read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 MASK_UEP_R_RES MASK_UEP_R_TOG bUEP_R_TOG_AUTO

MASK_UEP_R_RES : endpoint 8 control of the accept response to OUT transactions
bits : 0 - 1 (2 bit)
access : read-write

MASK_UEP_R_TOG : endpoint 8 synchronous trigger bit for the accept to prepare
bits : 3 - 4 (2 bit)
access : read-write

bUEP_R_TOG_AUTO : endpoint 8 synchronous trigger bit automatic filp enables the control bit
bits : 5 - 5 (1 bit)
access : read-only


UEP9_T_LEN

endpoint9 send the length
address_offset : 0xFC Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

UEP9_T_LEN UEP9_T_LEN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 UEP9_T_LEN

UEP9_T_LEN : endpoint 9 send the length
bits : 0 - 10 (11 bit)
access : read-write


UEP9_T_CTRL

endpoint 9 send control
address_offset : 0xFE Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

UEP9_T_CTRL UEP9_T_CTRL read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 MASK_UEP_T_RES MASK_UEP_T_TOG bUEP_T_TOG_AUTO

MASK_UEP_T_RES : endpoint 9 control of the send response to IN transactions
bits : 0 - 1 (2 bit)
access : read-write

MASK_UEP_T_TOG : endpoint 9 synchronous trigger bit for the sender to prepare
bits : 3 - 4 (2 bit)
access : read-write

bUEP_T_TOG_AUTO : endpoint 9 synchronous trigger bit automatic filp enables the control bit
bits : 5 - 5 (1 bit)
access : read-write


UEP9_R_CTRL

endpoint 9 send control
address_offset : 0xFF Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

UEP9_R_CTRL UEP9_R_CTRL read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 MASK_UEP_R_RES MASK_UEP_R_TOG bUEP_R_TOG_AUTO

MASK_UEP_R_RES : endpoint 9 control of the accept response to OUT transactions
bits : 0 - 1 (2 bit)
access : read-write

MASK_UEP_R_TOG : endpoint 9 synchronous trigger bit for the accept to prepare
bits : 3 - 4 (2 bit)
access : read-write

bUEP_R_TOG_AUTO : endpoint 9 synchronous trigger bit automatic filp enables the control bit
bits : 5 - 5 (1 bit)
access : read-only



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