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FLASH

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x400 byte (0x0)
mem_usage : registers
protection :

Registers

CTLR

ADDR

OBR

WPR

MODEKEYR

KEYR

OBKEYR

STATR


CTLR

Control register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CTLR CTLR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PG PER MER OBPG OBER STRT LOCK OBWRE ERRIE EOPIE FLOCK PAGE_PG PAGE_ER BER32 BER64 PGSTART RSENACT ENHANCEMODE SCKMODE

PG : Programming
bits : 0 - 0 (1 bit)

PER : Page Erase
bits : 1 - 1 (1 bit)

MER : Mass Erase
bits : 2 - 2 (1 bit)

OBPG : Option byte programming
bits : 4 - 4 (1 bit)

OBER : Option byte erase
bits : 5 - 5 (1 bit)

STRT : Start
bits : 6 - 6 (1 bit)

LOCK : Lock
bits : 7 - 7 (1 bit)

OBWRE : Option bytes write enable
bits : 9 - 9 (1 bit)

ERRIE : Error interrupt enable
bits : 10 - 10 (1 bit)

EOPIE : End of operation interrupt enable
bits : 12 - 12 (1 bit)

FLOCK : Fast programmable lock
bits : 15 - 15 (1 bit)

PAGE_PG : Fast programming
bits : 16 - 16 (1 bit)

PAGE_ER : Fast erase
bits : 17 - 17 (1 bit)

BER32 : Block Erase 32K
bits : 18 - 18 (1 bit)

BER64 : Block Erase 64K
bits : 19 - 19 (1 bit)

PGSTART : Page Programming Start
bits : 21 - 21 (1 bit)

RSENACT : Reset Flash Enhance read mode
bits : 22 - 22 (1 bit)

ENHANCEMODE : Flash Enhance read mode
bits : 24 - 24 (1 bit)

SCKMODE : Flash SCK mode
bits : 25 - 25 (1 bit)


ADDR

Flash address register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

ADDR ADDR write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FAR

FAR : Flash Address
bits : 0 - 31 (32 bit)


OBR

Option byte register
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

OBR OBR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OBERR RDPRT IWDG_SW STOP_RST STANDY_RST SRAM_CODE_MODE

OBERR : Option byte error
bits : 0 - 0 (1 bit)

RDPRT : Read protection
bits : 1 - 1 (1 bit)

IWDG_SW : IWDG_SW
bits : 2 - 2 (1 bit)

STOP_RST : STOP_RST
bits : 3 - 3 (1 bit)

STANDY_RST : STANDY_RST
bits : 4 - 4 (1 bit)

SRAM_CODE_MODE : SRAM_CODE_MODE
bits : 8 - 9 (2 bit)


WPR

Write protection register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

WPR WPR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WRP

WRP : Write protect
bits : 0 - 31 (32 bit)


MODEKEYR

Mode select register
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

MODEKEYR MODEKEYR write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MODEKEYR

MODEKEYR : Mode select
bits : 0 - 31 (32 bit)


KEYR

Flash key register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

KEYR KEYR write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 KEYR

KEYR : FPEC key
bits : 0 - 31 (32 bit)


OBKEYR

Flash option key register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

OBKEYR OBKEYR write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OPTKEY

OPTKEY : Option byte key
bits : 0 - 31 (32 bit)


STATR

Status register
address_offset : 0xC Bytes (0x0)
size : 32 bit
reset_value : 0x0
reset_Mask : 0x0

STATR STATR 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BSY WR_BSY WRPRTERR EOP ENHANCE_MOD_STA

BSY : Busy
bits : 0 - 0 (1 bit)
access : read-only

WR_BSY : Quick page programming
bits : 1 - 1 (1 bit)
access : read-only

WRPRTERR : Write protection error
bits : 4 - 4 (1 bit)
access : read-write

EOP : End of operation
bits : 5 - 5 (1 bit)
access : read-write

ENHANCE_MOD_STA : Enhance mode start
bits : 7 - 7 (1 bit)
access : read-only



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