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SYS

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x400 byte (0x0)
mem_usage : registers
protection :

Registers

R8_SAFE_ACCESS_SIG

R8_CHIP_ID

R8_XBUS_CONFIG

R8_PIN_ALTERNATE

R8_GPIO_INT_FLAG

R8_GPIO_INT_ENABLE

R8_GPIO_INT_MODE

R8_GPIO_INT_POLAR

R8_SAFE_ACCESS_ID

R16_SERD_ANA_CFG1

R32_SERD_ANA_CFG2

R8_WDOG_COUNT

R8_GLOB_ROM_CFG

R32_PA_DIR

R32_PA_PIN

R32_PA_OUT

R32_PA_CLR

R8_RST_BOOT_STAT

R32_PA_PU

R32_PA_PD

R32_PA_DRV

R32_PA_SMT

R8_RST_WDOG_CTRL

R32_PB_DIR

R32_PB_PIN

R32_PB_OUT

R32_PB_CLR

R8_GLOB_RESET_KEEP

R32_PB_PU

R32_PB_PD

R32_PB_DRV

R32_PB_SMT

R8_CLK_PLL_DIV

R8_CLK_CFG_CTRL

R8_CLK_MOD_AUX

R8_SLP_CLK_OFF0

R8_SLP_CLK_OFF1

R8_SLP_WAKE_CTRL

R8_SLP_POWER_CTRL


R8_SAFE_ACCESS_SIG

safe accessing sign register
address_offset : 0x0 Bytes (0x0)
size : 8 bit
reset_value : 0x0
reset_Mask : 0x0

R8_SAFE_ACCESS_SIG R8_SAFE_ACCESS_SIG 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 RB_SAFE_ACC_MODE RB_SAFE_ACC_TIMER

RB_SAFE_ACC_MODE : current safe accessing mode
bits : 0 - 1 (2 bit)
access : read-only

RB_SAFE_ACC_TIMER : safe accessing timer bit mask
bits : 4 - 6 (3 bit)
access : read-only


R8_CHIP_ID

chip ID register
address_offset : 0x1 Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

R8_CHIP_ID R8_CHIP_ID read-only 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 R8_CHIP_ID

R8_CHIP_ID : chip ID
bits : 0 - 7 (8 bit)


R8_XBUS_CONFIG

external bus configuration
address_offset : 0x10 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

R8_XBUS_CONFIG R8_XBUS_CONFIG read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 RB_XBUS_ENABLE RB_XBUS_ADDR_OE RB_XBUS_WIDTH RB_XBUS_HOLD RB_XBUS_SETUP

RB_XBUS_ENABLE : external bus enable
bits : 0 - 0 (1 bit)

RB_XBUS_ADDR_OE : external bus address output enable
bits : 2 - 3 (2 bit)

RB_XBUS_WIDTH : external bus access pulse width
bits : 4 - 5 (2 bit)

RB_XBUS_HOLD : external bus hold time
bits : 6 - 6 (1 bit)

RB_XBUS_SETUP : external bus setup time
bits : 7 - 7 (1 bit)


R8_PIN_ALTERNATE

alternate pin control
address_offset : 0x12 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

R8_PIN_ALTERNATE R8_PIN_ALTERNATE read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 RB_PIN_MII RB_PIN_TMR1 RB_PIN_TMR2 RB_PIN_UART0

RB_PIN_MII : ETH mii interface selection
bits : 0 - 0 (1 bit)

RB_PIN_TMR1 : TMR1 alternate pin enable
bits : 1 - 1 (1 bit)

RB_PIN_TMR2 : TMR2 alternate pin enable
bits : 2 - 2 (1 bit)

RB_PIN_UART0 : RXD0/TXD0 alternate pin enable
bits : 4 - 4 (1 bit)


R8_GPIO_INT_FLAG

GPIO interrupt control
address_offset : 0x1C Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

R8_GPIO_INT_FLAG R8_GPIO_INT_FLAG read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 RB_GPIO_PB15_IF

RB_GPIO_PB15_IF : PB15 pin interrupt flag
bits : 7 - 7 (1 bit)


R8_GPIO_INT_ENABLE

GPIO interrupt enable
address_offset : 0x1D Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

R8_GPIO_INT_ENABLE R8_GPIO_INT_ENABLE read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 RB_GPIO_PB15_IE

RB_GPIO_PB15_IE : PB15 pin interrupt enable
bits : 7 - 7 (1 bit)


R8_GPIO_INT_MODE

GPIO interrupt mode
address_offset : 0x1E Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

R8_GPIO_INT_MODE R8_GPIO_INT_MODE read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 RB_GPIO_PB15_IM

RB_GPIO_PB15_IM : PB15 pin interrupt mode
bits : 7 - 7 (1 bit)


R8_GPIO_INT_POLAR

GPIO interrupt polarity
address_offset : 0x1F Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

R8_GPIO_INT_POLAR R8_GPIO_INT_POLAR read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 RB_GPIO_PB15_IP

RB_GPIO_PB15_IP : PB15 pin interrupt mode
bits : 7 - 7 (1 bit)


R8_SAFE_ACCESS_ID

safe accessing ID register
address_offset : 0x2 Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

R8_SAFE_ACCESS_ID R8_SAFE_ACCESS_ID read-only 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 R8_SAFE_ACCESS_ID

R8_SAFE_ACCESS_ID : safe accessing ID
bits : 0 - 7 (8 bit)


R16_SERD_ANA_CFG1

Serdes Analog parameter configuration1
address_offset : 0x20 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

R16_SERD_ANA_CFG1 R16_SERD_ANA_CFG1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RB_SERD_PLL_CFG RB_SERD_30M_SEL RB_SERD_DN_TST

RB_SERD_PLL_CFG : SerDes PHY internal configuration bit
bits : 0 - 7 (8 bit)

RB_SERD_30M_SEL : SerDes PHY reference clock source seletion
bits : 8 - 8 (1 bit)

RB_SERD_DN_TST : Enable SerDes PHY GXM test pin
bits : 9 - 9 (1 bit)


R32_SERD_ANA_CFG2

Serdes Analog parameter configuration2
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

R32_SERD_ANA_CFG2 R32_SERD_ANA_CFG2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RB_SERD_TRX_CFG

RB_SERD_TRX_CFG : Tx and RX parameter setting
bits : 0 - 24 (25 bit)


R8_WDOG_COUNT

watch-dog count register
address_offset : 0x3 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

R8_WDOG_COUNT R8_WDOG_COUNT read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 R8_WDOG_COUNT

R8_WDOG_COUNT : watch-dog count
bits : 0 - 7 (8 bit)


R8_GLOB_ROM_CFG

flash ROM configuration register
address_offset : 0x4 Bytes (0x0)
size : 8 bit
reset_value : 0x0
reset_Mask : 0x0

R8_GLOB_ROM_CFG R8_GLOB_ROM_CFG 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 RB_ROM_EXT_RE RB_CODE_RAM_WE RB_ROM_DATA_WE RB_ROM_CODE_WE RB_ROM_CODE_OFS

RB_ROM_EXT_RE : enable flash ROM being read by external programmer
bits : 0 - 0 (1 bit)
access : read-only

RB_CODE_RAM_WE : enable code RAM being write
bits : 1 - 1 (1 bit)
access : read-write

RB_ROM_DATA_WE : enable flash ROM data area being erase/write
bits : 2 - 2 (1 bit)
access : read-write

RB_ROM_CODE_WE : enable flash ROM code_data area being erase/write
bits : 3 - 3 (1 bit)
access : read-write

RB_ROM_CODE_OFS : Config the start offset address of user code in Flash
bits : 4 - 4 (1 bit)
access : read-write


R32_PA_DIR

GPIO PA I/O direction
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

R32_PA_DIR R32_PA_DIR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R32_PA_DIR

R32_PA_DIR : GPIO PA I/O direction
bits : 0 - 23 (24 bit)


R32_PA_PIN

GPIO PA input
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

R32_PA_PIN R32_PA_PIN read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R32_PA_PIN

R32_PA_PIN : GPIO PA input
bits : 0 - 23 (24 bit)


R32_PA_OUT

GPIO PA output
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

R32_PA_OUT R32_PA_OUT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R32_PA_OUT

R32_PA_OUT : GPIO PA output
bits : 0 - 23 (24 bit)


R32_PA_CLR

GPIO PA clear output
address_offset : 0x4C Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

R32_PA_CLR R32_PA_CLR write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R32_PA_CLR

R32_PA_CLR : GPIO PA clear output
bits : 0 - 23 (24 bit)


R8_RST_BOOT_STAT

reset status and boot/debug status
address_offset : 0x5 Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

R8_RST_BOOT_STAT R8_RST_BOOT_STAT read-only 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 RB_RESET_FLAG RB_CFG_RESET_EN RB_CFG_BOOT_EN RB_CFG_DEBUG_EN RB_BOOT_LOADER

RB_RESET_FLAG : recent reset flag
bits : 0 - 1 (2 bit)

RB_CFG_RESET_EN : manual reset input enable status
bits : 2 - 2 (1 bit)

RB_CFG_BOOT_EN : boot-loader enable status
bits : 3 - 3 (1 bit)

RB_CFG_DEBUG_EN : debug enable status
bits : 4 - 4 (1 bit)

RB_BOOT_LOADER : indicate boot loader status
bits : 5 - 5 (1 bit)


R32_PA_PU

GPIO PA pullup resistance enable
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

R32_PA_PU R32_PA_PU read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R32_PA_PU

R32_PA_PU : GPIO PA pullup resistance enable
bits : 0 - 23 (24 bit)


R32_PA_PD

GPIO PA output open-drain_input pulldown resistance enable
address_offset : 0x54 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

R32_PA_PD R32_PA_PD read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R32_PA_PD

R32_PA_PD : GPIO PA output open-drain_input pulldown resistance enable
bits : 0 - 23 (24 bit)


R32_PA_DRV

GPIO PA driving capability
address_offset : 0x58 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

R32_PA_DRV R32_PA_DRV read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R32_PA_DRV

R32_PA_DRV : GPIO PA driving capability
bits : 0 - 23 (24 bit)


R32_PA_SMT

GPIO PA output slew rate_input schmitt trigger
address_offset : 0x5C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

R32_PA_SMT R32_PA_SMT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R32_PA_SMT

R32_PA_SMT : GPIO PA output slew rate_input schmitt trigger
bits : 0 - 23 (24 bit)


R8_RST_WDOG_CTRL

reset and watch-dog control
address_offset : 0x6 Bytes (0x0)
size : 8 bit
reset_value : 0x0
reset_Mask : 0x0

R8_RST_WDOG_CTRL R8_RST_WDOG_CTRL 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 RB_SOFTWARE_RESET RB_WDOG_RST_EN RB_WDOG_INT_EN RB_WDOG_INT_FLAG

RB_SOFTWARE_RESET : global software reset
bits : 0 - 0 (1 bit)
access : write-only

RB_WDOG_RST_EN : enable watch-dog reset if watch-dog timer overflow: 0=as timer only, 1=enable reset if timer overflow
bits : 1 - 1 (1 bit)
access : read-write

RB_WDOG_INT_EN : watch-dog interrupt enable or INT_ID_WDOG interrupt source selection: 0=software interrupt
bits : 2 - 2 (1 bit)
access : read-write

RB_WDOG_INT_FLAG : watch-dog timer overflow interrupt flag
bits : 3 - 3 (1 bit)
access : read-write


R32_PB_DIR

GPIO PB I/O direction
address_offset : 0x60 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

R32_PB_DIR R32_PB_DIR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R32_PB_DIR

R32_PB_DIR : GPIO PB I/O direction
bits : 0 - 24 (25 bit)


R32_PB_PIN

GPIO PB input
address_offset : 0x64 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

R32_PB_PIN R32_PB_PIN read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R32_PB_PIN

R32_PB_PIN : GPIO PB input
bits : 0 - 24 (25 bit)


R32_PB_OUT

GPIO PB output
address_offset : 0x68 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

R32_PB_OUT R32_PB_OUT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R32_PB_OUT

R32_PB_OUT : GPIO PB output
bits : 0 - 24 (25 bit)


R32_PB_CLR

GPIO PB clear output
address_offset : 0x6C Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

R32_PB_CLR R32_PB_CLR write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R32_PB_CLR

R32_PB_CLR : GPIO PB clear output
bits : 0 - 24 (25 bit)


R8_GLOB_RESET_KEEP

value keeper during global reset
address_offset : 0x7 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

R8_GLOB_RESET_KEEP R8_GLOB_RESET_KEEP read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 R8_GLOB_RESET_KEEP

R8_GLOB_RESET_KEEP : value keeper during global reset
bits : 0 - 7 (8 bit)


R32_PB_PU

GPIO PB pullup resistance enable
address_offset : 0x70 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

R32_PB_PU R32_PB_PU read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R32_PB_PU

R32_PB_PU : GPIO PB pullup resistance enable
bits : 0 - 24 (25 bit)


R32_PB_PD

GPIO PB output open-drain_input pulldown resistance enable
address_offset : 0x74 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

R32_PB_PD R32_PB_PD read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R32_PB_PD

R32_PB_PD : GPIO PB output open-drain_input pulldown resistance enable
bits : 0 - 24 (25 bit)


R32_PB_DRV

GPIO PB driving capability
address_offset : 0x78 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

R32_PB_DRV R32_PB_DRV read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R32_PB_DRV

R32_PB_DRV : GPIO PB driving capability
bits : 0 - 24 (25 bit)


R32_PB_SMT

GPIO PB output slew rate_input schmitt trigger
address_offset : 0x7C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

R32_PB_SMT R32_PB_SMT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R32_PB_SMT

R32_PB_SMT : GPIO PB output slew rate_input schmitt trigger
bits : 0 - 24 (25 bit)


R8_CLK_PLL_DIV

output clock divider from PLL
address_offset : 0x8 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

R8_CLK_PLL_DIV R8_CLK_PLL_DIV read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 R8_CLK_PLL_DIV

R8_CLK_PLL_DIV : output clock divider from PLL
bits : 0 - 7 (8 bit)


R8_CLK_CFG_CTRL

clock control
address_offset : 0xA Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

R8_CLK_CFG_CTRL R8_CLK_CFG_CTRL read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 RB_CLK_PLL_SLEEP RB_CLK_SEL_PLL

RB_CLK_PLL_SLEEP : PLL sleep control
bits : 0 - 0 (1 bit)

RB_CLK_SEL_PLL : clock source selection
bits : 1 - 1 (1 bit)


R8_CLK_MOD_AUX

clock mode aux register
address_offset : 0xB Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

R8_CLK_MOD_AUX R8_CLK_MOD_AUX read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 RB_INT_125M_EN RB_EXT_125M_EN RB_MCO_SEL_MSK RB_MCO_EN

RB_INT_125M_EN : clock from USB_PHY PCLK(125MHz)
bits : 0 - 0 (1 bit)

RB_EXT_125M_EN : clock from pin_PA[16]
bits : 1 - 1 (1 bit)

RB_MCO_SEL_MSK : MCO output selection
bits : 2 - 3 (2 bit)

RB_MCO_EN : MCO output enable
bits : 4 - 4 (1 bit)


R8_SLP_CLK_OFF0

sleep clock off control byte 0
address_offset : 0xC Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

R8_SLP_CLK_OFF0 R8_SLP_CLK_OFF0 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 RB_SLP_CLK_TMR0 RB_SLP_CLK_TMR1 RB_SLP_CLK_TMR2 RB_SLP_CLK_PWMX RB_SLP_CLK_UART0 RB_SLP_CLK_UART1 RB_SLP_CLK_UART2 RB_SLP_CLK_UART3

RB_SLP_CLK_TMR0 : sleep TMR0 clock
bits : 0 - 0 (1 bit)

RB_SLP_CLK_TMR1 : sleep TMR1 clock
bits : 1 - 1 (1 bit)

RB_SLP_CLK_TMR2 : sleep TMR2 clock
bits : 2 - 2 (1 bit)

RB_SLP_CLK_PWMX : sleep PWMX clock
bits : 3 - 3 (1 bit)

RB_SLP_CLK_UART0 : sleep UART0 clock
bits : 4 - 4 (1 bit)

RB_SLP_CLK_UART1 : sleep UART1 clock
bits : 5 - 5 (1 bit)

RB_SLP_CLK_UART2 : sleep UART2 clock
bits : 6 - 6 (1 bit)

RB_SLP_CLK_UART3 : sleep UART3 clock
bits : 7 - 7 (1 bit)


R8_SLP_CLK_OFF1

sleep clock off control byte 1
address_offset : 0xD Bytes (0x0)
size : 8 bit
reset_value : 0x0
reset_Mask : 0x0

R8_SLP_CLK_OFF1 R8_SLP_CLK_OFF1 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 RB_SLP_CLK_SPI0 RB_SLP_CLK_SPI1 RB_SLP_CLK_EMMC RB_SLP_CLK_HSPI RB_SLP_CLK_USBHS RB_SLP_CLK_USBSS RB_SLP_CLK_SERD RB_SLP_CLK_DVP

RB_SLP_CLK_SPI0 : sleep SPI0 clock
bits : 0 - 0 (1 bit)
access : read-write

RB_SLP_CLK_SPI1 : sleep SPI1 clock
bits : 1 - 1 (1 bit)
access : read-write

RB_SLP_CLK_EMMC : sleep EMMC clock
bits : 2 - 2 (1 bit)
access : read-write

RB_SLP_CLK_HSPI : sleep HSPI clock
bits : 3 - 3 (1 bit)
access : read-write

RB_SLP_CLK_USBHS : sleep USBHS clock
bits : 4 - 4 (1 bit)
access : read-write

RB_SLP_CLK_USBSS : sleep USBSS clock
bits : 5 - 5 (1 bit)
access : read-write

RB_SLP_CLK_SERD : sleep SERD clock
bits : 6 - 6 (1 bit)
access : read-write

RB_SLP_CLK_DVP : sleep DVP clock
bits : 7 - 7 (1 bit)
access : read-only


R8_SLP_WAKE_CTRL

wake control
address_offset : 0xE Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

R8_SLP_WAKE_CTRL R8_SLP_WAKE_CTRL read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 RB_SLP_USBHS_WAKE RB_SLP_USBSS_WAKE RB_SLP_CLK_ETH RB_SLP_CLK_ECDC RB_SLP_GPIO_WAKE RB_SLP_ETH_WAKE

RB_SLP_USBHS_WAKE : enable USBHS waking
bits : 0 - 0 (1 bit)

RB_SLP_USBSS_WAKE : enable USBSS waking
bits : 1 - 1 (1 bit)

RB_SLP_CLK_ETH : sleep ETH clock
bits : 2 - 2 (1 bit)

RB_SLP_CLK_ECDC : sleep ECDC clock
bits : 3 - 3 (1 bit)

RB_SLP_GPIO_WAKE : enable GPIO waking
bits : 4 - 4 (1 bit)

RB_SLP_ETH_WAKE : enable Eth waking
bits : 5 - 5 (1 bit)


R8_SLP_POWER_CTRL

power control
address_offset : 0xF Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

R8_SLP_POWER_CTRL R8_SLP_POWER_CTRL read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 RB_SLP_USBHS_PWRDN

RB_SLP_USBHS_PWRDN : enable USBHS power down
bits : 0 - 0 (1 bit)



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