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TMR1

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x400 byte (0x0)
mem_usage : registers
protection :

Registers

R8_TMR1_CTRL_MOD

R8_TMR1_CTRL_DMA

R32_TMR1_FIFO

R32_TMR1_DMA_NOW

R32_TMR1_DMA_BEG

R32_TMR1_DMA_END

R8_TMR1_INTER_EN

R8_TMR1_INT_FLAG

R8_TMR1_FIFO_COUNT

R32_TMR1_COUNT

R32_TMR1_CNT_END


R8_TMR1_CTRL_MOD

TMR1 mode control
address_offset : 0x0 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

R8_TMR1_CTRL_MOD R8_TMR1_CTRL_MOD read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 RB_TMR_MODE_IN RB_TMR_ALL_CLEAR RB_TMR_COUNT_EN RB_TMR_OUT_EN RB_TMR_OUT_POLAR_RB_TMR_CAP_COUNT RB_TMR_PWM_REPEAT_RB_TMR_CAP_EDGE

RB_TMR_MODE_IN : timer in mode
bits : 0 - 0 (1 bit)

RB_TMR_ALL_CLEAR : force clear timer FIFO and count
bits : 1 - 1 (1 bit)

RB_TMR_COUNT_EN : timer count enable
bits : 2 - 2 (1 bit)

RB_TMR_OUT_EN : timer output enable
bits : 3 - 3 (1 bit)

RB_TMR_OUT_POLAR_RB_TMR_CAP_COUNT : timer PWM output polarity / Count sub-mode
bits : 4 - 4 (1 bit)

RB_TMR_PWM_REPEAT_RB_TMR_CAP_EDGE : timer PWM repeat mode / timer capture edge mode
bits : 6 - 7 (2 bit)


R8_TMR1_CTRL_DMA

TMR1 DMA control
address_offset : 0x1 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

R8_TMR1_CTRL_DMA R8_TMR1_CTRL_DMA read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 RB_TMR_DMA_ENABLE RB_TMR_DMA_LOOP

RB_TMR_DMA_ENABLE : timer1/2 DMA enable
bits : 0 - 0 (1 bit)

RB_TMR_DMA_LOOP : timer1/2 DMA address loop enable
bits : 2 - 2 (1 bit)


R32_TMR1_FIFO

TMR1 FIFO only low 26 bit
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-only/write-only
reset_value : 0x0
reset_Mask : 0x0

R32_TMR1_FIFO R32_TMR1_FIFO read-only/write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R32_TMR1_FIFO

R32_TMR1_FIFO : TMR current count
bits : 0 - 31 (32 bit)


R32_TMR1_DMA_NOW

TMR1 DMA current address
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

R32_TMR1_DMA_NOW R32_TMR1_DMA_NOW read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R16_TMR1_DMA_NOW

R16_TMR1_DMA_NOW : TMR DMA current address
bits : 0 - 17 (18 bit)


R32_TMR1_DMA_BEG

TMR1 DMA begin address
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

R32_TMR1_DMA_BEG R32_TMR1_DMA_BEG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R16_TMR1_DMA_BEG

R16_TMR1_DMA_BEG : TMR1 DMA begin address
bits : 0 - 17 (18 bit)


R32_TMR1_DMA_END

TMR1 DMA end address
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

R32_TMR1_DMA_END R32_TMR1_DMA_END read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R16_TMR1_DMA_END

R16_TMR1_DMA_END : TMR1 DMA end address
bits : 0 - 17 (18 bit)


R8_TMR1_INTER_EN

TMR1 interrupt enable
address_offset : 0x2 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

R8_TMR1_INTER_EN R8_TMR1_INTER_EN read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 RB_TMR_IE_CYC_END RB_TMR_IE_DATA_ACT RB_TMR_IE_FIFO_HF RB_TMR_IE_DMA_END RB_TMR_IE_FIFO_OV

RB_TMR_IE_CYC_END : enable interrupt for timer capture count timeout or PWM cycle end
bits : 0 - 0 (1 bit)

RB_TMR_IE_DATA_ACT : enable interrupt for timer capture input action or PWM trigger
bits : 1 - 1 (1 bit)

RB_TMR_IE_FIFO_HF : enable interrupt for timer FIFO half (capture fifo >=4 or PWM fifo lower than3)
bits : 2 - 2 (1 bit)

RB_TMR_IE_DMA_END : enable interrupt for timer1/2 DMA completion
bits : 3 - 3 (1 bit)

RB_TMR_IE_FIFO_OV : enable interrupt for timer FIFO overflow
bits : 4 - 4 (1 bit)


R8_TMR1_INT_FLAG

TMR1 interrupt flag
address_offset : 0x6 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

R8_TMR1_INT_FLAG R8_TMR1_INT_FLAG read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 RB_TMR_IF_CYC_END RB_TMR_IF_DATA_ACT RB_TMR_IF_FIFO_HF RB_TMR_IF_DMA_END RB_TMR_IF_FIFO_OV

RB_TMR_IF_CYC_END : interrupt flag for timer capture count timeout or PWM cycle end
bits : 0 - 0 (1 bit)

RB_TMR_IF_DATA_ACT : interrupt flag for timer capture input action or PWM trigger
bits : 1 - 1 (1 bit)

RB_TMR_IF_FIFO_HF : interrupt flag for timer FIFO half (capture fifo >=4 or PWM fifo lower than 3)
bits : 2 - 2 (1 bit)

RB_TMR_IF_DMA_END : interrupt flag for timer1/2 DMA completion
bits : 3 - 3 (1 bit)

RB_TMR_IF_FIFO_OV : interrupt flag for timer FIFO overflow
bits : 4 - 4 (1 bit)


R8_TMR1_FIFO_COUNT

TMR1 FIFO count status
address_offset : 0x7 Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

R8_TMR1_FIFO_COUNT R8_TMR1_FIFO_COUNT read-only 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 R8_TMR1_FIFO_COUNT

R8_TMR1_FIFO_COUNT : TMR FIFO count status
bits : 0 - 7 (8 bit)


R32_TMR1_COUNT

TMR1 current count
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

R32_TMR1_COUNT R32_TMR1_COUNT read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R32_TMR1_COUNT

R32_TMR1_COUNT : TMR current count
bits : 0 - 31 (32 bit)


R32_TMR1_CNT_END

TMR1 end count value, only low 26 bit
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

R32_TMR1_CNT_END R32_TMR1_CNT_END read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R32_TMR1_CNT_END

R32_TMR1_CNT_END : TMR current count
bits : 0 - 31 (32 bit)



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