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UART2

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x400 byte (0x0)
mem_usage : registers
protection :

Registers

R8_UART2_MCR

R8_UART2_IER

R8_UART2_FCR

R8_UART2_LCR

R8_UART2_IIR

R8_UART2_LSR

R8_UART2_RBR_R8_UART2_THR

R8_UART2_RFC

R8_UART2_TFC

R16_UART2_DL

R8_UART2_DIV


R8_UART2_MCR

UART2 modem control
address_offset : 0x0 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

R8_UART2_MCR R8_UART2_MCR read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 RB_MCR_OUT2 RB_MCR_AU_FLOW_EN

RB_MCR_OUT2 : UART2 control OUT2
bits : 3 - 3 (1 bit)

RB_MCR_AU_FLOW_EN : UART0 enable autoflow control
bits : 5 - 5 (1 bit)


R8_UART2_IER

UART2 interrupt enable
address_offset : 0x1 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

R8_UART2_IER R8_UART2_IER read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 RB_IER_RECV_RDY RB_IER_THR_EMPTY RB_IER_LINE_STAT RB_IER_TXD_EN RB_IER_RESET

RB_IER_RECV_RDY : UART interrupt enable for receiver data ready
bits : 0 - 0 (1 bit)

RB_IER_THR_EMPTY : UART interrupt enable for THR empty
bits : 1 - 1 (1 bit)

RB_IER_LINE_STAT : UART interrupt enable for receiver line status
bits : 2 - 2 (1 bit)

RB_IER_TXD_EN : UART TXD pin enable
bits : 6 - 6 (1 bit)

RB_IER_RESET : UART software reset control, high action, auto clear
bits : 7 - 7 (1 bit)


R8_UART2_FCR

UART2 FIFO control
address_offset : 0x2 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

R8_UART2_FCR R8_UART2_FCR read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 RB_FCR_FIFO_EN RB_FCR_RX_FIFO_CLR RB_FCR_TX_FIFO_CLR RB_FCR_FIFO_TRIG

RB_FCR_FIFO_EN : UART FIFO enable
bits : 0 - 0 (1 bit)

RB_FCR_RX_FIFO_CLR : clear UART receiver FIFO, high action, auto clear
bits : 1 - 1 (1 bit)

RB_FCR_TX_FIFO_CLR : clear UART transmitter FIFO, high action, auto clear
bits : 2 - 2 (1 bit)

RB_FCR_FIFO_TRIG : UART receiver FIFO trigger level
bits : 6 - 7 (2 bit)


R8_UART2_LCR

UART2 line control
address_offset : 0x3 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

R8_UART2_LCR R8_UART2_LCR read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 RB_LCR_WORD_SZ RB_LCR_STOP_BIT RB_LCR_PAR_EN RB_LCR_PAR_MOD RB_LCR_BREAK_EN RB_LCR_DLAB_RB_LCR_GP_BIT

RB_LCR_WORD_SZ : UART word bit length
bits : 0 - 1 (2 bit)

RB_LCR_STOP_BIT : UART stop bit length
bits : 2 - 2 (1 bit)

RB_LCR_PAR_EN : UART parity enable
bits : 3 - 3 (1 bit)

RB_LCR_PAR_MOD : UART parity mode
bits : 4 - 5 (2 bit)

RB_LCR_BREAK_EN : UART break control enable
bits : 6 - 6 (1 bit)

RB_LCR_DLAB_RB_LCR_GP_BIT : UART reserved bit / UART general purpose bit
bits : 7 - 7 (1 bit)


R8_UART2_IIR

UART2 interrupt identification
address_offset : 0x4 Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

R8_UART2_IIR R8_UART2_IIR read-only 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 RB_IIR_NO_INT RB_IIR_INT_MASK RB_IIR_FIFO_ID

RB_IIR_NO_INT : UART no interrupt flag
bits : 0 - 0 (1 bit)

RB_IIR_INT_MASK : UART interrupt flag bit mask
bits : 1 - 3 (3 bit)

RB_IIR_FIFO_ID : UART FIFO enabled flag
bits : 6 - 7 (2 bit)


R8_UART2_LSR

UART2 line status
address_offset : 0x5 Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

R8_UART2_LSR R8_UART2_LSR read-only 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 RB_LSR_DATA_RDY RB_LSR_OVER_ERR RB_LSR_PAR_ERR RB_LSR_FRAME_ERR RB_LSR_BREAK_ERR RB_LSR_TX_FIFO_EMP RB_LSR_TX_ALL_EMP RB_LSR_ERR_RX_FIFO

RB_LSR_DATA_RDY : UART receiver fifo data ready status
bits : 0 - 0 (1 bit)

RB_LSR_OVER_ERR : UART receiver overrun error
bits : 1 - 1 (1 bit)

RB_LSR_PAR_ERR : UART receiver frame error
bits : 2 - 2 (1 bit)

RB_LSR_FRAME_ERR : UART receiver frame error
bits : 3 - 3 (1 bit)

RB_LSR_BREAK_ERR : UART receiver break error
bits : 4 - 4 (1 bit)

RB_LSR_TX_FIFO_EMP : UART transmitter fifo empty status
bits : 5 - 5 (1 bit)

RB_LSR_TX_ALL_EMP : UART transmitter all empty status
bits : 6 - 6 (1 bit)

RB_LSR_ERR_RX_FIFO : indicate error in UART receiver fifo
bits : 7 - 7 (1 bit)


R8_UART2_RBR_R8_UART2_THR

UART2 receiver buffer, receiving byte / UART2 transmitter holding, transmittal byte
address_offset : 0x8 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

R8_UART2_RBR_R8_UART2_THR R8_UART2_RBR_R8_UART2_THR read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 R8_UART2_RBR_R8_UART2_THR

R8_UART2_RBR_R8_UART2_THR : UART receiver buffer, receiving byte / UART transmitter holding, transmittal byte
bits : 0 - 7 (8 bit)


R8_UART2_RFC

UART2 receiver FIFO count
address_offset : 0xA Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

R8_UART2_RFC R8_UART2_RFC read-only 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 R8_UART2_RFC

R8_UART2_RFC : UART receiver FIFO count
bits : 0 - 7 (8 bit)


R8_UART2_TFC

UART2 transmitter FIFO count
address_offset : 0xB Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

R8_UART2_TFC R8_UART2_TFC read-only 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 R8_UART2_TFC

R8_UART2_TFC : UART transmitter FIFO count
bits : 0 - 7 (8 bit)


R16_UART2_DL

UART2 divisor latch
address_offset : 0xC Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

R16_UART2_DL R16_UART2_DL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R16_UART2_DL

R16_UART2_DL : UART divisor latch
bits : 0 - 15 (16 bit)


R8_UART2_DIV

UART2 pre-divisor latch byte
address_offset : 0xE Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

R8_UART2_DIV R8_UART2_DIV read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 R8_UART2_DIV

R8_UART2_DIV : UART pre-divisor latch byte
bits : 0 - 7 (8 bit)



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