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SPI1

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x400 byte (0x0)
mem_usage : registers
protection :

Registers

R8_SPI1_CTRL_MOD

R8_SPI1_CTRL_CFG

R8_SPI1_FIFO

R8_SPI1_FIFO_COUNT1

R32_SPI1_DMA_NOW

R32_SPI1_DMA_BEG

R32_SPI1_DMA_END

R8_SPI1_INTER_EN

R8_SPI1_CLOCK_DIV_R8_SPI1_SLAVE_PRE

R8_SPI1_BUFFER

R8_SPI1_RUN_FLAG

R8_SPI1_INT_FLAG

R8_SPI1_FIFO_COUNT

R16_SPI1_TOTAL_CNT


R8_SPI1_CTRL_MOD

SPI1 mode control
address_offset : 0x0 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

R8_SPI1_CTRL_MOD R8_SPI1_CTRL_MOD read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 RB_SPI_MODE_SLAVE RB_SPI_ALL_CLEAR RB_SPI_2WIRE_MOD RB_SPI_MST_SCK_MOD_RB_SPI_SLV_CMD_MOD RB_SPI_FIFO_DIR RB_SPI_SCK_OE RB_SPI_MOSI_OE RB_SPI_MISO_OE

RB_SPI_MODE_SLAVE : SPI slave mode
bits : 0 - 0 (1 bit)

RB_SPI_ALL_CLEAR : force clear SPI FIFO and count
bits : 1 - 1 (1 bit)

RB_SPI_2WIRE_MOD : SPI enable 2 wire mode
bits : 2 - 2 (1 bit)

RB_SPI_MST_SCK_MOD_RB_SPI_SLV_CMD_MOD : SPI master clock mode / SPI slave command mode
bits : 3 - 3 (1 bit)

RB_SPI_FIFO_DIR : SPI FIFO direction
bits : 4 - 4 (1 bit)

RB_SPI_SCK_OE : SPI SCK output enable
bits : 5 - 5 (1 bit)

RB_SPI_MOSI_OE : SPI MOSI output enable
bits : 6 - 6 (1 bit)

RB_SPI_MISO_OE : SPI MISO output enable
bits : 7 - 7 (1 bit)


R8_SPI1_CTRL_CFG

SPI1 configuration control
address_offset : 0x1 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

R8_SPI1_CTRL_CFG R8_SPI1_CTRL_CFG read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 RB_SPI_DMA_ENABLE RB_SPI_DMA_LOOP RB_SPI_AUTO_IF RB_SPI_BIT_ORDER

RB_SPI_DMA_ENABLE : SPI DMA enable
bits : 0 - 0 (1 bit)

RB_SPI_DMA_LOOP : SPI DMA address loop enable
bits : 2 - 2 (1 bit)

RB_SPI_AUTO_IF : enable buffer/FIFO accessing to auto clear RB_SPI_IF_BYTE_END interrupt flag
bits : 4 - 4 (1 bit)

RB_SPI_BIT_ORDER : SPI bit data order
bits : 5 - 5 (1 bit)


R8_SPI1_FIFO

SPI1 FIFO register
address_offset : 0x10 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

R8_SPI1_FIFO R8_SPI1_FIFO read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 R8_SPI1_FIFO

R8_SPI1_FIFO : SPI FIFO register
bits : 0 - 7 (8 bit)


R8_SPI1_FIFO_COUNT1

SPI0 FIFO count status
address_offset : 0x13 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

R8_SPI1_FIFO_COUNT1 R8_SPI1_FIFO_COUNT1 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 R8_SPI1_FIFO_COUNT1

R8_SPI1_FIFO_COUNT1 : SPI FIFO count statu
bits : 0 - 7 (8 bit)


R32_SPI1_DMA_NOW

SPI1 DMA current address
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

R32_SPI1_DMA_NOW R32_SPI1_DMA_NOW read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R16_SPI1_DMA_NOW

R16_SPI1_DMA_NOW : SPI DMA current address
bits : 0 - 17 (18 bit)


R32_SPI1_DMA_BEG

SPI1 DMA begin address
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

R32_SPI1_DMA_BEG R32_SPI1_DMA_BEG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R16_SPI1_DMA_BEG

R16_SPI1_DMA_BEG : SPI DMA begin address
bits : 0 - 17 (18 bit)


R32_SPI1_DMA_END

SPI1 DMA end address
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

R32_SPI1_DMA_END R32_SPI1_DMA_END read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R16_SPI1_DMA_END

R16_SPI1_DMA_END : SPI DMA end address
bits : 0 - 17 (18 bit)


R8_SPI1_INTER_EN

SPI1 interrupt enable
address_offset : 0x2 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

R8_SPI1_INTER_EN R8_SPI1_INTER_EN read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 RB_SPI_IE_CNT_END RB_SPI_IE_BYTE_END RB_SPI_IE_FIFO_HF RB_SPI_IE_DMA_END RB_SPI_IE_FIFO_OV RB_SPI_IE_FST_BYTE

RB_SPI_IE_CNT_END : enable interrupt for SPI total byte count end
bits : 0 - 0 (1 bit)

RB_SPI_IE_BYTE_END : enable interrupt for SPI byte exchanged
bits : 1 - 1 (1 bit)

RB_SPI_IE_FIFO_HF : enable interrupt for SPI FIFO half
bits : 2 - 2 (1 bit)

RB_SPI_IE_DMA_END : enable interrupt for SPI DMA completion
bits : 3 - 3 (1 bit)

RB_SPI_IE_FIFO_OV : enable interrupt for SPI FIFO overflow
bits : 4 - 4 (1 bit)

RB_SPI_IE_FST_BYTE : enable interrupt for SPI slave mode first byte received
bits : 7 - 7 (1 bit)


R8_SPI1_CLOCK_DIV_R8_SPI1_SLAVE_PRE

SPI1 master clock divisor / SPI0 slave preset value
address_offset : 0x3 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

R8_SPI1_CLOCK_DIV_R8_SPI1_SLAVE_PRE R8_SPI1_CLOCK_DIV_R8_SPI1_SLAVE_PRE read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 R8_SPI1_CLOCK_DIV_R8_SPI1_SLAVE_PRESET

R8_SPI1_CLOCK_DIV_R8_SPI1_SLAVE_PRESET : master clock divisor / SPI0 slave preset value
bits : 0 - 7 (8 bit)


R8_SPI1_BUFFER

SPI1 data buffer
address_offset : 0x4 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

R8_SPI1_BUFFER R8_SPI1_BUFFER read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 R8_SPI1_BUFFER

R8_SPI1_BUFFER : SPI data buffer
bits : 0 - 7 (8 bit)


R8_SPI1_RUN_FLAG

SPI1 work flag
address_offset : 0x5 Bytes (0x0)
size : 8 bit
access : read
reset_value : 0x0
reset_Mask : 0x0

R8_SPI1_RUN_FLAG R8_SPI1_RUN_FLAG read 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 RB_SPI_SLV_CMD_ACT RB_SPI_FIFO_READY RB_SPI_SLV_CS_LOAD RB_SPI_SLV_SELECT

RB_SPI_SLV_CMD_ACT : SPI slave command flag
bits : 4 - 4 (1 bit)

RB_SPI_FIFO_READY : SPI FIFO ready status
bits : 5 - 5 (1 bit)

RB_SPI_SLV_CS_LOAD : SPI slave chip-select loading status
bits : 6 - 6 (1 bit)

RB_SPI_SLV_SELECT : SPI slave selection status
bits : 7 - 7 (1 bit)


R8_SPI1_INT_FLAG

SPI1 interrupt flag
address_offset : 0x6 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

R8_SPI1_INT_FLAG R8_SPI1_INT_FLAG read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 RB_SPI_IF_CNT_END RB_SPI_IF_BYTE_END RB_SPI_IF_FIFO_HF RB_SPI_IF_DMA_END RB_SPI_IF_FIFO_OV RB_SPI_FREE RB_SPI_IF_FST_BYTE

RB_SPI_IF_CNT_END : interrupt flag for SPI total byte count end
bits : 0 - 0 (1 bit)

RB_SPI_IF_BYTE_END : interrupt flag for SPI byte exchanged
bits : 1 - 1 (1 bit)

RB_SPI_IF_FIFO_HF : interrupt flag for SPI FIFO half
bits : 2 - 2 (1 bit)

RB_SPI_IF_DMA_END : interrupt flag for SPI DMA completion
bits : 3 - 3 (1 bit)

RB_SPI_IF_FIFO_OV : interrupt flag for SPI FIFO overflow
bits : 4 - 4 (1 bit)

RB_SPI_FREE : current SPI free status
bits : 6 - 6 (1 bit)

RB_SPI_IF_FST_BYTE : interrupt flag for SPI slave mode first byte received
bits : 7 - 7 (1 bit)


R8_SPI1_FIFO_COUNT

SPI1 FIFO count status
address_offset : 0x7 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

R8_SPI1_FIFO_COUNT R8_SPI1_FIFO_COUNT read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 R8_SPI1_FIFO_COUNT

R8_SPI1_FIFO_COUNT : SPI FIFO count status
bits : 0 - 7 (8 bit)


R16_SPI1_TOTAL_CNT

SPI1 total byte count, only low 12 bit
address_offset : 0xC Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

R16_SPI1_TOTAL_CNT R16_SPI1_TOTAL_CNT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R16_SPI1_TOTAL_CNT

R16_SPI1_TOTAL_CNT : SPI total byte count, only low 12 bit
bits : 0 - 15 (16 bit)



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