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HSPI

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x400 byte (0x0)
mem_usage : registers
protection :

Registers

R8_HSPI_CFG

R8_HSPI_CTRL

R32_HSPI_RX_ADDR1

R16_HSPI_DMA_LEN0

R16_HSPI_RX_LEN0

R16_HSPI_DMA_LEN1

R16_HSPI_RX_LEN1

R16_HSPI_BURST_CFG

R8_HSPI_BURST_CNT

R8_HSPI_INT_EN

R32_HSPI_UDF0

R32_HSPI_UDF1

R8_HSPI_INT_FLAG

R8_HSPI_RTX_STATUS

R8_HSPI_TX_SC

HSPI_RX_SC

R8_HSPI_AUX

R32_HSPI_TX_ADDR0

R32_HSPI_TX_ADDR1

R32_HSPI_RX_ADDR0


R8_HSPI_CFG

parallel if tx/rx cfg
address_offset : 0x0 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

R8_HSPI_CFG R8_HSPI_CFG read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 RB_HSPI_MODE RB_HSPI_DUALDMA RB_HSPI_MSK_SIZE RB_HSPI_TX_TOG_EN RB_HSPI_RX_TOG_EN RB_HSPI_HW_ACK

RB_HSPI_MODE : parallel if mode
bits : 0 - 0 (1 bit)

RB_HSPI_DUALDMA : parallel if dualdma mode enable
bits : 1 - 1 (1 bit)

RB_HSPI_MSK_SIZE : parallel if data mode
bits : 2 - 3 (2 bit)

RB_HSPI_TX_TOG_EN : parallel if tx addr toggle enable
bits : 5 - 5 (1 bit)

RB_HSPI_RX_TOG_EN : parallel if rx addr toggle enable
bits : 6 - 6 (1 bit)

RB_HSPI_HW_ACK : parallel if tx ack by hardware
bits : 7 - 7 (1 bit)


R8_HSPI_CTRL

parallel if tx/rx control
address_offset : 0x1 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

R8_HSPI_CTRL R8_HSPI_CTRL read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 RB_HSPI_ENABLE RB_HSPI_DMA_EN RB_HSPI_SW_ACT RB_HSPI_ALL_CLR RB_HSPI_TRX_RST

RB_HSPI_ENABLE : parallel if enable
bits : 0 - 0 (1 bit)

RB_HSPI_DMA_EN : parallel if dma enable
bits : 1 - 1 (1 bit)

RB_HSPI_SW_ACT : parallel if transmit software trigger
bits : 2 - 2 (1 bit)

RB_HSPI_ALL_CLR : parallel if all clear
bits : 3 - 3 (1 bit)

RB_HSPI_TRX_RST : parallel if tx and rx logic clear, high action
bits : 4 - 4 (1 bit)


R32_HSPI_RX_ADDR1

parallel if dma rx addr1
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

R32_HSPI_RX_ADDR1 R32_HSPI_RX_ADDR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RB_HSPI_RX_ADDR1

RB_HSPI_RX_ADDR1 : parallel if dma rx addr1
bits : 0 - 16 (17 bit)


R16_HSPI_DMA_LEN0

parallel if dma length0
address_offset : 0x14 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

R16_HSPI_DMA_LEN0 R16_HSPI_DMA_LEN0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RB_HSPI_DMA_LEN0

RB_HSPI_DMA_LEN0 : parallel if dma length0
bits : 0 - 11 (12 bit)


R16_HSPI_RX_LEN0

parallel if receive length0
address_offset : 0x16 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

R16_HSPI_RX_LEN0 R16_HSPI_RX_LEN0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RB_HSPI_RX_LEN0

RB_HSPI_RX_LEN0 : parallel if dma length0
bits : 0 - 11 (12 bit)


R16_HSPI_DMA_LEN1

parallel if dma length1
address_offset : 0x18 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

R16_HSPI_DMA_LEN1 R16_HSPI_DMA_LEN1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RB_HSPI_DMA_LEN1

RB_HSPI_DMA_LEN1 : parallel if dma length1
bits : 0 - 11 (12 bit)


R16_HSPI_RX_LEN1

parallel if receive length1
address_offset : 0x1A Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

R16_HSPI_RX_LEN1 R16_HSPI_RX_LEN1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RB_HSPI_RX_LEN1

RB_HSPI_RX_LEN1 : parallel if dma length1
bits : 0 - 11 (12 bit)


R16_HSPI_BURST_CFG

parallel if tx burst config register
address_offset : 0x1C Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

R16_HSPI_BURST_CFG R16_HSPI_BURST_CFG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RB_HSPI_BURST_EN RB_HSPI_BURST_LEN

RB_HSPI_BURST_EN : burst transmit enable
bits : 0 - 0 (1 bit)

RB_HSPI_BURST_LEN : burst transmit length
bits : 8 - 15 (8 bit)


R8_HSPI_BURST_CNT

parallel if tx burst count
address_offset : 0x1E Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

R8_HSPI_BURST_CNT R8_HSPI_BURST_CNT read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 RB_HSPI_BURST_CNT

RB_HSPI_BURST_CNT : parallel if tx burst count
bits : 0 - 7 (8 bit)


R8_HSPI_INT_EN

parallel if interrupt enable register
address_offset : 0x2 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

R8_HSPI_INT_EN R8_HSPI_INT_EN read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 RB_HSPI_IE_T_DONE RB_HSPI_IE_R_DONE RB_HSPI_IE_FIFO_OV RB_HSPI_IE_B_DONE

RB_HSPI_IE_T_DONE : parallel if transmit done interrupt enable
bits : 0 - 0 (1 bit)

RB_HSPI_IE_R_DONE : parallel if receive done interrupt enable
bits : 1 - 1 (1 bit)

RB_HSPI_IE_FIFO_OV : parallel if fifo overflow interrupt enable
bits : 2 - 2 (1 bit)

RB_HSPI_IE_B_DONE : parallel if tx burst done interrupt enable
bits : 3 - 3 (1 bit)


R32_HSPI_UDF0

parallel if user defined field 0 register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

R32_HSPI_UDF0 R32_HSPI_UDF0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RB_HSPI_UDF0

RB_HSPI_UDF0 : parallel if user defined field 0 register
bits : 0 - 25 (26 bit)


R32_HSPI_UDF1

parallel if user defined field 1 register
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

R32_HSPI_UDF1 R32_HSPI_UDF1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RB_HSPI_UDF1

RB_HSPI_UDF1 : parallel if user defined field 1 register
bits : 0 - 25 (26 bit)


R8_HSPI_INT_FLAG

parallel if interrupt flag
address_offset : 0x28 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

R8_HSPI_INT_FLAG R8_HSPI_INT_FLAG read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 RB_HSPI_IF_T_DONE RB_HSPI_IF_R_DONE RB_HSPI_IF_FIFO_OV RB_HSPI_IF_B_DONE

RB_HSPI_IF_T_DONE : interrupt flag for parallel if transmit done
bits : 0 - 0 (1 bit)

RB_HSPI_IF_R_DONE : interrupt flag for parallel if receive done
bits : 1 - 1 (1 bit)

RB_HSPI_IF_FIFO_OV : interrupt flag for parallel if FIFO overflow
bits : 2 - 2 (1 bit)

RB_HSPI_IF_B_DONE : interrupt flag for parallel if tx burst done
bits : 3 - 3 (1 bit)


R8_HSPI_RTX_STATUS

parallel rtx status
address_offset : 0x29 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

R8_HSPI_RTX_STATUS R8_HSPI_RTX_STATUS read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 RB_HSPI_CRC_ERR RB_HSPI_NUM_MIS

RB_HSPI_CRC_ERR : CRC error occur
bits : 1 - 1 (1 bit)

RB_HSPI_NUM_MIS : rx and tx sequence number mismatch
bits : 2 - 2 (1 bit)


R8_HSPI_TX_SC

parallel TX sequence ctrl
address_offset : 0x2A Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

R8_HSPI_TX_SC R8_HSPI_TX_SC read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 RB_HSPI_TX_NUM RB_HSPI_TX_TOG

RB_HSPI_TX_NUM : parallel if tx sequence num
bits : 0 - 3 (4 bit)

RB_HSPI_TX_TOG : parallel if tx addr toggle flag
bits : 4 - 4 (1 bit)


HSPI_RX_SC

parallel RX sequence ctrl
address_offset : 0x2B Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HSPI_RX_SC HSPI_RX_SC read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 RB_HSPI_RX_NUM RB_HSPI_RX_TOG

RB_HSPI_RX_NUM : parallel if rx sequence num
bits : 0 - 3 (4 bit)

RB_HSPI_RX_TOG : parallel if rx addr toggle flag
bits : 4 - 4 (1 bit)


R8_HSPI_AUX

parallel if aux
address_offset : 0x3 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

R8_HSPI_AUX R8_HSPI_AUX read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 RB_HSPI_TCK_MOD RB_HSPI_RCK_MOD RB_HSPI_ACK_TX_MOD RB_HSPI_ACK_CNT_SEL

RB_HSPI_TCK_MOD : parallel if tx clk polar control
bits : 0 - 0 (1 bit)

RB_HSPI_RCK_MOD : parallel if rx clk polar control
bits : 1 - 1 (1 bit)

RB_HSPI_ACK_TX_MOD : parallel if tx ack mode cfg
bits : 2 - 2 (1 bit)

RB_HSPI_ACK_CNT_SEL : delay time of parallel if send ack when receive done
bits : 3 - 4 (2 bit)


R32_HSPI_TX_ADDR0

parallel if dma tx addr0
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

R32_HSPI_TX_ADDR0 R32_HSPI_TX_ADDR0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RB_HSPI_TX_ADDR0

RB_HSPI_TX_ADDR0 : parallel if dma tx addr0
bits : 0 - 16 (17 bit)


R32_HSPI_TX_ADDR1

parallel if dma tx addr1
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

R32_HSPI_TX_ADDR1 R32_HSPI_TX_ADDR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RB_HSPI_TX_ADDR1

RB_HSPI_TX_ADDR1 : parallel if dma tx addr1
bits : 0 - 16 (17 bit)


R32_HSPI_RX_ADDR0

parallel if dma rx addr0
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

R32_HSPI_RX_ADDR0 R32_HSPI_RX_ADDR0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RB_HSPI_RX_ADDR0

RB_HSPI_RX_ADDR0 : parallel if dma rx addr0
bits : 0 - 16 (17 bit)



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