\n

ECDC

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x400 byte (0x0)
mem_usage : registers
protection :

Registers

R16_ECEC_CTRL

R32_ECDC_KEY_191T160

R32_ECDC_KEY_159T128

R32_ECDC_KEY_127T96

R32_ECDC_KEY_95T64

R8_ECDC_INT_EN

R32_ECDC_KEY_63T32

R32_ECDC_KEY_31T0

R32_ECDC_IV_127T96

R32_ECDC_IV_95T64

R32_ECDC_IV_63T32

R32_ECDC_IV_31T0

R32_ECDC_SGSD_127T96

R32_ECDC_SGSD_95T64

R32_ECDC_SGSD_63T32

R32_ECDC_SGSD_31T0

R32_ECDC_SGRT_127T96

R32_ECDC_SGRT_95T64

R32_ECDC_SGRT_63T32

RB_ECDC_SGRT_31T0

R8_ECDC_INT_FG

R32_ECDC_SRAM_ADDR

R32_ECDC_SRAM_LEN

R32_ECDC_KEY_255T224

R32_ECDC_KEY_223T192


R16_ECEC_CTRL

ECED AES/SM4 register
address_offset : 0x0 Bytes (0x0)
size : 16 bit
reset_value : 0x0
reset_Mask : 0x0

R16_ECEC_CTRL R16_ECEC_CTRL 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RB_ECDC_KEYEX_EN RB_ECDC_RDPERI_EN RB_ECDC_WRPERI_EN RB_ECDC_MODE_SEL RB_ECDC_CLKDIV_MASK RB_ECDC_WRSRAM_EN RB_ECDC_ALGRM_MOD RB_ECDC_CIPHER_MOD RB_ECDC_KLEN_MASK RB_ECDC_DAT_MOD

RB_ECDC_KEYEX_EN : enable key expansion
bits : 0 - 0 (1 bit)
access : read-write

RB_ECDC_RDPERI_EN : when write data to dma
bits : 1 - 1 (1 bit)
access : read-write

RB_ECDC_WRPERI_EN : when read data from dma
bits : 2 - 2 (1 bit)
access : read-write

RB_ECDC_MODE_SEL : ECDC mode select
bits : 3 - 3 (1 bit)
access : read-write

RB_ECDC_CLKDIV_MASK : Clock divide factor
bits : 4 - 6 (3 bit)
access : read-write

RB_ECDC_WRSRAM_EN : module dma enable
bits : 7 - 7 (1 bit)
access : read-write

RB_ECDC_ALGRM_MOD : Encryption and decryption algorithm mode selection
bits : 8 - 8 (1 bit)
access : read-write

RB_ECDC_CIPHER_MOD : Block cipher mode selection
bits : 9 - 9 (1 bit)
access : read-write

RB_ECDC_KLEN_MASK : Key length setting
bits : 10 - 11 (2 bit)
access : read-write

RB_ECDC_DAT_MOD : source data and result data is bit endian
bits : 13 - 13 (1 bit)
access : write-only


R32_ECDC_KEY_191T160

User key 160-191 register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

R32_ECDC_KEY_191T160 R32_ECDC_KEY_191T160 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RB_ECDC_KEY_191T160

RB_ECDC_KEY_191T160 : User key 160-191 register
bits : 0 - 31 (32 bit)


R32_ECDC_KEY_159T128

User key 128-159 register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

R32_ECDC_KEY_159T128 R32_ECDC_KEY_159T128 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RB_ECDC_KEY_159T128

RB_ECDC_KEY_159T128 : User key 128-159 register
bits : 0 - 31 (32 bit)


R32_ECDC_KEY_127T96

User key 96-127 register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

R32_ECDC_KEY_127T96 R32_ECDC_KEY_127T96 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RB_ECDC_KEY_127T96

RB_ECDC_KEY_127T96 : User key 96-127 register
bits : 0 - 31 (32 bit)


R32_ECDC_KEY_95T64

User key 64-95 register
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

R32_ECDC_KEY_95T64 R32_ECDC_KEY_95T64 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RB_ECDC_KEY_95T64

RB_ECDC_KEY_95T64 : User key 64-95 register
bits : 0 - 31 (32 bit)


R8_ECDC_INT_EN

Interupt enable register
address_offset : 0x2 Bytes (0x0)
size : 8 bit
reset_value : 0x0
reset_Mask : 0x0

R8_ECDC_INT_EN R8_ECDC_INT_EN 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 RB_ECDC_IE_EKDONE RB_ECDC_IE_SINGLE RB_ECDC_IE_WRSRAM

RB_ECDC_IE_EKDONE : Key extension completion interrupt enable
bits : 0 - 0 (1 bit)
access : read-write

RB_ECDC_IE_SINGLE : Single encryption and decryption completion interrupt enable
bits : 1 - 1 (1 bit)
access : read-write

RB_ECDC_IE_WRSRAM : Memory to memory encryption and decryption completion interrupt enable
bits : 2 - 2 (1 bit)
access : write-only


R32_ECDC_KEY_63T32

User key 32-63 register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

R32_ECDC_KEY_63T32 R32_ECDC_KEY_63T32 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RB_ECDC_KEY_63T32

RB_ECDC_KEY_63T32 : User key 32-63 register
bits : 0 - 31 (32 bit)


R32_ECDC_KEY_31T0

User key 0-31 register
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

R32_ECDC_KEY_31T0 R32_ECDC_KEY_31T0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RB_ECDC_KEY_31T0

RB_ECDC_KEY_31T0 : User key 0-31 register
bits : 0 - 31 (32 bit)


R32_ECDC_IV_127T96

CTR mode count 96-127 register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

R32_ECDC_IV_127T96 R32_ECDC_IV_127T96 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RB_ECDC_IV_127T96

RB_ECDC_IV_127T96 : CTR mode count 96-127 register
bits : 0 - 31 (32 bit)


R32_ECDC_IV_95T64

CTR mode count 64-95 register
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

R32_ECDC_IV_95T64 R32_ECDC_IV_95T64 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RB_ECDC_IV_95T64

RB_ECDC_IV_95T64 : CTR mode count 64-95 register
bits : 0 - 31 (32 bit)


R32_ECDC_IV_63T32

CTR mode count 32-63 register
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

R32_ECDC_IV_63T32 R32_ECDC_IV_63T32 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RB_ECDC_IV_63T32

RB_ECDC_IV_63T32 : CTR mode count 32-63 register
bits : 0 - 31 (32 bit)


R32_ECDC_IV_31T0

CTR mode count 0-31 register
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

R32_ECDC_IV_31T0 R32_ECDC_IV_31T0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RB_ECDC_IV_31T0

RB_ECDC_IV_31T0 : CTR mode count 0-31 register
bits : 0 - 31 (32 bit)


R32_ECDC_SGSD_127T96

Single encryption and decryption of original data 96-127 register
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

R32_ECDC_SGSD_127T96 R32_ECDC_SGSD_127T96 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RB_ECDC_SGSD_127T96

RB_ECDC_SGSD_127T96 : Single encryption and decryption of original data 96-127 register
bits : 0 - 31 (32 bit)


R32_ECDC_SGSD_95T64

Single encryption and decryption of original data 64-95 register
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

R32_ECDC_SGSD_95T64 R32_ECDC_SGSD_95T64 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RB_ECDC_SGSD_95T64

RB_ECDC_SGSD_95T64 : Single encryption and decryption of original data 64-95 register
bits : 0 - 31 (32 bit)


R32_ECDC_SGSD_63T32

Single encryption and decryption of original data 32-63 register
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

R32_ECDC_SGSD_63T32 R32_ECDC_SGSD_63T32 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RB_ECDC_SGSD_63T32

RB_ECDC_SGSD_63T32 : Single encryption and decryption of original data 32-63 register
bits : 0 - 31 (32 bit)


R32_ECDC_SGSD_31T0

Single encryption and decryption of original data 0-31 register
address_offset : 0x4C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

R32_ECDC_SGSD_31T0 R32_ECDC_SGSD_31T0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RB_ECDC_SGSD_31T0

RB_ECDC_SGSD_31T0 : Single encryption and decryption of original data 0-31 register
bits : 0 - 31 (32 bit)


R32_ECDC_SGRT_127T96

Single encryption and decryption result 96-127 register
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

R32_ECDC_SGRT_127T96 R32_ECDC_SGRT_127T96 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RB_ECDC_SGRT_127T96

RB_ECDC_SGRT_127T96 : Single encryption and decryption result 96-127 register
bits : 0 - 31 (32 bit)


R32_ECDC_SGRT_95T64

Single encryption and decryption result 64-95 register
address_offset : 0x54 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

R32_ECDC_SGRT_95T64 R32_ECDC_SGRT_95T64 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RB_ECDC_SGRT_95T64

RB_ECDC_SGRT_95T64 : Single encryption and decryption result 64-95 register
bits : 0 - 31 (32 bit)


R32_ECDC_SGRT_63T32

Single encryption and decryption result 0-31 register
address_offset : 0x58 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

R32_ECDC_SGRT_63T32 R32_ECDC_SGRT_63T32 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RB_ECDC_SGRT_63T32

RB_ECDC_SGRT_63T32 : Single encryption and decryption result 0-31 register
bits : 0 - 31 (32 bit)


RB_ECDC_SGRT_31T0

Single encryption and decryption result 0-31 register
address_offset : 0x5C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RB_ECDC_SGRT_31T0 RB_ECDC_SGRT_31T0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RB_ECDC_SGRT_31T0

RB_ECDC_SGRT_31T0 : Single encryption and decryption result 0-31 register
bits : 0 - 31 (32 bit)


R8_ECDC_INT_FG

Interupt flag register
address_offset : 0x6 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

R8_ECDC_INT_FG R8_ECDC_INT_FG read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 RB_ECDC_IF_EKDONE RB_ECDC_IF_SINGLE RB_ECDC_IF_WRSRAM

RB_ECDC_IF_EKDONE : Key extension completion interrupt flag
bits : 0 - 0 (1 bit)

RB_ECDC_IF_SINGLE : Single encryption and decryption completion interrupt flag
bits : 1 - 1 (1 bit)

RB_ECDC_IF_WRSRAM : Memory to memory encryption and decryption completion interrupt flag
bits : 2 - 2 (1 bit)


R32_ECDC_SRAM_ADDR

encryption and decryption sram start address register
address_offset : 0x60 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

R32_ECDC_SRAM_ADDR R32_ECDC_SRAM_ADDR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RB_ECDC_SRAM_ADDR

RB_ECDC_SRAM_ADDR : encryption and decryption sram start address register
bits : 0 - 16 (17 bit)


R32_ECDC_SRAM_LEN

encryption and decryption sram size register
address_offset : 0x64 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

R32_ECDC_SRAM_LEN R32_ECDC_SRAM_LEN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RB_ECDC_SRAM_LEN

RB_ECDC_SRAM_LEN : encryption and decryption sram size register
bits : 0 - 12 (13 bit)


R32_ECDC_KEY_255T224

User key 224-255 register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

R32_ECDC_KEY_255T224 R32_ECDC_KEY_255T224 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RB_ECDC_KEY_255T224

RB_ECDC_KEY_255T224 : User key 224-255 register
bits : 0 - 31 (32 bit)


R32_ECDC_KEY_223T192

User key 192-223 register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

R32_ECDC_KEY_223T192 R32_ECDC_KEY_223T192 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RB_ECDC_KEY_223T192

RB_ECDC_KEY_223T192 : User key 192-223 register
bits : 0 - 31 (32 bit)



Is something missing? Is something wrong? can you help correct it ? Please contact us at info@chipselect.org !

This website is sponsored by EmbeetleEmbeetle, an IDE designed from scratch for embedded software developers.