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DVP

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x400 byte (0x0)
mem_usage : registers
protection :

Registers

R8_DVP_CR0

R8_DVP_CR1

R8_DVP_INT_FLAG

R8_DVP_FIFO_ST

R16_DVP_ROW_CNT

R16_DVP_COL_CNT

R8_DVP_INT_EN

R16_DVP_ROW_NUM

R16_DVP_COL_NUM

R32_DVP_DMA_BUF0

R32_DVP_DMA_BUF1


R8_DVP_CR0

DVP control register0
address_offset : 0x0 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

R8_DVP_CR0 R8_DVP_CR0 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 RB_DVP_ENABLE RB_DVP_V_POLAR RB_DVP_H_POLAR RB_DVP_P_POLAR RB_DVP_MSK_DAT_MOD RB_DVP_JPEG RB_DVP_RAW_CM

RB_DVP_ENABLE : DVP enable
bits : 0 - 0 (1 bit)

RB_DVP_V_POLAR : DVP VSYNC polarity control
bits : 1 - 1 (1 bit)

RB_DVP_H_POLAR : DVP HSYNC polarity control
bits : 2 - 2 (1 bit)

RB_DVP_P_POLAR : DVP PCLK polarity control
bits : 3 - 3 (1 bit)

RB_DVP_MSK_DAT_MOD : DVP data bit width confguration
bits : 4 - 5 (2 bit)

RB_DVP_JPEG : DVP JPEG mode
bits : 6 - 6 (1 bit)

RB_DVP_RAW_CM : DVP row count mode
bits : 7 - 7 (1 bit)


R8_DVP_CR1

DVP control register1
address_offset : 0x1 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

R8_DVP_CR1 R8_DVP_CR1 read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 RB_DVP_DMA_ENABLE RB_DVP_ALL_CLR RB_DVP_RCV_CLR RB_DVP_BUF_TOG

RB_DVP_DMA_ENABLE : DVP dma enable
bits : 0 - 0 (1 bit)

RB_DVP_ALL_CLR : DVP all clear, high action
bits : 1 - 1 (1 bit)

RB_DVP_RCV_CLR : DVP receive logic clear, high action
bits : 2 - 2 (1 bit)

RB_DVP_BUF_TOG : DVP bug toggle by software
bits : 3 - 3 (1 bit)


R8_DVP_INT_FLAG

DVP interrupt flag register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

R8_DVP_INT_FLAG R8_DVP_INT_FLAG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RB_DVP_IF_STR_FRM RB_DVP_IF_ROW_DONE RB_DVP_IF_FRM_DONE RB_DVP_IF_FIFO_OV RB_DVP_IF_STP_FRM

RB_DVP_IF_STR_FRM : interrupt flag for DVP frame start
bits : 0 - 0 (1 bit)

RB_DVP_IF_ROW_DONE : interrupt flag for DVP row receive done
bits : 1 - 1 (1 bit)

RB_DVP_IF_FRM_DONE : interrupt flag for DVP frame receive done
bits : 2 - 2 (1 bit)

RB_DVP_IF_FIFO_OV : interrupt flag for DVP receive fifo overflow
bits : 3 - 3 (1 bit)

RB_DVP_IF_STP_FRM : interrupt flag for DVP frame stop
bits : 4 - 4 (1 bit)


R8_DVP_FIFO_ST

DVP receive fifo status
address_offset : 0x11 Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

R8_DVP_FIFO_ST R8_DVP_FIFO_ST read-only 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 RB_DVP_FIFO_RDY RB_DVP_FIFO_FULL RB_DVP_FIFO_OV RB_DVP_MSK_FIFO_CNT

RB_DVP_FIFO_RDY : DVP receive fifo ready
bits : 0 - 0 (1 bit)

RB_DVP_FIFO_FULL : DVP receive fifo full
bits : 1 - 1 (1 bit)

RB_DVP_FIFO_OV : DVP receive fifo overflow
bits : 2 - 2 (1 bit)

RB_DVP_MSK_FIFO_CNT : DVP receive fifo count
bits : 4 - 6 (3 bit)


R16_DVP_ROW_CNT

DVP row count value
address_offset : 0x14 Bytes (0x0)
size : 16 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

R16_DVP_ROW_CNT R16_DVP_ROW_CNT read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RB_DVP_ROW_CNT

RB_DVP_ROW_CNT : DVP receive fifo full
bits : 0 - 15 (16 bit)


R16_DVP_COL_CNT

DVP col count value
address_offset : 0x16 Bytes (0x0)
size : 16 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

R16_DVP_COL_CNT R16_DVP_COL_CNT read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RB_DVP_COL_CNT

RB_DVP_COL_CNT : DVP receive fifo ready
bits : 0 - 15 (16 bit)


R8_DVP_INT_EN

DVP interrupt enable register
address_offset : 0x2 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

R8_DVP_INT_EN R8_DVP_INT_EN read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 RB_DVP_IE_STR_FRM RB_DVP_IE_ROW_DONE RB_DVP_IE_FRM_DONE RB_DVP_IE_FIFO_OV RB_DVP_IE_STP_FRM

RB_DVP_IE_STR_FRM : DVP frame start interrupt enable
bits : 0 - 0 (1 bit)

RB_DVP_IE_ROW_DONE : DVP row received done interrupt enable
bits : 1 - 1 (1 bit)

RB_DVP_IE_FRM_DONE : DVP frame received done interrupt enable
bits : 2 - 2 (1 bit)

RB_DVP_IE_FIFO_OV : DVP receive fifo overflow interrupt enable
bits : 3 - 3 (1 bit)

RB_DVP_IE_STP_FRM : DVP frame stop interrupt enable
bits : 4 - 4 (1 bit)


R16_DVP_ROW_NUM

DVP row number of a frame indicator register
address_offset : 0x4 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

R16_DVP_ROW_NUM R16_DVP_ROW_NUM read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RB_DVP_ROW_NUM

RB_DVP_ROW_NUM : the number of rows contained in a frame of image data
bits : 0 - 15 (16 bit)


R16_DVP_COL_NUM

DVP row number of a frame indicator register
address_offset : 0x6 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

R16_DVP_COL_NUM R16_DVP_COL_NUM read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RB_DVP_COL_NUM

RB_DVP_COL_NUM : the number of PCLK cyccles contained in a row of data in RGB mode
bits : 0 - 15 (16 bit)


R32_DVP_DMA_BUF0

DVP dma buffer0 addr
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

R32_DVP_DMA_BUF0 R32_DVP_DMA_BUF0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RB_DVP_DMA_BUF0

RB_DVP_DMA_BUF0 : the receiving address 0 of DMA
bits : 0 - 16 (17 bit)


R32_DVP_DMA_BUF1

DVP dma buffer1 addr
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

R32_DVP_DMA_BUF1 R32_DVP_DMA_BUF1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RB_DVP_DMA_BUF1

RB_DVP_DMA_BUF1 : the receiving address1 of DMA
bits : 0 - 16 (17 bit)



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