\n
address_offset : 0x0 Bytes (0x0)
size : 0x100 byte (0x0)
mem_usage : registers
protection :
Systick counter control register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
reset_value : 0x0
reset_Mask : 0x0
STE : Systick counter enable
bits : 0 - 0 (1 bit)
access : read-write
STIE : Systick counter interrupt enable
bits : 1 - 1 (1 bit)
access : read-write
STCLK : System counter clock Source selection
bits : 2 - 2 (1 bit)
access : read-write
STRELOAD : System counter reload control
bits : 8 - 8 (1 bit)
access : read-write
Systick compare high register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CMPH : CMPH
bits : 0 - 31 (32 bit)
Systick counter flag
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SWIE : System soft interrupt enable
bits : 0 - 0 (1 bit)
CNTIF : Systick counter clear zero flag
bits : 1 - 1 (1 bit)
Systick counter low register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CNTL : CNTL
bits : 0 - 31 (32 bit)
Systick counter high register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CNTH : CNTH
bits : 0 - 31 (32 bit)
Systick compare low register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CMPL : CMPL
bits : 0 - 31 (32 bit)
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