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Systick

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x100 byte (0x0)
mem_usage : registers
protection :

Registers

STK_CTLR

STK_CMPHR

STK_CNTFG

STK_CNTL

STK_CNTH

STK_CMPLR


STK_CTLR

Systick counter control register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
reset_value : 0x0
reset_Mask : 0x0

STK_CTLR STK_CTLR 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 STE STIE STCLK STRELOAD

STE : Systick counter enable
bits : 0 - 0 (1 bit)
access : read-write

STIE : Systick counter interrupt enable
bits : 1 - 1 (1 bit)
access : read-write

STCLK : System counter clock Source selection
bits : 2 - 2 (1 bit)
access : read-write

STRELOAD : System counter reload control
bits : 8 - 8 (1 bit)
access : read-write


STK_CMPHR

Systick compare high register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

STK_CMPHR STK_CMPHR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CMPH

CMPH : CMPH
bits : 0 - 31 (32 bit)


STK_CNTFG

Systick counter flag
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

STK_CNTFG STK_CNTFG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SWIE CNTIF

SWIE : System soft interrupt enable
bits : 0 - 0 (1 bit)

CNTIF : Systick counter clear zero flag
bits : 1 - 1 (1 bit)


STK_CNTL

Systick counter low register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

STK_CNTL STK_CNTL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CNTL

CNTL : CNTL
bits : 0 - 31 (32 bit)


STK_CNTH

Systick counter high register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

STK_CNTH STK_CNTH read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CNTH

CNTH : CNTH
bits : 0 - 31 (32 bit)


STK_CMPLR

Systick compare low register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

STK_CMPLR STK_CMPLR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CMPL

CMPL : CMPL
bits : 0 - 31 (32 bit)



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