\n

RCC

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x400 byte (0x0)
mem_usage : registers
protection :

Registers

CTLR

APB1PRSTR

AHBPCENR

APB2PCENR

APB1PCENR

BDCTLR

RSTSCKR

AHBRSTR

CFGR0

INTR

APB2PRSTR


CTLR

Clock control register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
reset_value : 0x0
reset_Mask : 0x0

CTLR CTLR 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HSION HSIRDY HSITRIM HSICAL HSEON HSERDY HSEBYP CSSON PLLON PLLRDY

HSION : Internal High Speed clock enable
bits : 0 - 0 (1 bit)
access : read-write

HSIRDY : Internal High Speed clock ready flag
bits : 1 - 1 (1 bit)
access : read-only

HSITRIM : Internal High Speed clock trimming
bits : 3 - 7 (5 bit)
access : read-write

HSICAL : Internal High Speed clock Calibration
bits : 8 - 15 (8 bit)
access : read-only

HSEON : External High Speed clock enable
bits : 16 - 16 (1 bit)
access : read-write

HSERDY : External High Speed clock ready flag
bits : 17 - 17 (1 bit)
access : read-only

HSEBYP : External High Speed clock Bypass
bits : 18 - 18 (1 bit)
access : read-write

CSSON : Clock Security System enable
bits : 19 - 19 (1 bit)
access : read-write

PLLON : PLL enable
bits : 24 - 24 (1 bit)
access : read-write

PLLRDY : PLL clock ready flag
bits : 25 - 25 (1 bit)
access : read-only


APB1PRSTR

PB1 peripheral reset register(RCC_APB1PRSTR)
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

APB1PRSTR APB1PRSTR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TIM2RST TIM3RST TIM4RST WWDGRST SPI2RST USART2RST USART3RST I2C1RST I2C2RST USBDRST CANRST BKPRST PWRRST DACRST

TIM2RST : Timer 2 reset
bits : 0 - 0 (1 bit)

TIM3RST : Timer 3 reset
bits : 1 - 1 (1 bit)

TIM4RST : Timer 4 reset
bits : 2 - 2 (1 bit)

WWDGRST : Window watchdog reset
bits : 11 - 11 (1 bit)

SPI2RST : SPI2 reset
bits : 14 - 14 (1 bit)

USART2RST : USART 2 reset
bits : 17 - 17 (1 bit)

USART3RST : USART 3 reset
bits : 18 - 18 (1 bit)

I2C1RST : I2C1 reset
bits : 21 - 21 (1 bit)

I2C2RST : I2C2 reset
bits : 22 - 22 (1 bit)

USBDRST : USBD reset
bits : 23 - 23 (1 bit)

CANRST : CAN reset
bits : 25 - 25 (1 bit)

BKPRST : Backup interface reset
bits : 27 - 27 (1 bit)

PWRRST : Power interface reset
bits : 28 - 28 (1 bit)

DACRST : DAC interface reset
bits : 29 - 29 (1 bit)


AHBPCENR

HB Peripheral Clock enable register(RCC_AHBPCENR)
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AHBPCENR AHBPCENR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMAEN SRAMEN FLITFEN CRCEN USBHDEN

DMAEN : DMA clock enable
bits : 0 - 0 (1 bit)

SRAMEN : SRAM interface clock enable
bits : 2 - 2 (1 bit)

FLITFEN : FLITF clock enable
bits : 4 - 4 (1 bit)

CRCEN : CRC clock enable
bits : 6 - 6 (1 bit)

USBHDEN : USBHD clock enable
bits : 12 - 12 (1 bit)


APB2PCENR

PB2 peripheral clock enable register (RCC_APB2PCENR)
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

APB2PCENR APB2PCENR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AFIOEN IOPAEN IOPBEN IOPCEN IOPDEN ADCEN TIM1EN SPI1EN USART1EN

AFIOEN : Alternate function I/O clock enable
bits : 0 - 0 (1 bit)

IOPAEN : I/O port A clock enable
bits : 2 - 2 (1 bit)

IOPBEN : I/O port B clock enable
bits : 3 - 3 (1 bit)

IOPCEN : I/O port C clock enable
bits : 4 - 4 (1 bit)

IOPDEN : I/O port D clock enable
bits : 5 - 5 (1 bit)

ADCEN : ADC interface clock enable
bits : 9 - 9 (1 bit)

TIM1EN : TIM1 Timer clock enable
bits : 11 - 11 (1 bit)

SPI1EN : SPI 1 clock enable
bits : 12 - 12 (1 bit)

USART1EN : USART1 clock enable
bits : 14 - 14 (1 bit)


APB1PCENR

PB1 peripheral clock enable register (RCC_APB1PCENR)
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

APB1PCENR APB1PCENR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TIM2EN TIM3EN TIM4EN WWDGEN SPI2EN USART2EN USART3EN I2C1EN I2C2EN USBDEN CANEN BKPEN PWREN DACEN

TIM2EN : Timer 2 clock enable
bits : 0 - 0 (1 bit)

TIM3EN : Timer 3 clock enable
bits : 1 - 1 (1 bit)

TIM4EN : Timer 4 clock enable
bits : 2 - 2 (1 bit)

WWDGEN : Window watchdog clock enable
bits : 11 - 11 (1 bit)

SPI2EN : SPI 2 clock enable
bits : 14 - 14 (1 bit)

USART2EN : USART 2 clock enable
bits : 17 - 17 (1 bit)

USART3EN : USART 3 clock enable
bits : 18 - 18 (1 bit)

I2C1EN : I2C 1 clock enable
bits : 21 - 21 (1 bit)

I2C2EN : I2C 2 clock enable
bits : 22 - 22 (1 bit)

USBDEN : USBD clock enable
bits : 23 - 23 (1 bit)

CANEN : CAN clock enable
bits : 25 - 25 (1 bit)

BKPEN : Backup interface clock enable
bits : 27 - 27 (1 bit)

PWREN : Power interface clock enable
bits : 28 - 28 (1 bit)

DACEN : DAC interface clock enable
bits : 29 - 29 (1 bit)


BDCTLR

Backup domain control register(RCC_BDCTLR)
address_offset : 0x20 Bytes (0x0)
size : 32 bit
reset_value : 0x0
reset_Mask : 0x0

BDCTLR BDCTLR 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LSEON LSERDY LSEBYP RTCSEL RTCEN BDRST

LSEON : External Low Speed oscillator enable
bits : 0 - 0 (1 bit)
access : read-write

LSERDY : External Low Speed oscillator ready
bits : 1 - 1 (1 bit)
access : read-only

LSEBYP : External Low Speed oscillator bypass
bits : 2 - 2 (1 bit)
access : read-write

RTCSEL : RTC clock source selection
bits : 8 - 9 (2 bit)
access : read-write

RTCEN : RTC clock enable
bits : 15 - 15 (1 bit)
access : read-write

BDRST : Backup domain software reset
bits : 16 - 16 (1 bit)
access : read-write


RSTSCKR

Control/status register(RCC_RSTSCKR)
address_offset : 0x24 Bytes (0x0)
size : 32 bit
reset_value : 0x0
reset_Mask : 0x0

RSTSCKR RSTSCKR 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LSION LSIRDY RMVF PINRSTF PORRSTF SFTRSTF IWDGRSTF WWDGRSTF LPWRRSTF

LSION : Internal low speed oscillator enable
bits : 0 - 0 (1 bit)
access : read-write

LSIRDY : Internal low speed oscillator ready
bits : 1 - 1 (1 bit)
access : read-only

RMVF : Remove reset flag
bits : 24 - 24 (1 bit)
access : read-write

PINRSTF : PIN reset flag
bits : 26 - 26 (1 bit)
access : read-write

PORRSTF : POR/PDR reset flag
bits : 27 - 27 (1 bit)
access : read-write

SFTRSTF : Software reset flag
bits : 28 - 28 (1 bit)
access : read-write

IWDGRSTF : Independent watchdog reset flag
bits : 29 - 29 (1 bit)
access : read-write

WWDGRSTF : Window watchdog reset flag
bits : 30 - 30 (1 bit)
access : read-write

LPWRRSTF : Low-power reset flag
bits : 31 - 31 (1 bit)
access : read-write


AHBRSTR

HB reset register(RCC_APHBRSTR)
address_offset : 0x28 Bytes (0x0)
size : 32 bit
reset_value : 0x0
reset_Mask : 0x0

AHBRSTR AHBRSTR 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 USBHDRST

USBHDRST : USBHD reset
bits : 12 - 12 (1 bit)
access : read-write


CFGR0

Clock configuration register(RCC_CFGR0)
address_offset : 0x4 Bytes (0x0)
size : 32 bit
reset_value : 0x0
reset_Mask : 0x0

CFGR0 CFGR0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SW SWS HPRE PPRE1 PPRE2 ADCPRE PLLSRC PLLXTPRE PLLMUL USBPRE MCO

SW : System clock Switch
bits : 0 - 1 (2 bit)
access : read-write

SWS : System Clock Switch Status
bits : 2 - 3 (2 bit)
access : read-only

HPRE : HB prescaler
bits : 4 - 7 (4 bit)
access : read-write

PPRE1 : PB Low speed prescaler(APB1)
bits : 8 - 10 (3 bit)
access : read-write

PPRE2 : PB High speed prescaler(APB2)
bits : 11 - 13 (3 bit)
access : read-write

ADCPRE : ADC prescaler
bits : 14 - 15 (2 bit)
access : read-write

PLLSRC : PLL entry clock source
bits : 16 - 16 (1 bit)
access : read-write

PLLXTPRE : HSE divider for PLL entry
bits : 17 - 17 (1 bit)
access : read-write

PLLMUL : PLL Multiplication Factor
bits : 18 - 21 (4 bit)
access : read-write

USBPRE : USB prescaler
bits : 22 - 22 (1 bit)
access : read-write

MCO : Microcontroller clock output
bits : 24 - 26 (3 bit)
access : read-write


INTR

Clock interrupt register(RCC_INTR)
address_offset : 0x8 Bytes (0x0)
size : 32 bit
reset_value : 0x0
reset_Mask : 0x0

INTR INTR 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LSIRDYF LSERDYF HSIRDYF HSERDYF PLLRDYF CSSF LSIRDYIE LSERDYIE HSIRDYIE HSERDYIE PLLRDYIE LSIRDYC LSERDYC HSIRDYC HSERDYC PLLRDYC CSSC

LSIRDYF : LSI Ready Interrupt flag
bits : 0 - 0 (1 bit)
access : read-only

LSERDYF : LSE Ready Interrupt flag
bits : 1 - 1 (1 bit)
access : read-only

HSIRDYF : HSI Ready Interrupt flag
bits : 2 - 2 (1 bit)
access : read-only

HSERDYF : HSE Ready Interrupt flag
bits : 3 - 3 (1 bit)
access : read-only

PLLRDYF : PLL Ready Interrupt flag
bits : 4 - 4 (1 bit)
access : read-only

CSSF : Clock Security System Interrupt flag
bits : 7 - 7 (1 bit)
access : read-only

LSIRDYIE : LSI Ready Interrupt Enable
bits : 8 - 8 (1 bit)
access : read-write

LSERDYIE : LSE Ready Interrupt Enable
bits : 9 - 9 (1 bit)
access : read-write

HSIRDYIE : HSI Ready Interrupt Enable
bits : 10 - 10 (1 bit)
access : read-write

HSERDYIE : HSE Ready Interrupt Enable
bits : 11 - 11 (1 bit)
access : read-write

PLLRDYIE : PLL Ready Interrupt Enable
bits : 12 - 12 (1 bit)
access : read-write

LSIRDYC : LSI Ready Interrupt Clear
bits : 16 - 16 (1 bit)
access : write-only

LSERDYC : LSE Ready Interrupt Clear
bits : 17 - 17 (1 bit)
access : write-only

HSIRDYC : HSI Ready Interrupt Clear
bits : 18 - 18 (1 bit)
access : write-only

HSERDYC : HSE Ready Interrupt Clear
bits : 19 - 19 (1 bit)
access : write-only

PLLRDYC : PLL Ready Interrupt Clear
bits : 20 - 20 (1 bit)
access : write-only

CSSC : Clock security system interrupt clear
bits : 23 - 23 (1 bit)
access : write-only


APB2PRSTR

PB2 peripheral reset register(RCC_APB2PRSTR)
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

APB2PRSTR APB2PRSTR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AFIORST IOPARST IOPBRST IOPCRST IOPDRST ADCRST TIM1RST SPI1RST USART1RST

AFIORST : Alternate function I/O reset
bits : 0 - 0 (1 bit)

IOPARST : IO port A reset
bits : 2 - 2 (1 bit)

IOPBRST : IO port B reset
bits : 3 - 3 (1 bit)

IOPCRST : IO port C reset
bits : 4 - 4 (1 bit)

IOPDRST : IO port D reset
bits : 5 - 5 (1 bit)

ADCRST : ADC interface reset
bits : 9 - 9 (1 bit)

TIM1RST : TIM1 timer reset
bits : 11 - 11 (1 bit)

SPI1RST : SPI 1 reset
bits : 12 - 12 (1 bit)

USART1RST : USART1 reset
bits : 14 - 14 (1 bit)



Is something missing? Is something wrong? can you help correct it ? Please contact us at info@chipselect.org !

This website is sponsored by EmbeetleEmbeetle, an IDE designed from scratch for embedded software developers.