\n

DBG

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x400 byte (0x0)
mem_usage : registers
protection :

Registers

CR1

CR2


CR1

DBGMCU_CR1
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CR1 CR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IWDG_STOP WWDG_STOP I2C1_SMBUS_TIMEOUT I2C2_SMBUS_TIMEOUT TIM1_STOP TIM2_STOP TIM3_STOP TIM4_STOP

IWDG_STOP : IWDG_STOP
bits : 0 - 0 (1 bit)

WWDG_STOP : WWDG_STOP
bits : 1 - 1 (1 bit)

I2C1_SMBUS_TIMEOUT : I2C1_SMBUS_TIMEOUT
bits : 2 - 2 (1 bit)

I2C2_SMBUS_TIMEOUT : I2C2_SMBUS_TIMEOUT
bits : 3 - 3 (1 bit)

TIM1_STOP : TIM1_STOP
bits : 4 - 4 (1 bit)

TIM2_STOP : TIM2_STOP
bits : 5 - 5 (1 bit)

TIM3_STOP : TIM3_STOP
bits : 6 - 6 (1 bit)

TIM4_STOP : TIM4_STOP
bits : 7 - 7 (1 bit)


CR2

DBGMCU_CR2
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CR2 CR2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SLEEP STOP STANDBY

SLEEP : DBG_SLEEP
bits : 0 - 0 (1 bit)

STOP : DBG_STOP
bits : 1 - 1 (1 bit)

STANDBY : DBG_STANDBY
bits : 2 - 2 (1 bit)



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