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FLASH

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x400 byte (0x0)
mem_usage : registers
protection :

Registers

ACTLR

CTLR

ADDR

OBR

WPR

MODEKEYR

KEYR

OBKEYR

STATR


ACTLR

Flash access control register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
reset_value : 0x0
reset_Mask : 0x0

ACTLR ACTLR 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LATENCY PRFTBE PRFTBS

LATENCY : Latency
bits : 0 - 2 (3 bit)
access : read-write

PRFTBE : Prefetch buffer enable
bits : 4 - 4 (1 bit)
access : read-write

PRFTBS : Prefetch buffer status
bits : 5 - 5 (1 bit)
access : read-only


CTLR

Control register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CTLR CTLR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PG PER MER OBPG OBER STRT LOCK OPTWRE ERRIE EOPIE FLOCK FTPG FTER BUFLOAD BUFRST

PG : Programming
bits : 0 - 0 (1 bit)

PER : Page Erase
bits : 1 - 1 (1 bit)

MER : Mass Erase
bits : 2 - 2 (1 bit)

OBPG : Option byte programming
bits : 4 - 4 (1 bit)

OBER : Option byte erase
bits : 5 - 5 (1 bit)

STRT : Start
bits : 6 - 6 (1 bit)

LOCK : Lock
bits : 7 - 7 (1 bit)

OPTWRE : Option bytes write enable
bits : 9 - 9 (1 bit)

ERRIE : Error interrupt enable
bits : 10 - 10 (1 bit)

EOPIE : End of operation interrupt enable
bits : 12 - 12 (1 bit)

FLOCK : FAST programming lock
bits : 15 - 15 (1 bit)

FTPG : execute fast programming
bits : 16 - 16 (1 bit)

FTER : execute fast 128byte erase
bits : 17 - 17 (1 bit)

BUFLOAD : execute data load inner buffer
bits : 18 - 18 (1 bit)

BUFRST : execute inner buffer reset
bits : 19 - 19 (1 bit)


ADDR

Flash address register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

ADDR ADDR write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FAR

FAR : Flash Address
bits : 0 - 31 (32 bit)


OBR

Option byte register
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

OBR OBR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OPTERR RDPRT IWDGSW STOPRST STANDYRST USBDMODE USBDPU PORCTR

OPTERR : Option byte error
bits : 0 - 0 (1 bit)

RDPRT : Read protection
bits : 1 - 1 (1 bit)

IWDGSW : IWDG_SW
bits : 2 - 2 (1 bit)

STOPRST : nRST_STOP
bits : 3 - 3 (1 bit)

STANDYRST : nRST_STDBY
bits : 4 - 4 (1 bit)

USBDMODE : USBD compatible speed mode configure
bits : 5 - 5 (1 bit)

USBDPU : USBD compatible inner pull up resistance configure
bits : 6 - 6 (1 bit)

PORCTR : Power on reset time
bits : 7 - 7 (1 bit)


WPR

Write protection register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

WPR WPR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WRP

WRP : Write protect
bits : 0 - 31 (32 bit)


MODEKEYR

Extension key register
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

MODEKEYR MODEKEYR write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MODEKEYR

MODEKEYR : high speed write /erase mode ENABLE
bits : 0 - 31 (32 bit)


KEYR

Flash key register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

KEYR KEYR write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 KEYR

KEYR : FPEC key
bits : 0 - 31 (32 bit)


OBKEYR

Flash option key register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

OBKEYR OBKEYR write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OBKEYR

OBKEYR : Option byte key
bits : 0 - 31 (32 bit)


STATR

Status register
address_offset : 0xC Bytes (0x0)
size : 32 bit
reset_value : 0x0
reset_Mask : 0x0

STATR STATR 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BSY PGERR WRPRTERR EOP

BSY : Busy
bits : 0 - 0 (1 bit)
access : read-only

PGERR : Programming error
bits : 2 - 2 (1 bit)
access : read-write

WRPRTERR : Write protection error
bits : 4 - 4 (1 bit)
access : read-write

EOP : End of operation
bits : 5 - 5 (1 bit)
access : read-write



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