\n
address_offset : 0x0 Bytes (0x0)
size : 0x400 byte (0x0)
mem_usage : registers
protection :
RW, function pin alternate configuration
address_offset : 0x18 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RB_PIN_TMR0 : RW, TMR0 alternate pin enable
bits : 0 - 0 (1 bit)
RB_PIN_TMR1 : RW, TMR1 alternate pin enable
bits : 1 - 1 (1 bit)
RB_PIN_TMR2 : RW, TMR2 alternate pin enable
bits : 2 - 2 (1 bit)
RB_PIN_UART0 : RW, RXD0/TXD0 alternate pin enable
bits : 4 - 4 (1 bit)
RB_PIN_UART1 : RW, RXD1/TXD1 alternate pin enable
bits : 5 - 5 (1 bit)
RB_PIN_SPI0 : RW, SCS/SCK0/MOSI/MISO alternate pin enable
bits : 8 - 8 (1 bit)
RW, analog pin enable and digital input disable
address_offset : 0x1A Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RB_PIN_USB_DP_PU : RW,USB UDP internal pullup resistance enable
bits : 6 - 6 (1 bit)
RB_PIN_USB_IE : RW, USB analog I/O enable: 0=analog I/O disable, 1=analog I/O enable
bits : 7 - 7 (1 bit)
RB_PIN_ADC8_9_IE : RW, ADC/TouchKey channel 9/8 digital input disable: 0=digital input enable, 1=digital input disable
bits : 8 - 8 (1 bit)
RB_PIN_ADC0_IE : RW, ADC/TouchKey channel0 digital input disable: 0=digital input enable, 1=digital input disable
bits : 9 - 9 (1 bit)
RB_PIN_ADC1_IE : RW, ADC/TouchKey channel1 digital input disable: 0=digital input enable, 1=digital input disable
bits : 10 - 10 (1 bit)
RB_PIN_ADC12_IE : RW, ADC/TouchKey channel12 digital input disable: 0=digital input enable, 1=digital input disable
bits : 11 - 11 (1 bit)
RB_PIN_ADC13_IE : RW, ADC/TouchKey channel13 digital input disable: 0=digital input enable, 1=digital input disable
bits : 12 - 12 (1 bit)
RB_PIN_XT32K_IE : RW, external 32KHz oscillator digital input disable: 0=digital input enable, 1=digital input disable
bits : 13 - 13 (1 bit)
RB_PIN_ADC2_3_IE : RW, ADC/TouchKey channel 2/3 digital input disable: 0=digital input enable, 1=digital input disable
bits : 14 - 14 (1 bit)
RB_PIN_ADC4_5_IE : RW, ADC/TouchKey channel 4/5 digital input disable: 0=digital input enable, 1=digital input disable
bits : 15 - 15 (1 bit)
RWA, power plan before sleep instruction, SAM
address_offset : 0x20 Bytes (0x0)
size : 16 bit
access : Read or Write under safe Accessing mode
reset_value : 0x0
reset_Mask : 0x0
RB_PWR_XROM : RWA, power for retention 2KB SRAM
bits : 0 - 0 (1 bit)
RB_PWR_RAM2K : RWA, power for retention 2KB SRAM
bits : 1 - 1 (1 bit)
RB_PWR_CORE : RWA, power retention for core and base peripherals
bits : 2 - 2 (1 bit)
RB_PWR_EXTEND : RWA, power retention for USB and BLE
bits : 3 - 3 (1 bit)
RB_PWR_RAM16K : RWA, power for main SRAM
bits : 4 - 4 (1 bit)
RB_PWR_SYS_EN : RWA, power for system
bits : 7 - 7 (1 bit)
RB_PWR_LDO_EN : RWA, LDO enable
bits : 8 - 8 (1 bit)
RB_PWR_DCDC_EN : RWA, DC/DC converter enable: 0=DC/DC disable and bypass, 1=DC/DC enable
bits : 9 - 9 (1 bit)
RB_PWR_DCDC_PRE : RWA, DC/DC converter pre-enable
bits : 10 - 10 (1 bit)
RB_PWR_MUST_0010 : RWA, power plan enable, auto clear after sleep executed
bits : 11 - 14 (4 bit)
access : read-only
RB_PWR_PLAN_EN : RWA, must write 0010
bits : 15 - 15 (1 bit)
access : read-only
RWA, aux power adjust control, SAM
address_offset : 0x22 Bytes (0x0)
size : 8 bit
access : Read or Write under safe Accessing mode
reset_value : 0x0
reset_Mask : 0x0
RB_ULPLDO_ADJ : RWA, Ultra-Low-Power LDO voltage adjust
bits : 0 - 2 (3 bit)
access : read-write
RWA, battery voltage detector control, SAM
address_offset : 0x24 Bytes (0x0)
size : 8 bit
access : Read / Write under safe Accessing mode
reset_value : 0x0
reset_Mask : 0x0
RB_BAT_DET_EN/RB_BAT_LOW_VTHX : RWA, battery voltage detector enable/select monitor threshold voltage
bits : 0 - 0 (1 bit)
RB_BAT_MON_EN : RWA, battery voltage monitor enable under sleep mode
bits : 1 - 1 (1 bit)
RB_BAT_LOWER_IE : RWA, interrupt enable for battery lower voltage
bits : 2 - 2 (1 bit)
RB_BAT_LOW_IE : RWA, interrupt enable for battery low voltage
bits : 3 - 3 (1 bit)
RWA, battery voltage detector configuration, SAM
address_offset : 0x25 Bytes (0x0)
size : 8 bit
access : Read or Write under safe Accessing mode
reset_value : 0x0
reset_Mask : 0x0
RB_BAT_LOW_VTH : RWA, select threshold voltage of battery voltage low
bits : 0 - 1 (2 bit)
RO, battery status
address_offset : 0x26 Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RB_BAT_STAT_LOWER : RO, battery lower voltage status, high action
bits : 0 - 0 (1 bit)
RB_BAT_STAT_LOW : RO, battery low voltage status, high action
bits : 1 - 1 (1 bit)
RWA, internal 32KHz oscillator tune control, SAM
address_offset : 0x2C Bytes (0x0)
size : 16 bit
access : Read or Write under safe Accessing mode
reset_value : 0x0
reset_Mask : 0x0
RB_INT32K_TUNE : RWA, internal 32KHz oscillator frequency tune
bits : 0 - 11 (12 bit)
RWA, external 32KHz oscillator tune control, SAM
address_offset : 0x2E Bytes (0x0)
size : 8 bit
access : Read or Write under safe Accessing mode
reset_value : 0x0
reset_Mask : 0x0
RB_XT32K_I_TUNE : RWA, external 32KHz oscillator current tune: 00=75% current, 01=standard current, 10=150% current, 11=200% current
bits : 0 - 1 (2 bit)
RB_XT32K_C_LOAD : RWA, external 32KHz oscillator load capacitor tune: Cap = RB_XT32K_C_LOAD + 12pF
bits : 4 - 7 (4 bit)
RWA, 32KHz oscillator configure
address_offset : 0x2F Bytes (0x0)
size : 8 bit
access : Read or Write under safe Accessing mode
reset_value : 0x0
reset_Mask : 0x0
RB_CLK_XT32K_PON : RWA, external 32KHz oscillator power on
bits : 0 - 0 (1 bit)
access : read-write
RB_CLK_INT32K_PON : RWA, internal 32KHz oscillator power on
bits : 1 - 1 (1 bit)
access : read-write
RB_CLK_OSC32K_XT : RWA, 32KHz oscillator source selection: 0=RC, 1=XT
bits : 2 - 2 (1 bit)
access : read-write
RB_32K_CLK_PIN : RO, 32KHz oscillator clock pin status
bits : 7 - 7 (1 bit)
access : read-only
RW, RTC flag and clear control
address_offset : 0x30 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RB_RTC_TMR_CLR : RW, set 1 to clear RTC timer action flag, auto clear
bits : 4 - 4 (1 bit)
access : read-write
RB_RTC_TRIG_CLR : RW, set 1 to clear RTC trigger action flag, auto clear
bits : 5 - 5 (1 bit)
access : read-write
RB_RTC_TMR_FLAG : RO, RTC timer action flag
bits : 6 - 6 (1 bit)
access : read-only
RB_RTC_TRIG_FLAG : RO, RTC trigger action flag
bits : 7 - 7 (1 bit)
access : read-only
RWA, RTC mode control, SAM
address_offset : 0x31 Bytes (0x0)
size : 8 bit
access : Read or Write under safe Accessing mode
reset_value : 0x0
reset_Mask : 0x0
RB_RTC_TMR_MODE : RWA, RTC timer mode: 000=0.125S, 001=0.25S, 010=0.5S, 011=1S, 100=2S, 101=4S, 110=8S, 111=16S
bits : 0 - 2 (3 bit)
RB_RTC_IGNORE_B0 : RWA, force ignore bit0 for trigger mode: 0=compare bit0, 1=ignore bit0
bits : 3 - 3 (1 bit)
RB_RTC_TMR_EN : RWA, RTC timer mode enable
bits : 4 - 4 (1 bit)
RB_RTC_TRIG_EN : RWA, RTC trigger mode enable
bits : 5 - 5 (1 bit)
RB_RTC_LOAD_LO : RWA, set 1 to load RTC count low word R32_RTC_CNT_32K, auto clear after loaded
bits : 6 - 6 (1 bit)
RB_RTC_LOAD_HI : RWA, set 1 to load RTC count high word R32_RTC_CNT_DAY, auto clear after loaded
bits : 7 - 7 (1 bit)
RWA, RTC trigger value, SAM
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : Read or Write under safe Accessing mode
reset_value : 0x0
reset_Mask : 0x0
R32_RTC_TRIG : RWA, RTC trigger value
bits : 0 - 31 (32 bit)
RO, RTC count based 32KHz
address_offset : 0x38 Bytes (0x0)
size : 16 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
R16_RTC_CNT_32K : RWA,RTC count based 32KHz
bits : 0 - 15 (16 bit)
RO, RTC count based 2 second
address_offset : 0x3A Bytes (0x0)
size : 16 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
R16_RTC_CNT_2S : RO, RTC count based 2 second
bits : 0 - 15 (16 bit)
RO, RTC count based one day, only low 14 bit
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
R32_RTC_CNT_DAY : RWA,RTC count based one day
bits : 0 - 13 (14 bit)
RWA, reset status, SAM or flash ROM configuration
address_offset : 0x4 Bytes (0x0)
size : 8 bit
access : -Read only for Fixed value
reset_value : 0x0
reset_Mask : 0x0
RB_RESET_FLAG : RO, recent reset flag
bits : 0 - 2 (3 bit)
access : read-only
RB_ROM_CODE_OFS : RWA, code offset address selection in Flash ROM: 0=start address 0x000000, 1=start address 0x008000
bits : 4 - 4 (1 bit)
access : read-write
RB_ROM_CTRL_EN : RWA, enable flash ROM control interface enable
bits : 5 - 5 (1 bit)
access : read-write
RB_ROM_DATA_WE : RWA,enable flash ROM data and code area being erase/write
bits : 6 - 6 (1 bit)
access : read-write
RB_ROM_CODE_WE : RWA, enable flash ROM code area being erase or write
bits : 7 - 7 (1 bit)
access : read-write
WO, safe accessing sign register, must write SAFE_ACCESS_SIG1 then SAFE_ACCESS_SIG2 to enter safe accessing mode
address_offset : 0x40 Bytes (0x0)
size : 8 bit
access : read/write
reset_value : 0x0
reset_Mask : 0x0
RB_SAFE_ACC_MODE : RO, current safe accessing mode: 11=safe unlocked (SAM), other=locked (00..01..10..11)
bits : 0 - 1 (2 bit)
R8_SAFE_ACCESS_SIG : WO, safe accessing sign register, must write 0x57 then 0xA8 to enter safe accessing mode
bits : 0 - 7 (8 bit)
RB_SAFE_ACC_ACT : RO, indicate safe accessing status now: 0=locked, read only, 1=safe/unlocked (SAM), write enabled
bits : 3 - 3 (1 bit)
RB_SAFE_ACC_TIMER : RO, safe accessing timer bit mask (16*clock number)
bits : 4 - 6 (3 bit)
RF, chip ID register, always is ID_CH57*
address_offset : 0x41 Bytes (0x0)
size : 8 bit
access : -Read only for Fixed value
reset_value : 0x0
reset_Mask : 0x0
R8_CHIP_ID : RF,chip ID register
bits : 0 - 7 (8 bit)
RF, safe accessing ID register, always 0x04
address_offset : 0x42 Bytes (0x0)
size : 8 bit
access : -Read only for Fixed value
reset_value : 0x0
reset_Mask : 0x0
R8_SAFE_ACCESS_ID : RF,safe accessing ID register
bits : 0 - 7 (8 bit)
RW, watch-dog count, count by clock frequency Fsys/131072
address_offset : 0x43 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
R8_WDOG_COUNT : RF,watch-dog count, count by clock frequency Fsys/131072
bits : 0 - 7 (8 bit)
RO, global configuration information and status
address_offset : 0x45 Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RB_CFG_ROM_READ : RO, indicate protected status of Flash ROM code and data: 0=reading protect, 1=enable read by external programmer
bits : 0 - 0 (1 bit)
RB_CFG_RESET_EN : RO, manual reset input enable status
bits : 2 - 2 (1 bit)
RB_CFG_BOOT_EN : RO, boot-loader enable status
bits : 3 - 3 (1 bit)
RB_CFG_DEBUG_EN : RO, debug enable status
bits : 4 - 4 (1 bit)
RB_BOOT_LOADER : RO, indicate boot loader status: 0=application status (by software reset), 1=boot loader status
bits : 5 - 5 (1 bit)
RWA, reset and watch-dog control, SAM
address_offset : 0x46 Bytes (0x0)
size : 8 bit
access : Read or Write under safe Accessing mode
reset_value : 0x0
reset_Mask : 0x0
RB_SOFTWARE_RESET : WA or WZ, global software reset, high action, auto clear
bits : 0 - 0 (1 bit)
RB_WDOG_RST_EN : RWA, enable watch-dog reset if watch-dog timer overflow: 0=as timer only, 1=enable reset if timer overflow
bits : 1 - 1 (1 bit)
RB_WDOG_INT_EN : RWA, watch-dog timer overflow interrupt enable: 0=disable, 1=enable
bits : 2 - 2 (1 bit)
RB_WDOG_INT_FLAG : RW1, watch-dog timer overflow interrupt flag, cleared by RW1 or reload watch-dog count or __SEV(Send-Event)
bits : 4 - 4 (1 bit)
RW, value keeper during global reset
address_offset : 0x47 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
R8_GLOB_RESET_KEEP : RW, value keeper during global reset
bits : 0 - 7 (8 bit)
RWA, PLL configuration control, SAM
address_offset : 0x4B Bytes (0x0)
size : 8 bit
access : Read or Write under safe Accessing mode
reset_value : 0x0
reset_Mask : 0x0
RB_PLL_CFG_DAT : RWA, PLL configure data
bits : 0 - 6 (7 bit)
access : read-write
RWA, external 32MHz oscillator tune control, SAM
address_offset : 0x4E Bytes (0x0)
size : 8 bit
access : Read or Write under safe Accessing mode
reset_value : 0x0
reset_Mask : 0x0
RB_XT32M_I_BIAS : RWA, external 32MHz oscillator bias current tune: 00=75% current, 01=standard current, 10=125% current, 11=150% current
bits : 0 - 1 (2 bit)
access : read-write
RB_XT32M_C_LOAD : RWA, external 32MHz oscillator load capacitor tune: Cap = RB_XT32M_C_LOAD * 2 + 10pF
bits : 4 - 6 (3 bit)
access : read-write
RO, system clock count value for 32KHz 5 cycles
address_offset : 0x50 Bytes (0x0)
size : 16 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RB_OSC_CAL_CNT : RO, system clock count value for 32KHz 5 cycles
bits : 0 - 13 (14 bit)
RWA, oscillator frequency calibration control, SAM
address_offset : 0x52 Bytes (0x0)
size : 8 bit
access : Read or Write under safe Accessing mode
reset_value : 0x0
reset_Mask : 0x0
RB_OSC_CNT_EN : RWA, calibration counter enable
bits : 0 - 0 (1 bit)
access : read-write
RB_OSC_CNT_HALT : RO, calibration counter halt status: 0=counting, 1=halt for reading count value
bits : 1 - 1 (1 bit)
access : read-only
RW, Touchkey charge and discharge count
address_offset : 0x54 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RB_TKEY_CHARG_CNT : RW, Touchkey charge count
bits : 0 - 4 (5 bit)
RB_TKEY_DISCH_CNT : RW, Touchkey discharge count
bits : 5 - 7 (3 bit)
RW, Touchkey convert start control
address_offset : 0x56 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RB_TKEY_START : RW, Touchkey convert start control
bits : 0 - 0 (1 bit)
RW, Touchkey configure
address_offset : 0x57 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RB_TKEY_PWR_ON : RW, Touchkey power on
bits : 0 - 0 (1 bit)
RB_TKEY_CURRENT : RW, Touchkey charge current selection
bits : 1 - 1 (1 bit)
RB_TKEY_PGA_ADJ : RW, ADC input PGA speed selection
bits : 3 - 3 (1 bit)
RW, ADC input channel selection
address_offset : 0x58 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RB_ADC_CH_INX : RW, ADC input channel index
bits : 0 - 3 (4 bit)
RW, ADC configure
address_offset : 0x59 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RB_ADC_POWER_ON : RW, ADC power control: 0=power down, 1=power on
bits : 0 - 0 (1 bit)
RB_ADC_BUF_EN : RW, ADC input buffer enable
bits : 1 - 1 (1 bit)
RB_ADC_DIFF_EN : RW, ADC input channel mode: 0=single-end, 1=differnetial
bits : 2 - 2 (1 bit)
RB_ADC_OFS_TEST : RW, enable ADC offset test mode: 0=normal mode, 1=short port4 to test offset
bits : 3 - 3 (1 bit)
RB_ADC_PGA_GAIN : RW, set ADC input PGA gain: 00=-12dB, 01=-6dB, 10=0dB, 11=6dB
bits : 4 - 5 (2 bit)
RB_ADC_CLK_DIV : RW, select ADC clock frequency: 00=3.2MHz, 01=2.67MHz, 10=5.33MHz, 11=4MHz
bits : 6 - 7 (2 bit)
RW, ADC convert control
address_offset : 0x5A Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RB_ADC_START : RW, ADC convert start control: 0=stop ADC convert, 1=start an ADC convert, auto clear
bits : 0 - 0 (1 bit)
access : read-write
RB_ADC_EOC_X : RO, end of ADC conversion flag
bits : 7 - 7 (1 bit)
access : read-only
RW, temperature sensor control
address_offset : 0x5B Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RB_TEM_SEN_PWR_ON : RW, temperature sensor power control: 0=power down, 1=power on
bits : 7 - 7 (1 bit)
RO, ADC data
address_offset : 0x5C Bytes (0x0)
size : 16 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RB_ADC_DATA : RO, ADC conversion data
bits : 0 - 11 (12 bit)
RO, ADC interrupt flag register
address_offset : 0x5E Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RB_ADC_IF_EOC : RO, ADC conversion interrupt flag: 0=free or converting, 1=end of conversion, interrupt action, write R8_ADC_CONVERT to clear flag
bits : 7 - 7 (1 bit)
RO, ADC interrupt flag register
address_offset : 0x5E Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
RB_ADC_IF_EOC : RW, ADC conversion interrupt flag: 0=free or converting, 1=end of conversion, interrupt action, write R8_ADC_CONVERT to clear flag
bits : 7 - 7 (1 bit)
RO, ADC DMA control and status register
address_offset : 0x60 Bytes (0x0)
size : 8 bit
access : write-read
reset_value : 0x0
reset_Mask : 0x0
R32_ADC_DMA_CTRL : RW, ADC DMA enable
bits : 0 - 7 (8 bit)
RW, ADC DMA control
address_offset : 0x61 Bytes (0x0)
size : 8 bit
access : write-read
reset_value : 0x0
reset_Mask : 0x0
RB_ADC_DMA_ENABLE : RW, ADC DMA enable
bits : 0 - 0 (1 bit)
RB_ADC_DMA_LOOP : RW, ADC DMA address loop enable
bits : 2 - 2 (1 bit)
RB_ADC_IE_DMA_END : RW, enable interrupt for ADC DMA completion
bits : 3 - 3 (1 bit)
RB_ADC_IE_EOC : RW, enable interrupt for end of ADC conversion
bits : 4 - 4 (1 bit)
RB_ADC_AUTO_EN : RW, enable auto continuing ADC for DMA
bits : 7 - 7 (1 bit)
RO, ADC interrupt flag
address_offset : 0x62 Bytes (0x0)
size : 8 bit
access : write-read
reset_value : 0x0
reset_Mask : 0x0
RB_ADC_IF_DMA_END : interrupt flag for ADC DMA completion
bits : 3 - 3 (1 bit)
RB_ADC_IF_END_ADC : interrupt flag for end of ADC conversion
bits : 4 - 4 (1 bit)
RO, ADC interrupt flag
address_offset : 0x63 Bytes (0x0)
size : 8 bit
access : write-read
reset_value : 0x0
reset_Mask : 0x0
R8_ADC_AUTO_CYCLE : auto ADC cycle value, unit is 16 Fsys
bits : 0 - 7 (8 bit)
RO, ADC DMA current address
address_offset : 0x64 Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
R16_ADC_DMA_NOW : ADC DMA current address
bits : 0 - 15 (16 bit)
RW, ADC DMA begin address
address_offset : 0x68 Bytes (0x0)
size : 8 bit
access : write-read
reset_value : 0x0
reset_Mask : 0x0
R16_ADC_DMA_BEG : ADC DMA begin address
bits : 0 - 15 (16 bit)
RW, ADC DMA end address
address_offset : 0x6C Bytes (0x0)
size : 8 bit
access : write-read
reset_value : 0x0
reset_Mask : 0x0
R16_ADC_DMA_END : ADC DMA end address
bits : 0 - 15 (16 bit)
RWA, system clock configuration, SAM
address_offset : 0x8 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RB_CLK_PLL_DIV : RWA, output clock divider from PLL or CK32M
bits : 0 - 4 (5 bit)
access : read-write
RB_CLK_SYS_MOD : RWA, system clock source mode: 00=divided from 32MHz, 01=divided from PLL-480MHz, 10=directly from 32MHz, 11=directly from 32KHz
bits : 6 - 7 (2 bit)
access : read-write
RW, GPIO PA interrupt enable
address_offset : 0x90 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
R16_PA_INT_EN : GPIO PA interrupt enable
bits : 0 - 15 (16 bit)
RW, GPIO PB interrupt enable
address_offset : 0x92 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
R16_PB_INT_EN : GPIO PB interrupt enable
bits : 0 - 15 (16 bit)
RW, GPIO PA interrupt mode: 0=level action, 1=edge action
address_offset : 0x94 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
R16_PA_INT_MODE : GPIO PA interrupt mode
bits : 0 - 15 (16 bit)
RW, GPIO PB interrupt mode: 0=level action, 1=edge action RW, status for parallel slave read
address_offset : 0x96 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
R16_PB_INT_MODE : GPIO PB interrupt mode
bits : 0 - 15 (16 bit)
RW1, GPIO PA interrupt flag
address_offset : 0x9C Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
R16_PA_INT_IF : GPIO PA interrupt flag
bits : 0 - 15 (16 bit)
RW1, GPIO PB interrupt flag
address_offset : 0x9E Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
R16_PB_INT_IF : GPIO PB interrupt flag
bits : 0 - 15 (16 bit)
RWA, high frequency clock module power control, SAM
address_offset : 0xA Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RB_CLK_XT32M_PON : RWA, external 32MHz oscillator power control: 0=power down, 1-power on
bits : 2 - 2 (1 bit)
RB_CLK_PLL_PON : RWA, PLL power control: 0=power down, 1-power on
bits : 4 - 4 (1 bit)
RW, GPIO PA I/O direction: 0=in, 1=out
address_offset : 0xA0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
R8_PA_DIR_0 : GPIO PA I/O direction byte 0
bits : 0 - 7 (8 bit)
R8_PA_DIR_1 : GPIO PA I/O direction byte 1
bits : 8 - 15 (8 bit)
RO, GPIO PA input
address_offset : 0xA4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
R8_PA_PIN_0 : GPIO PA input byte 0
bits : 0 - 7 (8 bit)
R8_PA_PIN_1 : GPIO PA input byte 1
bits : 8 - 15 (8 bit)
RW, GPIO PA output
address_offset : 0xA8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
R8_PA_OUT_0 : GPIO PA output byte 0
bits : 0 - 7 (8 bit)
R8_PA_OUT_1 : GPIO PA output byte 1
bits : 8 - 15 (8 bit)
WZ, GPIO PA clear output: 0=keep, 1=clear
address_offset : 0xAC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
R8_PA_CLR_0 : GPIO PA clear output byte 0
bits : 0 - 7 (8 bit)
R8_PA_CLR_1 : GPIO PA clear output byte 1
bits : 8 - 15 (8 bit)
RW, GPIO PA pullup resistance enable
address_offset : 0xB0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
R8_PA_PU_0 : GPIO PA pullup resistance enable byte 0
bits : 0 - 7 (8 bit)
R8_PA_PU_1 : GPIO PA pullup resistance enable byte 0
bits : 8 - 15 (8 bit)
RW, PA pulldown for input or PA driving capability for output
address_offset : 0xB4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
R8_PA_PD_DRV_0 : PA pulldown for input or PA driving capability for output byte 0
bits : 0 - 7 (8 bit)
R8_PA_PD_DRV_1 : PA pulldown for input or PA driving capability for output byte 1
bits : 8 - 15 (8 bit)
RWA, sleep clock off control byte 0, SAM
address_offset : 0xC Bytes (0x0)
size : 8 bit
access : Read or Write under safe Accessing mode
reset_value : 0x0
reset_Mask : 0x0
RB_SLP_CLK_TMR0 : RWA, close TMR0 clock
bits : 0 - 0 (1 bit)
RB_SLP_CLK_TMR1 : RWA, close TMR1 clock
bits : 1 - 1 (1 bit)
RB_SLP_CLK_TMR2 : RWA, close TMR2 clock
bits : 2 - 2 (1 bit)
RB_SLP_CLK_TMR3 : RWA, close TMR3 clock
bits : 3 - 3 (1 bit)
RB_SLP_CLK_UART0 : RWA, close UART0 clock
bits : 4 - 4 (1 bit)
RB_SLP_CLK_UART1 : RWA, close UART1 clock
bits : 5 - 5 (1 bit)
RB_SLP_CLK_UART2 : RWA, close UART2 clock
bits : 6 - 6 (1 bit)
RB_SLP_CLK_UART3 : RWA, close UART3 clock
bits : 7 - 7 (1 bit)
RW, GPIO PB I/O direction: 0=in, 1=out
address_offset : 0xC0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
R8_PB_DIR_0 : GPIO PB I/O direction byte 0
bits : 0 - 7 (8 bit)
R8_PB_DIR_1 : GPIO PB I/O direction byte 1
bits : 8 - 15 (8 bit)
R8_PB_DIR_2 : GPIO PB I/O direction byte 2
bits : 16 - 23 (8 bit)
RO, GPIO PB input
address_offset : 0xC4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
R8_PB_PIN_0 : GPIO PB input byte 0
bits : 0 - 7 (8 bit)
R8_PB_PIN_1 : GPIO PB input byte 1
bits : 8 - 15 (8 bit)
R8_PB_PIN_2 : GPIO PB input byte 2
bits : 16 - 23 (8 bit)
RW, GPIO PB output RW, data for parallel slave read
address_offset : 0xC8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
R8_PB_OUT_0 : GPIO PB output byte 0
bits : 0 - 7 (8 bit)
R8_PB_OUT_1 : GPIO PB output byte 1
bits : 8 - 15 (8 bit)
R8_PB_OUT_2 : GPIO PB output byte 2
bits : 16 - 23 (8 bit)
WZ, GPIO PB clear output: 0=keep, 1=clear
address_offset : 0xCC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
R8_PB_CLR_0 : GPIO PB clear output byte 0
bits : 0 - 7 (8 bit)
R8_PB_CLR_1 : GPIO PB clear output byte 1
bits : 8 - 15 (8 bit)
R8_PB_CLR_2 : GPIO PB clear output byte 2
bits : 16 - 23 (8 bit)
RWA, sleep clock off control byte 1, SAM
address_offset : 0xD Bytes (0x0)
size : 8 bit
access : Read or Write under safe Accessing mode
reset_value : 0x0
reset_Mask : 0x0
RB_SLP_CLK_SPI0 : RWA, close SPI0 clock
bits : 0 - 0 (1 bit)
RB_SLP_CLK_PWMX : RWA, close PWMx clock
bits : 2 - 2 (1 bit)
RB_SLP_CLK_USB : RWA, close USB clock
bits : 4 - 4 (1 bit)
RB_SLP_CLK_BLE : RWA, close BLE clock
bits : 7 - 7 (1 bit)
RW, GPIO PB pullup resistance enable
address_offset : 0xD0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
R8_PB_PU_0 : GPIO PB pullup resistance enable byte 0
bits : 0 - 7 (8 bit)
R8_PB_PU_1 : GPIO PB pullup resistance enable byte 1
bits : 8 - 15 (8 bit)
R8_PB_PU_2 : GPIO PB pullup resistance enable byte 2
bits : 16 - 23 (8 bit)
RW, PB pulldown for input or PB driving capability for output
address_offset : 0xD4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
R8_PB_PD_DRV_0 : PB pulldown for input or PB driving capability for output byte 0
bits : 0 - 7 (8 bit)
R8_PB_PD_DRV_1 : PB pulldown for input or PB driving capability for output byte 0
bits : 8 - 15 (8 bit)
R8_PB_PD_DRV_2 : PB pulldown for input or PB driving capability for output byte 0
bits : 16 - 23 (8 bit)
RWA, wake control, SAM
address_offset : 0xE Bytes (0x0)
size : 8 bit
access : Read or Write under safe Accessing mode
reset_value : 0x0
reset_Mask : 0x0
RB_SLP_USB_WAKE : RWA, enable USB waking
bits : 0 - 0 (1 bit)
RB_SLP_RTC_WAKE : RWA, enable RTC waking
bits : 3 - 3 (1 bit)
RB_SLP_GPIO_WAKE : RWA, enable GPIO waking
bits : 4 - 4 (1 bit)
RB_SLP_BAT_WAKE : RWA, enable BAT waking
bits : 5 - 5 (1 bit)
RB_WAKE_EV_MODE : RWA, event wakeup mode
bits : 6 - 6 (1 bit)
RB_WAKE_DELAY : RWA, wakeup delay
bits : 7 - 7 (1 bit)
RWA, peripherals power down control, SAM
address_offset : 0xF Bytes (0x0)
size : 8 bit
access : Read or Write under safe Accessing mode
reset_value : 0x0
reset_Mask : 0x0
RB_SLP_CLK_RAMX : RWA, close main SRAM clock
bits : 4 - 4 (1 bit)
RB_SLP_CLK_RAM2K : RWA, close retention 2KB SRAM clock
bits : 5 - 5 (1 bit)
RB_RAM_RET_LV : RWA, SRAM retention voltage selection
bits : 6 - 6 (1 bit)
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