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TMR

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x400 byte (0x0)
mem_usage : registers
protection :

Registers

R8_TMR3_CTRL_MOD

R32_TMR3_FIFO

R8_TMR3_INTER_EN

R8_TMR3_INT_FLAG

R8_TMR3_FIFO_COUNT

R32_TMR3_COUNT

R32_TMR3_CNT_END


R8_TMR3_CTRL_MOD

RW, TMR3 mode control
address_offset : 0x0 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

R8_TMR3_CTRL_MOD R8_TMR3_CTRL_MOD read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 RB_TMR_MODE_IN RB_TMR_ALL_CLEAR RB_TMR_COUNT_EN RB_TMR_OUT_EN RB_TMR_OUT_POLAR/RB_TMR_CAP_COUNT RB_TMR_PWM_REPEAT/RB_TMR_CAP_EDGE

RB_TMR_MODE_IN : RW, timer in mode: 0=timer/PWM, 1=capture/count
bits : 0 - 0 (1 bit)

RB_TMR_ALL_CLEAR : RW, force clear timer FIFO and count
bits : 1 - 1 (1 bit)

RB_TMR_COUNT_EN : RW, timer count enable
bits : 2 - 2 (1 bit)

RB_TMR_OUT_EN : RW, timer output enable
bits : 3 - 3 (1 bit)

RB_TMR_OUT_POLAR/RB_TMR_CAP_COUNT : RW, timer PWM output polarity: 0=default low and high action, 1=default high and low action RW, count sub-mode if RB_TMR_MODE_IN=1: 0=capture, 1=count
bits : 4 - 4 (1 bit)

RB_TMR_PWM_REPEAT/RB_TMR_CAP_EDGE : RW, timer PWM repeat mode: 00=1, 01=4, 10=8, 11-16 RW, timer capture edge mode: 00=disable, 01=edge change, 10=fall to fall, 11-rise to rise
bits : 6 - 7 (2 bit)


R32_TMR3_FIFO

RO/WO, TMR3 FIFO register, only low 26 bit
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-only or write-only
reset_value : 0x0
reset_Mask : 0x0

R32_TMR3_FIFO R32_TMR3_FIFO read-only or write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R32_TMR3_FIFO

R32_TMR3_FIFO : RO/WO, TMR3 FIFO register, only low 26 bit
bits : 0 - 31 (32 bit)


R8_TMR3_INTER_EN

RW, TMR3 interrupt enable
address_offset : 0x2 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

R8_TMR3_INTER_EN R8_TMR3_INTER_EN read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 RB_TMR_IE_CYC_END RB_TMR_IE_DATA_ACT RB_TMR_IE_FIFO_HF RB_TMR_IE_DMA_END RB_TMR_IE_FIFO_OV

RB_TMR_IE_CYC_END : RW, enable interrupt for timer capture count timeout or PWM cycle end
bits : 0 - 0 (1 bit)

RB_TMR_IE_DATA_ACT : RW, enable interrupt for timer capture input action or PWM trigger
bits : 1 - 1 (1 bit)

RB_TMR_IE_FIFO_HF : RW, enable interrupt for timer FIFO half (capture fifo >=4 or PWM fifo less than 3)
bits : 2 - 2 (1 bit)

RB_TMR_IE_DMA_END : RW, enable interrupt for timer1/2 DMA completion
bits : 3 - 3 (1 bit)

RB_TMR_IE_FIFO_OV : RW, enable interrupt for timer FIFO overflow
bits : 4 - 4 (1 bit)


R8_TMR3_INT_FLAG

RW1, TMR3 interrupt flag
address_offset : 0x6 Bytes (0x0)
size : 8 bit
access : Read or Write 1 to Clear
reset_value : 0x0
reset_Mask : 0x0

R8_TMR3_INT_FLAG R8_TMR3_INT_FLAG Read or Write 1 to Clear 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 RB_TMR_IF_CYC_END RB_TMR_IF_DATA_ACT RB_TMR_IF_FIFO_HF RB_TMR_IF_DMA_END RB_TMR_IF_FIFO_OV

RB_TMR_IF_CYC_END : RW1, interrupt flag for timer capture count timeout or PWM cycle end
bits : 0 - 0 (1 bit)

RB_TMR_IF_DATA_ACT : RW1, interrupt flag for timer capture input action or PWM trigger
bits : 1 - 1 (1 bit)

RB_TMR_IF_FIFO_HF : RW1, interrupt flag for timer FIFO half (capture fifo >=4 or PWM fifo less than 3
bits : 2 - 2 (1 bit)

RB_TMR_IF_DMA_END : RW1, interrupt flag for timer1/2 DMA completion
bits : 3 - 3 (1 bit)

RB_TMR_IF_FIFO_OV : RW1, interrupt flag for timer FIFO overflow
bits : 4 - 4 (1 bit)


R8_TMR3_FIFO_COUNT

RO, TMR3 FIFO count status
address_offset : 0x7 Bytes (0x0)
size : 8 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

R8_TMR3_FIFO_COUNT R8_TMR3_FIFO_COUNT read-only 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 R8_TMR3_FIFO_COUNT

R8_TMR3_FIFO_COUNT : R0, TMR3 FIFO count status
bits : 0 - 7 (8 bit)


R32_TMR3_COUNT

RO, TMR3 current count
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

R32_TMR3_COUNT R32_TMR3_COUNT read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R32_TMR3_COUNT

R32_TMR3_COUNT : R0, TMR3 current count
bits : 0 - 31 (32 bit)


R32_TMR3_CNT_END

RW, TMR3 end count value, only low 26 bit
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

R32_TMR3_CNT_END R32_TMR3_CNT_END read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R32_TMR3_CNT_END

R32_TMR3_CNT_END : RW, TMR3 end count value, only low 26 bit
bits : 0 - 31 (32 bit)



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