R8_UART0_MCR

R8_UART0_IER

R8_UART0_FCR

R8_UART0_LCR

R8_UART0_IIR

R8_UART0_LSR

R8_UART0_MSR

R8_UART0_RBR

R8_UART0_THR

R8_UART0_RFC

R8_UART0_TFC

R16_UART0_DL

R8_UART0_DIV

R8_UART0_ADR

RB_MCR_DTR : RW, UART0 control DTR
bits : 0 - 0 (1 bit)

RB_MCR_RTS : RW, UART0 control RTS
bits : 1 - 1 (1 bit)

RB_MCR_OUT1 : RW, UART0 control OUT1
bits : 2 - 2 (1 bit)

RB_MCR_OUT2/RB_MCR_INT_OE : RW, UART control OUT2/ UART interrupt output enable
bits : 3 - 3 (1 bit)

RB_MCR_LOOP : RW, UART0 enable local loop back
bits : 4 - 4 (1 bit)

RB_MCR_AU_FLOW_EN : RW, UART0 enable autoflow control
bits : 5 - 5 (1 bit)

RB_MCR_TNOW : RW, UART0 enable TNOW output on DTR pin
bits : 6 - 6 (1 bit)

RB_MCR_HALF : RW, UART0 enable half-duplex
bits : 7 - 7 (1 bit)

RB_IER_RECV_RDY : RW, UART interrupt enable for receiver data ready
bits : 0 - 0 (1 bit)

RB_IER_THR_EMPTY : RW, UART interrupt enable for THR empty
bits : 1 - 1 (1 bit)

RB_IER_LINE_STAT : RW, UART interrupt enable for receiver line status
bits : 2 - 2 (1 bit)

RB_IER_MODEM_CHG : RW, UART0 interrupt enable for modem status change
bits : 3 - 3 (1 bit)

RB_IER_DTR_EN : RW, UART0 DTR/TNOW output pin enable
bits : 4 - 4 (1 bit)

RB_IER_RTS_EN : RW, UART0 RTS output pin enable
bits : 5 - 5 (1 bit)

RB_IER_TXD_EN : RW, UART TXD pin enable
bits : 6 - 6 (1 bit)

RB_IER_RESET : WZ, UART software reset control, high action, auto clear
bits : 7 - 7 (1 bit)

RB_FCR_FIFO_EN : RW, UART FIFO enable
bits : 0 - 0 (1 bit)

RB_FCR_RX_FIFO_CLR : WZ, clear UART receiver FIFO, high action, auto clear
bits : 1 - 1 (1 bit)

RB_FCR_TX_FIFO_CLR : WZ, clear UART transmitter FIFO, high action, auto clear
bits : 2 - 2 (1 bit)

RB_FCR_FIFO_TRIG : RW, UART receiver FIFO trigger level: 00-1byte, 01-2bytes, 10-4bytes, 11-7bytes
bits : 6 - 7 (2 bit)

RB_LCR_WORD_SZ : RW, UART word bit length: 00-5bit, 01-6bit, 10-7bit, 11-8bit
bits : 0 - 1 (2 bit)

RB_LCR_STOP_BIT : RW, UART stop bit length: 0-1bit, 1-2bit
bits : 2 - 2 (1 bit)

RB_LCR_PAR_EN : RW, UART parity enable
bits : 3 - 3 (1 bit)

RB_LCR_PAR_MOD : RW, UART parity mode: 00-odd, 01-even, 10-mark, 11-space
bits : 4 - 5 (2 bit)

RB_LCR_BREAK_EN : RW, UART break control enable
bits : 6 - 6 (1 bit)

RB_LCR_GP_BIT/RB_LCR_DLAB : RW, UART general purpose bit RW, UART reserved bit
bits : 7 - 7 (1 bit)

RB_IIR_NO_INT : RO, UART no interrupt flag: 0=interrupt action, 1=no interrupt
bits : 0 - 0 (1 bit)

RB_IIR_INT_MASK : RO, UART interrupt flag bit mask
bits : 0 - 3 (4 bit)

RB_IIR_FIFO_ID : RO, UART FIFO enabled flag
bits : 6 - 7 (2 bit)

RB_LSR_DATA_RDY : RO, UART receiver fifo data ready status
bits : 0 - 0 (1 bit)

RB_LSR_OVER_ERR : RZ, UART receiver overrun error
bits : 1 - 1 (1 bit)

RB_LSR_PAR_ERR : RZ, UART receiver parity error
bits : 2 - 2 (1 bit)

RB_LSR_FRAME_ERR : RZ, UART receiver frame error
bits : 3 - 3 (1 bit)

RB_LSR_BREAK_ERR : RZ, UART receiver break error
bits : 4 - 4 (1 bit)

RB_LSR_TX_FIFO_EMP : RO, UART transmitter fifo empty status
bits : 5 - 5 (1 bit)

RB_LSR_TX_ALL_EMP : RO, UART transmitter all empty status
bits : 6 - 6 (1 bit)

RB_LSR_ERR_RX_FIFO : RO, indicate error in UART receiver fifo
bits : 7 - 7 (1 bit)

RB_MSR_CTS_CHG : RZ, UART0 CTS changed status, high action
bits : 0 - 0 (1 bit)
access : read-only

RB_MSR_DSR_CHG : RZ, UART0 DSR changed status, high action
bits : 1 - 1 (1 bit)
access : read-only

RB_MSR_RI_CHG : RZ, UART0 RI changed status, high action
bits : 2 - 2 (1 bit)

RB_MSR_DCD_CHG : RZ, UART0 DCD changed status, high action
bits : 3 - 3 (1 bit)

RB_MSR_CTS : RO, UART0 CTS action status
bits : 4 - 4 (1 bit)

RB_MSR_DSR : RO, UART0 DSR action statusv
bits : 5 - 5 (1 bit)

RB_MSR_RI : RO, UART0 RI action status
bits : 6 - 6 (1 bit)

RB_MSR_DCD : RO, UART0 DCD action status
bits : 7 - 7 (1 bit)

R8_UART0_RBR : RO, UART0 receiver buffer, receiving byte
bits : 0 - 7 (8 bit)

R8_UART0_THR : RO, UART0 transmitter holding, transmittal byte
bits : 0 - 7 (8 bit)

R8_UART0_RFC : RO, UART0 receiver FIFO count
bits : 0 - 7 (8 bit)

R8_UART0_TFC : RO, UART0 transmitter FIFO count
bits : 0 - 7 (8 bit)

R16_UART0_DL : RW, UART0 divisor latch
bits : 0 - 15 (16 bit)

R8_UART0_DIV : RW,UART0 pre-divisor latch byte, only low 7 bit, from 1 to 0/128
bits : 0 - 7 (8 bit)

R8_UART0_ADR : RW,UART0 slave address: 0xFF=disable, other=enable
bits : 0 - 7 (8 bit)