R8_SPI0_CTRL_MOD

R8_SPI0_CTRL_CFG

R8_SPI0_FIFO

R8_SPI0_FIFO_COUNT1

R16_SPI0_DMA_NOW

R16_SPI0_DMA_BEG

R16_SPI0_DMA_END

R8_SPI0_INTER_EN

R8_SPI0_CLOCK_DIV__R8_SPI0_SLAVE_PRE

R8_SPI0_BUFFER

R8_SPI0_RUN_FLAG

R8_SPI0_INT_FLAG

R8_SPI0_FIFO_COUNT

R16_SPI0_TOTAL_CNT

RB_SPI_MODE_SLAVE : RW, SPI0 slave mode: 0=master or host, 1=slave or device
bits : 0 - 0 (1 bit)

RB_SPI_ALL_CLEAR : RW, force clear SPI FIFO and count
bits : 1 - 1 (1 bit)

RB_SPI_2WIRE_MOD : RW, SPI0 enable 2 wire mode for slave: 0=3wire(SCK0,MOSI,MISO), 1=2wire(SCK0,MISO=MXSX)
bits : 2 - 2 (1 bit)

RB_SPI_MST_SCK_MOD__RB_SPI_SLV_CMD_MOD : RW, SPI master clock mode: 0=mode 0, 1=mode 3 RW, SPI0 slave command mode: 0=byte stream, 1=first byte command
bits : 3 - 3 (1 bit)

RB_SPI_FIFO_DIR : RW, SPI FIFO direction: 0=out(write @master mode), 1=in(read @master mode)
bits : 4 - 4 (1 bit)

RB_SPI_SCK_OE : RW, SPI SCK output enable
bits : 5 - 5 (1 bit)

RB_SPI_MOSI_OE : RW, SPI MOSI output enable
bits : 6 - 6 (1 bit)

RB_SPI_MISO_OE : RW, SPI MISO output enable
bits : 7 - 7 (1 bit)

RB_SPI_DMA_ENABLE : RW, SPI0 DMA enable
bits : 0 - 0 (1 bit)

RB_SPI_DMA_LOOP : RW, SPI0 DMA address loop enable
bits : 2 - 2 (1 bit)

RB_SPI_AUTO_IF : RW, enable buffer/FIFO accessing to auto clear RB_SPI_IF_BYTE_END interrupt flag
bits : 4 - 4 (1 bit)

RB_SPI_BIT_ORDER : RW, SPI bit data order: 0=MSB first, 1=LSB first
bits : 5 - 5 (1 bit)

RB_SPI_MST_DLY_EN : RW, SPI master input delay enable
bits : 6 - 6 (1 bit)

R8_SPI0_FIFO : RO/WO, SPI0 FIFO register
bits : 0 - 7 (8 bit)

R8_SPI0_FIFO_COUNT1 : RO, SPI0 FIFO count status
bits : 0 - 7 (8 bit)

R16_SPI0_DMA_NOW : RW, SPI0 DMA current address
bits : 0 - 15 (16 bit)

R16_SPI0_DMA_BEG : RW, SPI0 DMA begin address
bits : 0 - 15 (16 bit)

R16_SPI0_DMA_END : RW, SPI0 DMA end address
bits : 0 - 15 (16 bit)

RB_SPI_IE_CNT_END : RW, enable interrupt for SPI total byte count end
bits : 0 - 0 (1 bit)

RB_SPI_IE_BYTE_END : RW, enable interrupt for SPI byte exchanged
bits : 1 - 1 (1 bit)

RB_SPI_IE_FIFO_HF : RW, enable interrupt for SPI FIFO half
bits : 2 - 2 (1 bit)

RB_SPI_IE_DMA_END : RW, enable interrupt for SPI0 DMA completion
bits : 3 - 3 (1 bit)

RB_SPI_IE_FIFO_OV : RW, enable interrupt for SPI0 FIFO overflow
bits : 4 - 4 (1 bit)

RB_SPI_IE_FST_BYTE : RW, enable interrupt for SPI0 slave mode first byte received
bits : 7 - 7 (1 bit)

R8_SPI0_CLOCK_DIV__R8_SPI0_SLAVE_PRE : RW, SPI0 master clock divisor RW, SPI0 slave preset value
bits : 0 - 7 (8 bit)

R8_SPI0_BUFFER : RW, SPI0 data buffer
bits : 0 - 7 (8 bit)

RB_SPI_SLV_CMD_ACT : RO, SPI0 slave first byte or command flag
bits : 4 - 4 (1 bit)

RB_SPI_FIFO_READY : RO, SPI FIFO ready status
bits : 5 - 5 (1 bit)

RB_SPI_SLV_CS_LOAD : RO, SPI0 slave chip-select loading status
bits : 6 - 6 (1 bit)

RB_SPI_SLV_SELECT : RO, SPI0 slave selection status
bits : 7 - 7 (1 bit)

RB_SPI_IF_CNT_END : RW1, interrupt flag for SPI total byte count end
bits : 0 - 0 (1 bit)

RB_SPI_IF_BYTE_END : RW1, interrupt flag for SPI byte exchanged
bits : 1 - 1 (1 bit)

RB_SPI_IF_FIFO_HF : RW1, interrupt flag for SPI FIFO half
bits : 2 - 2 (1 bit)

RB_SPI_IF_DMA_END : RW1, interrupt flag for SPI0 DMA completion
bits : 3 - 3 (1 bit)

RB_SPI_IF_FIFO_OV : RW1, interrupt flag for SPI0 FIFO overflow
bits : 4 - 4 (1 bit)

RB_SPI_FREE : RO, current SPI free status
bits : 6 - 6 (1 bit)

RB_SPI_IF_FST_BYTE : RW1, interrupt flag for SPI0 slave mode first byte received
bits : 7 - 7 (1 bit)

R8_SPI0_FIFO_COUNT : RO, SPI0 FIFO count status
bits : 0 - 7 (8 bit)

R16_SPI0_TOTAL_CNT : RW, SPI0 total byte count, only low 12 bit
bits : 0 - 15 (16 bit)