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PWMx

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x400 byte (0x0)
mem_usage : registers
protection :

Registers

R8_PWM_OUT_EN

R8_PWM_POLAR

R8_PWM_CONFIG

R8_PWM_CLOCK_DIV

R8_PWM4_DATA

R8_PWM5_DATA

R8_PWM6_DATA

R8_PWM7_DATA

R8_PWM8_DATA

R8_PWM9_DATA

R8_PWM10_DATA

R8_PWM11_DATA

R8_PWM_INT_CTRL


R8_PWM_OUT_EN

RW, PWM output enable control
address_offset : 0x0 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

R8_PWM_OUT_EN R8_PWM_OUT_EN read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 RB_PWM4_OUT_EN RB_PWM5_OUT_EN RB_PWM6_OUT_EN RB_PWM7_OUT_EN RB_PWM8_OUT_EN RB_PWM9_OUT_EN RB_PWM10_OUT_EN RB_PWM11_OUT_EN

RB_PWM4_OUT_EN : RW, PWM4 output enable
bits : 0 - 0 (1 bit)

RB_PWM5_OUT_EN : RW, PWM5 output enable
bits : 1 - 1 (1 bit)

RB_PWM6_OUT_EN : RW, PWM6 output enable
bits : 2 - 2 (1 bit)

RB_PWM7_OUT_EN : RW, PWM7 output enable
bits : 3 - 3 (1 bit)

RB_PWM8_OUT_EN : RW, PWM8 output enable
bits : 4 - 4 (1 bit)

RB_PWM9_OUT_EN : RW, PWM9 output enable
bits : 5 - 5 (1 bit)

RB_PWM10_OUT_EN : RW, PWM10 output enable
bits : 6 - 6 (1 bit)

RB_PWM11_OUT_EN : RW, PWM11 output enable
bits : 7 - 7 (1 bit)


R8_PWM_POLAR

RW, PWM output polarity control
address_offset : 0x1 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

R8_PWM_POLAR R8_PWM_POLAR read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 RB_PWM4_POLAR RB_PWM5_POLAR RB_PWM6_POLAR RB_PWM7_POLAR RB_PWM8_POLAR RB_PWM9_POLAR RB_PWM10_POLAR RB_PWM11_POLAR

RB_PWM4_POLAR : RW, PWM4 output polarity: 0=default low and high action, 1=default high and low action
bits : 0 - 0 (1 bit)

RB_PWM5_POLAR : RW, PWM5 output polarity: 0=default low and high action, 1=default high and low action
bits : 1 - 1 (1 bit)

RB_PWM6_POLAR : RW, PWM6 output polarity: 0=default low and high action, 1=default high and low action
bits : 2 - 2 (1 bit)

RB_PWM7_POLAR : RW, PWM7 output polarity: 0=default low and high action, 1=default high and low action
bits : 3 - 3 (1 bit)

RB_PWM8_POLAR : RW, PWM8 output polarity: 0=default low and high action, 1=default high and low action
bits : 4 - 4 (1 bit)

RB_PWM9_POLAR : RW, PWM9 output polarity: 0=default low and high action, 1=default high and low action
bits : 5 - 5 (1 bit)

RB_PWM10_POLAR : RW, PWM10 output polarity: 0=default low and high action, 1=default high and low action
bits : 6 - 6 (1 bit)

RB_PWM11_POLAR : RW, PWM11 output polarity: 0=default low and high action, 1=default high and low action
bits : 7 - 7 (1 bit)


R8_PWM_CONFIG

RW, PWM configuration
address_offset : 0x2 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

R8_PWM_CONFIG R8_PWM_CONFIG read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 RB_PWM_CYCLE_SEL RB_PWM_STAG_ST RB_PWM_CYC_MOD RB_PWM4_5_STAG_EN RB_PWM6_7_STAG_EN RB_PWM8_9_STAG_EN RB_PWM10_11_STAG_EN

RB_PWM_CYCLE_SEL : RW, PWM cycle selection: 0=256 128 64 32 clocks, 1=255 127 63 31 clocks
bits : 0 - 0 (1 bit)

RB_PWM_STAG_ST : RO, PWM stagger cycle status
bits : 1 - 1 (1 bit)
access : read-only

RB_PWM_CYC_MOD : RW, PWM data width mode: 00=8 bits data, 01=7 bits data, 10=6 bits data, 11=5 bits data
bits : 2 - 3 (2 bit)

RB_PWM4_5_STAG_EN : RW, PWM4/5 stagger output enable: 0=independent output, 1=stagger output
bits : 4 - 4 (1 bit)

RB_PWM6_7_STAG_EN : RW, PWM6/7 stagger output enable: 0=independent output, 1=stagger output
bits : 5 - 5 (1 bit)

RB_PWM8_9_STAG_EN : RW, PWM8/9 stagger output enable: 0=independent output, 1=stagger output
bits : 6 - 6 (1 bit)

RB_PWM10_11_STAG_EN : RW, PWM10/11 stagger output enable: 0=independent output, 1=stagger output
bits : 7 - 7 (1 bit)


R8_PWM_CLOCK_DIV

RW, PWM clock divisor
address_offset : 0x3 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

R8_PWM_CLOCK_DIV R8_PWM_CLOCK_DIV read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 R8_PWM_CLOCK_DIV

R8_PWM_CLOCK_DIV : RW, PWM clock divisor
bits : 0 - 7 (8 bit)


R8_PWM4_DATA

RW, PWM4 data holding
address_offset : 0x4 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

R8_PWM4_DATA R8_PWM4_DATA read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 R8_PWM4_DATA

R8_PWM4_DATA : RW, PWM4 data holding
bits : 0 - 7 (8 bit)


R8_PWM5_DATA

RW, PWM5 data holding
address_offset : 0x5 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

R8_PWM5_DATA R8_PWM5_DATA read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 R8_PWM5_DATA

R8_PWM5_DATA : RW, PWM5 data holding
bits : 0 - 7 (8 bit)


R8_PWM6_DATA

RW, PWM6 data holding
address_offset : 0x6 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

R8_PWM6_DATA R8_PWM6_DATA read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 R8_PWM6_DATA

R8_PWM6_DATA : RW, PWM6 data holding
bits : 0 - 7 (8 bit)


R8_PWM7_DATA

RW, PWM7 data holding
address_offset : 0x7 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

R8_PWM7_DATA R8_PWM7_DATA read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 R8_PWM7_DATA

R8_PWM7_DATA : RW, PWM7 data holding
bits : 0 - 7 (8 bit)


R8_PWM8_DATA

RW, PWM8 data holding
address_offset : 0x8 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

R8_PWM8_DATA R8_PWM8_DATA read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 R8_PWM8_DATA

R8_PWM8_DATA : RW, PWM8 data holding
bits : 0 - 7 (8 bit)


R8_PWM9_DATA

RW, PWM9 data holding
address_offset : 0x9 Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

R8_PWM9_DATA R8_PWM9_DATA read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 R8_PWM9_DATA

R8_PWM9_DATA : RW, PWM9 data holding
bits : 0 - 7 (8 bit)


R8_PWM10_DATA

RW, PWM10 data holding
address_offset : 0xA Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

R8_PWM10_DATA R8_PWM10_DATA read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 R8_PWM10_DATA

R8_PWM10_DATA : RW, PWM10 data holding
bits : 0 - 7 (8 bit)


R8_PWM11_DATA

RW, PWM11 data holding
address_offset : 0xB Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

R8_PWM11_DATA R8_PWM11_DATA read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 R8_PWM11_DATA

R8_PWM11_DATA : RW, PWM11 data holding
bits : 0 - 7 (8 bit)


R8_PWM_INT_CTRL

RW, PWM interrupt control
address_offset : 0xC Bytes (0x0)
size : 8 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

R8_PWM_INT_CTRL R8_PWM_INT_CTRL read-write 0 1 2 3 4 5 6 7 Resets to 0 0 0 0 0 0 0 0 RB_PWM_IE_CYC RB_PWM_CYC_PRE RB_PWM_IF_CYC

RB_PWM_IE_CYC : RW, enable interrupt for PWM cycle end
bits : 0 - 0 (1 bit)

RB_PWM_CYC_PRE : RW, select PWM cycle interrupt point
bits : 1 - 1 (1 bit)

RB_PWM_IF_CYC : RW1, interrupt flag for PWM cycle end
bits : 7 - 7 (1 bit)



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