PSM

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x10 byte (0x0)
mem_usage : registers
protection :

Registers

FRCE_ON

FRCE_OFF

WDSEL

DONE


FRCE_ON

Force block out of reset (i.e. power it on)
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FRCE_ON FRCE_ON read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PROC_COLD OTP ROSC XOSC RESETS CLOCKS PSM_READY BUSFABRIC ROM BOOTRAM SRAM0 SRAM1 SRAM2 SRAM3 SRAM4 SRAM5 SRAM6 SRAM7 SRAM8 SRAM9 XIP SIO ACCESSCTRL PROC0 PROC1

PROC_COLD :
bits : 0 - 0 (1 bit)
access : read-write

OTP :
bits : 1 - 1 (1 bit)
access : read-write

ROSC :
bits : 2 - 2 (1 bit)
access : read-write

XOSC :
bits : 3 - 3 (1 bit)
access : read-write

RESETS :
bits : 4 - 4 (1 bit)
access : read-write

CLOCKS :
bits : 5 - 5 (1 bit)
access : read-write

PSM_READY :
bits : 6 - 6 (1 bit)
access : read-write

BUSFABRIC :
bits : 7 - 7 (1 bit)
access : read-write

ROM :
bits : 8 - 8 (1 bit)
access : read-write

BOOTRAM :
bits : 9 - 9 (1 bit)
access : read-write

SRAM0 :
bits : 10 - 10 (1 bit)
access : read-write

SRAM1 :
bits : 11 - 11 (1 bit)
access : read-write

SRAM2 :
bits : 12 - 12 (1 bit)
access : read-write

SRAM3 :
bits : 13 - 13 (1 bit)
access : read-write

SRAM4 :
bits : 14 - 14 (1 bit)
access : read-write

SRAM5 :
bits : 15 - 15 (1 bit)
access : read-write

SRAM6 :
bits : 16 - 16 (1 bit)
access : read-write

SRAM7 :
bits : 17 - 17 (1 bit)
access : read-write

SRAM8 :
bits : 18 - 18 (1 bit)
access : read-write

SRAM9 :
bits : 19 - 19 (1 bit)
access : read-write

XIP :
bits : 20 - 20 (1 bit)
access : read-write

SIO :
bits : 21 - 21 (1 bit)
access : read-write

ACCESSCTRL :
bits : 22 - 22 (1 bit)
access : read-write

PROC0 :
bits : 23 - 23 (1 bit)
access : read-write

PROC1 :
bits : 24 - 24 (1 bit)
access : read-write


FRCE_OFF

Force into reset (i.e. power it off)
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FRCE_OFF FRCE_OFF read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PROC_COLD OTP ROSC XOSC RESETS CLOCKS PSM_READY BUSFABRIC ROM BOOTRAM SRAM0 SRAM1 SRAM2 SRAM3 SRAM4 SRAM5 SRAM6 SRAM7 SRAM8 SRAM9 XIP SIO ACCESSCTRL PROC0 PROC1

PROC_COLD :
bits : 0 - 0 (1 bit)
access : read-write

OTP :
bits : 1 - 1 (1 bit)
access : read-write

ROSC :
bits : 2 - 2 (1 bit)
access : read-write

XOSC :
bits : 3 - 3 (1 bit)
access : read-write

RESETS :
bits : 4 - 4 (1 bit)
access : read-write

CLOCKS :
bits : 5 - 5 (1 bit)
access : read-write

PSM_READY :
bits : 6 - 6 (1 bit)
access : read-write

BUSFABRIC :
bits : 7 - 7 (1 bit)
access : read-write

ROM :
bits : 8 - 8 (1 bit)
access : read-write

BOOTRAM :
bits : 9 - 9 (1 bit)
access : read-write

SRAM0 :
bits : 10 - 10 (1 bit)
access : read-write

SRAM1 :
bits : 11 - 11 (1 bit)
access : read-write

SRAM2 :
bits : 12 - 12 (1 bit)
access : read-write

SRAM3 :
bits : 13 - 13 (1 bit)
access : read-write

SRAM4 :
bits : 14 - 14 (1 bit)
access : read-write

SRAM5 :
bits : 15 - 15 (1 bit)
access : read-write

SRAM6 :
bits : 16 - 16 (1 bit)
access : read-write

SRAM7 :
bits : 17 - 17 (1 bit)
access : read-write

SRAM8 :
bits : 18 - 18 (1 bit)
access : read-write

SRAM9 :
bits : 19 - 19 (1 bit)
access : read-write

XIP :
bits : 20 - 20 (1 bit)
access : read-write

SIO :
bits : 21 - 21 (1 bit)
access : read-write

ACCESSCTRL :
bits : 22 - 22 (1 bit)
access : read-write

PROC0 :
bits : 23 - 23 (1 bit)
access : read-write

PROC1 :
bits : 24 - 24 (1 bit)
access : read-write


WDSEL

Set to 1 if the watchdog should reset this
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

WDSEL WDSEL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PROC_COLD OTP ROSC XOSC RESETS CLOCKS PSM_READY BUSFABRIC ROM BOOTRAM SRAM0 SRAM1 SRAM2 SRAM3 SRAM4 SRAM5 SRAM6 SRAM7 SRAM8 SRAM9 XIP SIO ACCESSCTRL PROC0 PROC1

PROC_COLD :
bits : 0 - 0 (1 bit)
access : read-write

OTP :
bits : 1 - 1 (1 bit)
access : read-write

ROSC :
bits : 2 - 2 (1 bit)
access : read-write

XOSC :
bits : 3 - 3 (1 bit)
access : read-write

RESETS :
bits : 4 - 4 (1 bit)
access : read-write

CLOCKS :
bits : 5 - 5 (1 bit)
access : read-write

PSM_READY :
bits : 6 - 6 (1 bit)
access : read-write

BUSFABRIC :
bits : 7 - 7 (1 bit)
access : read-write

ROM :
bits : 8 - 8 (1 bit)
access : read-write

BOOTRAM :
bits : 9 - 9 (1 bit)
access : read-write

SRAM0 :
bits : 10 - 10 (1 bit)
access : read-write

SRAM1 :
bits : 11 - 11 (1 bit)
access : read-write

SRAM2 :
bits : 12 - 12 (1 bit)
access : read-write

SRAM3 :
bits : 13 - 13 (1 bit)
access : read-write

SRAM4 :
bits : 14 - 14 (1 bit)
access : read-write

SRAM5 :
bits : 15 - 15 (1 bit)
access : read-write

SRAM6 :
bits : 16 - 16 (1 bit)
access : read-write

SRAM7 :
bits : 17 - 17 (1 bit)
access : read-write

SRAM8 :
bits : 18 - 18 (1 bit)
access : read-write

SRAM9 :
bits : 19 - 19 (1 bit)
access : read-write

XIP :
bits : 20 - 20 (1 bit)
access : read-write

SIO :
bits : 21 - 21 (1 bit)
access : read-write

ACCESSCTRL :
bits : 22 - 22 (1 bit)
access : read-write

PROC0 :
bits : 23 - 23 (1 bit)
access : read-write

PROC1 :
bits : 24 - 24 (1 bit)
access : read-write


DONE

Is the subsystem ready?
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DONE DONE read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PROC_COLD OTP ROSC XOSC RESETS CLOCKS PSM_READY BUSFABRIC ROM BOOTRAM SRAM0 SRAM1 SRAM2 SRAM3 SRAM4 SRAM5 SRAM6 SRAM7 SRAM8 SRAM9 XIP SIO ACCESSCTRL PROC0 PROC1

PROC_COLD :
bits : 0 - 0 (1 bit)
access : read-only

OTP :
bits : 1 - 1 (1 bit)
access : read-only

ROSC :
bits : 2 - 2 (1 bit)
access : read-only

XOSC :
bits : 3 - 3 (1 bit)
access : read-only

RESETS :
bits : 4 - 4 (1 bit)
access : read-only

CLOCKS :
bits : 5 - 5 (1 bit)
access : read-only

PSM_READY :
bits : 6 - 6 (1 bit)
access : read-only

BUSFABRIC :
bits : 7 - 7 (1 bit)
access : read-only

ROM :
bits : 8 - 8 (1 bit)
access : read-only

BOOTRAM :
bits : 9 - 9 (1 bit)
access : read-only

SRAM0 :
bits : 10 - 10 (1 bit)
access : read-only

SRAM1 :
bits : 11 - 11 (1 bit)
access : read-only

SRAM2 :
bits : 12 - 12 (1 bit)
access : read-only

SRAM3 :
bits : 13 - 13 (1 bit)
access : read-only

SRAM4 :
bits : 14 - 14 (1 bit)
access : read-only

SRAM5 :
bits : 15 - 15 (1 bit)
access : read-only

SRAM6 :
bits : 16 - 16 (1 bit)
access : read-only

SRAM7 :
bits : 17 - 17 (1 bit)
access : read-only

SRAM8 :
bits : 18 - 18 (1 bit)
access : read-only

SRAM9 :
bits : 19 - 19 (1 bit)
access : read-only

XIP :
bits : 20 - 20 (1 bit)
access : read-only

SIO :
bits : 21 - 21 (1 bit)
access : read-only

ACCESSCTRL :
bits : 22 - 22 (1 bit)
access : read-only

PROC0 :
bits : 23 - 23 (1 bit)
access : read-only

PROC1 :
bits : 24 - 24 (1 bit)
access : read-only



Is something missing? Is something wrong? can you help correct it ? Please contact us at info@chipselect.org !

This website is sponsored by EmbeetleEmbeetle, an IDE designed from scratch for embedded software developers.