CLOCKS

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0xD4 byte (0x0)
mem_usage : registers
protection :

Registers

CLK_GPOUT0_CTRL

CLK_GPOUT1_DIV

CLK_GPOUT1_SELECTED

CLK_GPOUT2_CTRL

CLK_GPOUT2_DIV

CLK_GPOUT2_SELECTED

CLK_GPOUT3_CTRL

CLK_GPOUT3_DIV

CLK_GPOUT3_SELECTED

CLK_REF_CTRL

CLK_REF_DIV

CLK_REF_SELECTED

CLK_SYS_CTRL

CLK_GPOUT0_DIV

CLK_SYS_DIV

CLK_SYS_SELECTED

CLK_PERI_CTRL

CLK_PERI_DIV

CLK_PERI_SELECTED

CLK_HSTX_CTRL

CLK_HSTX_DIV

CLK_HSTX_SELECTED

CLK_USB_CTRL

CLK_USB_DIV

CLK_USB_SELECTED

CLK_ADC_CTRL

CLK_ADC_DIV

CLK_ADC_SELECTED

DFTCLK_XOSC_CTRL

DFTCLK_ROSC_CTRL

CLK_GPOUT0_SELECTED

DFTCLK_LPOSC_CTRL

CLK_SYS_RESUS_CTRL

CLK_SYS_RESUS_STATUS

FC0_REF_KHZ

FC0_MIN_KHZ

FC0_MAX_KHZ

FC0_DELAY

FC0_INTERVAL

FC0_SRC

FC0_STATUS

FC0_RESULT

WAKE_EN0

WAKE_EN1

SLEEP_EN0

SLEEP_EN1

ENABLED0

CLK_GPOUT1_CTRL

ENABLED1

INTR

INTE

INTF

INTS


CLK_GPOUT0_CTRL

Clock control, can be changed on-the-fly (except for auxsrc)
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CLK_GPOUT0_CTRL CLK_GPOUT0_CTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AUXSRC KILL ENABLE DC50 PHASE NUDGE ENABLED

AUXSRC : Selects the auxiliary clock source, will glitch when switching
bits : 5 - 8 (4 bit)
access : read-write

Enumeration:

0 : clksrc_pll_sys


1 : clksrc_gpin0


2 : clksrc_gpin1


3 : clksrc_pll_usb


4 : clksrc_pll_usb_primary_ref_opcg


5 : rosc_clksrc


6 : xosc_clksrc


7 : lposc_clksrc


8 : clk_sys


9 : clk_usb


10 : clk_adc


11 : clk_ref


12 : clk_peri


13 : clk_hstx


14 : otp_clk2fc


End of enumeration elements list.

KILL : Asynchronously kills the clock generator, enable must be set low before deasserting kill
bits : 10 - 10 (1 bit)
access : read-write

ENABLE : Starts and stops the clock generator cleanly
bits : 11 - 11 (1 bit)
access : read-write

DC50 : Enables duty cycle correction for odd divisors, can be changed on-the-fly
bits : 12 - 12 (1 bit)
access : read-write

PHASE : This delays the enable signal by up to 3 cycles of the input clock This must be set before the clock is enabled to have any effect
bits : 16 - 17 (2 bit)
access : read-write

NUDGE : An edge on this signal shifts the phase of the output by 1 cycle of the input clock This can be done at any time
bits : 20 - 20 (1 bit)
access : read-write

ENABLED : clock generator is enabled
bits : 28 - 28 (1 bit)
access : read-only


CLK_GPOUT1_DIV


address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CLK_GPOUT1_DIV CLK_GPOUT1_DIV read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FRAC INT

FRAC : Fractional component of the divisor, can be changed on-the-fly
bits : 0 - 15 (16 bit)
access : read-write

INT : Integer part of clock divisor, 0 -> max+1, can be changed on-the-fly
bits : 16 - 31 (16 bit)
access : read-write


CLK_GPOUT1_SELECTED

Indicates which src is currently selected (one-hot)
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CLK_GPOUT1_SELECTED CLK_GPOUT1_SELECTED read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CLK_GPOUT1_SELECTED

CLK_GPOUT1_SELECTED : This slice does not have a glitchless mux (only the AUX_SRC field is present, not SRC) so this register is hardwired to 0x1.
bits : 0 - 0 (1 bit)
access : read-only


CLK_GPOUT2_CTRL

Clock control, can be changed on-the-fly (except for auxsrc)
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CLK_GPOUT2_CTRL CLK_GPOUT2_CTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AUXSRC KILL ENABLE DC50 PHASE NUDGE ENABLED

AUXSRC : Selects the auxiliary clock source, will glitch when switching
bits : 5 - 8 (4 bit)
access : read-write

Enumeration:

0 : clksrc_pll_sys


1 : clksrc_gpin0


2 : clksrc_gpin1


3 : clksrc_pll_usb


4 : clksrc_pll_usb_primary_ref_opcg


5 : rosc_clksrc_ph


6 : xosc_clksrc


7 : lposc_clksrc


8 : clk_sys


9 : clk_usb


10 : clk_adc


11 : clk_ref


12 : clk_peri


13 : clk_hstx


14 : otp_clk2fc


End of enumeration elements list.

KILL : Asynchronously kills the clock generator, enable must be set low before deasserting kill
bits : 10 - 10 (1 bit)
access : read-write

ENABLE : Starts and stops the clock generator cleanly
bits : 11 - 11 (1 bit)
access : read-write

DC50 : Enables duty cycle correction for odd divisors, can be changed on-the-fly
bits : 12 - 12 (1 bit)
access : read-write

PHASE : This delays the enable signal by up to 3 cycles of the input clock This must be set before the clock is enabled to have any effect
bits : 16 - 17 (2 bit)
access : read-write

NUDGE : An edge on this signal shifts the phase of the output by 1 cycle of the input clock This can be done at any time
bits : 20 - 20 (1 bit)
access : read-write

ENABLED : clock generator is enabled
bits : 28 - 28 (1 bit)
access : read-only


CLK_GPOUT2_DIV


address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CLK_GPOUT2_DIV CLK_GPOUT2_DIV read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FRAC INT

FRAC : Fractional component of the divisor, can be changed on-the-fly
bits : 0 - 15 (16 bit)
access : read-write

INT : Integer part of clock divisor, 0 -> max+1, can be changed on-the-fly
bits : 16 - 31 (16 bit)
access : read-write


CLK_GPOUT2_SELECTED

Indicates which src is currently selected (one-hot)
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CLK_GPOUT2_SELECTED CLK_GPOUT2_SELECTED read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CLK_GPOUT2_SELECTED

CLK_GPOUT2_SELECTED : This slice does not have a glitchless mux (only the AUX_SRC field is present, not SRC) so this register is hardwired to 0x1.
bits : 0 - 0 (1 bit)
access : read-only


CLK_GPOUT3_CTRL

Clock control, can be changed on-the-fly (except for auxsrc)
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CLK_GPOUT3_CTRL CLK_GPOUT3_CTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AUXSRC KILL ENABLE DC50 PHASE NUDGE ENABLED

AUXSRC : Selects the auxiliary clock source, will glitch when switching
bits : 5 - 8 (4 bit)
access : read-write

Enumeration:

0 : clksrc_pll_sys


1 : clksrc_gpin0


2 : clksrc_gpin1


3 : clksrc_pll_usb


4 : clksrc_pll_usb_primary_ref_opcg


5 : rosc_clksrc_ph


6 : xosc_clksrc


7 : lposc_clksrc


8 : clk_sys


9 : clk_usb


10 : clk_adc


11 : clk_ref


12 : clk_peri


13 : clk_hstx


14 : otp_clk2fc


End of enumeration elements list.

KILL : Asynchronously kills the clock generator, enable must be set low before deasserting kill
bits : 10 - 10 (1 bit)
access : read-write

ENABLE : Starts and stops the clock generator cleanly
bits : 11 - 11 (1 bit)
access : read-write

DC50 : Enables duty cycle correction for odd divisors, can be changed on-the-fly
bits : 12 - 12 (1 bit)
access : read-write

PHASE : This delays the enable signal by up to 3 cycles of the input clock This must be set before the clock is enabled to have any effect
bits : 16 - 17 (2 bit)
access : read-write

NUDGE : An edge on this signal shifts the phase of the output by 1 cycle of the input clock This can be done at any time
bits : 20 - 20 (1 bit)
access : read-write

ENABLED : clock generator is enabled
bits : 28 - 28 (1 bit)
access : read-only


CLK_GPOUT3_DIV


address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CLK_GPOUT3_DIV CLK_GPOUT3_DIV read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FRAC INT

FRAC : Fractional component of the divisor, can be changed on-the-fly
bits : 0 - 15 (16 bit)
access : read-write

INT : Integer part of clock divisor, 0 -> max+1, can be changed on-the-fly
bits : 16 - 31 (16 bit)
access : read-write


CLK_GPOUT3_SELECTED

Indicates which src is currently selected (one-hot)
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CLK_GPOUT3_SELECTED CLK_GPOUT3_SELECTED read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CLK_GPOUT3_SELECTED

CLK_GPOUT3_SELECTED : This slice does not have a glitchless mux (only the AUX_SRC field is present, not SRC) so this register is hardwired to 0x1.
bits : 0 - 0 (1 bit)
access : read-only


CLK_REF_CTRL

Clock control, can be changed on-the-fly (except for auxsrc)
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CLK_REF_CTRL CLK_REF_CTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SRC AUXSRC

SRC : Selects the clock source glitchlessly, can be changed on-the-fly
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : rosc_clksrc_ph


1 : clksrc_clk_ref_aux


2 : xosc_clksrc


3 : lposc_clksrc


End of enumeration elements list.

AUXSRC : Selects the auxiliary clock source, will glitch when switching
bits : 5 - 6 (2 bit)
access : read-write

Enumeration:

0 : clksrc_pll_usb


1 : clksrc_gpin0


2 : clksrc_gpin1


3 : clksrc_pll_usb_primary_ref_opcg


End of enumeration elements list.


CLK_REF_DIV


address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CLK_REF_DIV CLK_REF_DIV read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INT

INT : Integer part of clock divisor, 0 -> max+1, can be changed on-the-fly
bits : 16 - 23 (8 bit)
access : read-write


CLK_REF_SELECTED

Indicates which src is currently selected (one-hot)
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CLK_REF_SELECTED CLK_REF_SELECTED read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CLK_REF_SELECTED

CLK_REF_SELECTED : The glitchless multiplexer does not switch instantaneously (to avoid glitches), so software should poll this register to wait for the switch to complete. This register contains one decoded bit for each of the clock sources enumerated in the CTRL SRC field. At most one of these bits will be set at any time, indicating that clock is currently present at the output of the glitchless mux. Whilst switching is in progress, this register may briefly show all-0s.
bits : 0 - 3 (4 bit)
access : read-only


CLK_SYS_CTRL

Clock control, can be changed on-the-fly (except for auxsrc)
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CLK_SYS_CTRL CLK_SYS_CTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SRC AUXSRC

SRC : Selects the clock source glitchlessly, can be changed on-the-fly
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0 : clk_ref


1 : clksrc_clk_sys_aux


End of enumeration elements list.

AUXSRC : Selects the auxiliary clock source, will glitch when switching
bits : 5 - 7 (3 bit)
access : read-write

Enumeration:

0 : clksrc_pll_sys


1 : clksrc_pll_usb


2 : rosc_clksrc


3 : xosc_clksrc


4 : clksrc_gpin0


5 : clksrc_gpin1


End of enumeration elements list.


CLK_GPOUT0_DIV


address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CLK_GPOUT0_DIV CLK_GPOUT0_DIV read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FRAC INT

FRAC : Fractional component of the divisor, can be changed on-the-fly
bits : 0 - 15 (16 bit)
access : read-write

INT : Integer part of clock divisor, 0 -> max+1, can be changed on-the-fly
bits : 16 - 31 (16 bit)
access : read-write


CLK_SYS_DIV


address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CLK_SYS_DIV CLK_SYS_DIV read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FRAC INT

FRAC : Fractional component of the divisor, can be changed on-the-fly
bits : 0 - 15 (16 bit)
access : read-write

INT : Integer part of clock divisor, 0 -> max+1, can be changed on-the-fly
bits : 16 - 31 (16 bit)
access : read-write


CLK_SYS_SELECTED

Indicates which src is currently selected (one-hot)
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CLK_SYS_SELECTED CLK_SYS_SELECTED read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CLK_SYS_SELECTED

CLK_SYS_SELECTED : The glitchless multiplexer does not switch instantaneously (to avoid glitches), so software should poll this register to wait for the switch to complete. This register contains one decoded bit for each of the clock sources enumerated in the CTRL SRC field. At most one of these bits will be set at any time, indicating that clock is currently present at the output of the glitchless mux. Whilst switching is in progress, this register may briefly show all-0s.
bits : 0 - 1 (2 bit)
access : read-only


CLK_PERI_CTRL

Clock control, can be changed on-the-fly (except for auxsrc)
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CLK_PERI_CTRL CLK_PERI_CTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AUXSRC KILL ENABLE ENABLED

AUXSRC : Selects the auxiliary clock source, will glitch when switching
bits : 5 - 7 (3 bit)
access : read-write

Enumeration:

0 : clk_sys


1 : clksrc_pll_sys


2 : clksrc_pll_usb


3 : rosc_clksrc_ph


4 : xosc_clksrc


5 : clksrc_gpin0


6 : clksrc_gpin1


End of enumeration elements list.

KILL : Asynchronously kills the clock generator, enable must be set low before deasserting kill
bits : 10 - 10 (1 bit)
access : read-write

ENABLE : Starts and stops the clock generator cleanly
bits : 11 - 11 (1 bit)
access : read-write

ENABLED : clock generator is enabled
bits : 28 - 28 (1 bit)
access : read-only


CLK_PERI_DIV


address_offset : 0x4C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CLK_PERI_DIV CLK_PERI_DIV read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INT

INT : Integer part of clock divisor, 0 -> max+1, can be changed on-the-fly
bits : 16 - 17 (2 bit)
access : read-write


CLK_PERI_SELECTED

Indicates which src is currently selected (one-hot)
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CLK_PERI_SELECTED CLK_PERI_SELECTED read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CLK_PERI_SELECTED

CLK_PERI_SELECTED : This slice does not have a glitchless mux (only the AUX_SRC field is present, not SRC) so this register is hardwired to 0x1.
bits : 0 - 0 (1 bit)
access : read-only


CLK_HSTX_CTRL

Clock control, can be changed on-the-fly (except for auxsrc)
address_offset : 0x54 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CLK_HSTX_CTRL CLK_HSTX_CTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AUXSRC KILL ENABLE PHASE NUDGE ENABLED

AUXSRC : Selects the auxiliary clock source, will glitch when switching
bits : 5 - 7 (3 bit)
access : read-write

Enumeration:

0 : clk_sys


1 : clksrc_pll_sys


2 : clksrc_pll_usb


3 : clksrc_gpin0


4 : clksrc_gpin1


End of enumeration elements list.

KILL : Asynchronously kills the clock generator, enable must be set low before deasserting kill
bits : 10 - 10 (1 bit)
access : read-write

ENABLE : Starts and stops the clock generator cleanly
bits : 11 - 11 (1 bit)
access : read-write

PHASE : This delays the enable signal by up to 3 cycles of the input clock This must be set before the clock is enabled to have any effect
bits : 16 - 17 (2 bit)
access : read-write

NUDGE : An edge on this signal shifts the phase of the output by 1 cycle of the input clock This can be done at any time
bits : 20 - 20 (1 bit)
access : read-write

ENABLED : clock generator is enabled
bits : 28 - 28 (1 bit)
access : read-only


CLK_HSTX_DIV


address_offset : 0x58 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CLK_HSTX_DIV CLK_HSTX_DIV read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INT

INT : Integer part of clock divisor, 0 -> max+1, can be changed on-the-fly
bits : 16 - 17 (2 bit)
access : read-write


CLK_HSTX_SELECTED

Indicates which src is currently selected (one-hot)
address_offset : 0x5C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CLK_HSTX_SELECTED CLK_HSTX_SELECTED read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CLK_HSTX_SELECTED

CLK_HSTX_SELECTED : This slice does not have a glitchless mux (only the AUX_SRC field is present, not SRC) so this register is hardwired to 0x1.
bits : 0 - 0 (1 bit)
access : read-only


CLK_USB_CTRL

Clock control, can be changed on-the-fly (except for auxsrc)
address_offset : 0x60 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CLK_USB_CTRL CLK_USB_CTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AUXSRC KILL ENABLE PHASE NUDGE ENABLED

AUXSRC : Selects the auxiliary clock source, will glitch when switching
bits : 5 - 7 (3 bit)
access : read-write

Enumeration:

0 : clksrc_pll_usb


1 : clksrc_pll_sys


2 : rosc_clksrc_ph


3 : xosc_clksrc


4 : clksrc_gpin0


5 : clksrc_gpin1


End of enumeration elements list.

KILL : Asynchronously kills the clock generator, enable must be set low before deasserting kill
bits : 10 - 10 (1 bit)
access : read-write

ENABLE : Starts and stops the clock generator cleanly
bits : 11 - 11 (1 bit)
access : read-write

PHASE : This delays the enable signal by up to 3 cycles of the input clock This must be set before the clock is enabled to have any effect
bits : 16 - 17 (2 bit)
access : read-write

NUDGE : An edge on this signal shifts the phase of the output by 1 cycle of the input clock This can be done at any time
bits : 20 - 20 (1 bit)
access : read-write

ENABLED : clock generator is enabled
bits : 28 - 28 (1 bit)
access : read-only


CLK_USB_DIV


address_offset : 0x64 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CLK_USB_DIV CLK_USB_DIV read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INT

INT : Integer part of clock divisor, 0 -> max+1, can be changed on-the-fly
bits : 16 - 19 (4 bit)
access : read-write


CLK_USB_SELECTED

Indicates which src is currently selected (one-hot)
address_offset : 0x68 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CLK_USB_SELECTED CLK_USB_SELECTED read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CLK_USB_SELECTED

CLK_USB_SELECTED : This slice does not have a glitchless mux (only the AUX_SRC field is present, not SRC) so this register is hardwired to 0x1.
bits : 0 - 0 (1 bit)
access : read-only


CLK_ADC_CTRL

Clock control, can be changed on-the-fly (except for auxsrc)
address_offset : 0x6C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CLK_ADC_CTRL CLK_ADC_CTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AUXSRC KILL ENABLE PHASE NUDGE ENABLED

AUXSRC : Selects the auxiliary clock source, will glitch when switching
bits : 5 - 7 (3 bit)
access : read-write

Enumeration:

0 : clksrc_pll_usb


1 : clksrc_pll_sys


2 : rosc_clksrc_ph


3 : xosc_clksrc


4 : clksrc_gpin0


5 : clksrc_gpin1


End of enumeration elements list.

KILL : Asynchronously kills the clock generator, enable must be set low before deasserting kill
bits : 10 - 10 (1 bit)
access : read-write

ENABLE : Starts and stops the clock generator cleanly
bits : 11 - 11 (1 bit)
access : read-write

PHASE : This delays the enable signal by up to 3 cycles of the input clock This must be set before the clock is enabled to have any effect
bits : 16 - 17 (2 bit)
access : read-write

NUDGE : An edge on this signal shifts the phase of the output by 1 cycle of the input clock This can be done at any time
bits : 20 - 20 (1 bit)
access : read-write

ENABLED : clock generator is enabled
bits : 28 - 28 (1 bit)
access : read-only


CLK_ADC_DIV


address_offset : 0x70 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CLK_ADC_DIV CLK_ADC_DIV read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INT

INT : Integer part of clock divisor, 0 -> max+1, can be changed on-the-fly
bits : 16 - 19 (4 bit)
access : read-write


CLK_ADC_SELECTED

Indicates which src is currently selected (one-hot)
address_offset : 0x74 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CLK_ADC_SELECTED CLK_ADC_SELECTED read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CLK_ADC_SELECTED

CLK_ADC_SELECTED : This slice does not have a glitchless mux (only the AUX_SRC field is present, not SRC) so this register is hardwired to 0x1.
bits : 0 - 0 (1 bit)
access : read-only


DFTCLK_XOSC_CTRL


address_offset : 0x78 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DFTCLK_XOSC_CTRL DFTCLK_XOSC_CTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SRC

SRC :
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : NULL


1 : clksrc_pll_usb_primary


2 : clksrc_gpin0


End of enumeration elements list.


DFTCLK_ROSC_CTRL


address_offset : 0x7C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DFTCLK_ROSC_CTRL DFTCLK_ROSC_CTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SRC

SRC :
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : NULL


1 : clksrc_pll_sys_primary_rosc


2 : clksrc_gpin1


End of enumeration elements list.


CLK_GPOUT0_SELECTED

Indicates which src is currently selected (one-hot)
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CLK_GPOUT0_SELECTED CLK_GPOUT0_SELECTED read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CLK_GPOUT0_SELECTED

CLK_GPOUT0_SELECTED : This slice does not have a glitchless mux (only the AUX_SRC field is present, not SRC) so this register is hardwired to 0x1.
bits : 0 - 0 (1 bit)
access : read-only


DFTCLK_LPOSC_CTRL


address_offset : 0x80 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DFTCLK_LPOSC_CTRL DFTCLK_LPOSC_CTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SRC

SRC :
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0 : NULL


1 : clksrc_pll_usb_primary_lposc


2 : clksrc_gpin1


End of enumeration elements list.


CLK_SYS_RESUS_CTRL


address_offset : 0x84 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CLK_SYS_RESUS_CTRL CLK_SYS_RESUS_CTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TIMEOUT ENABLE FRCE CLEAR

TIMEOUT : This is expressed as a number of clk_ref cycles and must be >= 2x clk_ref_freq/min_clk_tst_freq
bits : 0 - 7 (8 bit)
access : read-write

ENABLE : Enable resus
bits : 8 - 8 (1 bit)
access : read-write

FRCE : Force a resus, for test purposes only
bits : 12 - 12 (1 bit)
access : read-write

CLEAR : For clearing the resus after the fault that triggered it has been corrected
bits : 16 - 16 (1 bit)
access : read-write


CLK_SYS_RESUS_STATUS


address_offset : 0x88 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CLK_SYS_RESUS_STATUS CLK_SYS_RESUS_STATUS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RESUSSED

RESUSSED : Clock has been resuscitated, correct the error then send ctrl_clear=1
bits : 0 - 0 (1 bit)
access : read-only


FC0_REF_KHZ

Reference clock frequency in kHz
address_offset : 0x8C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FC0_REF_KHZ FC0_REF_KHZ read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FC0_REF_KHZ

FC0_REF_KHZ :
bits : 0 - 19 (20 bit)
access : read-write


FC0_MIN_KHZ

Minimum pass frequency in kHz. This is optional. Set to 0 if you are not using the pass/fail flags
address_offset : 0x90 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FC0_MIN_KHZ FC0_MIN_KHZ read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FC0_MIN_KHZ

FC0_MIN_KHZ :
bits : 0 - 24 (25 bit)
access : read-write


FC0_MAX_KHZ

Maximum pass frequency in kHz. This is optional. Set to 0x1ffffff if you are not using the pass/fail flags
address_offset : 0x94 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FC0_MAX_KHZ FC0_MAX_KHZ read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FC0_MAX_KHZ

FC0_MAX_KHZ :
bits : 0 - 24 (25 bit)
access : read-write


FC0_DELAY

Delays the start of frequency counting to allow the mux to settle Delay is measured in multiples of the reference clock period
address_offset : 0x98 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FC0_DELAY FC0_DELAY read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FC0_DELAY

FC0_DELAY :
bits : 0 - 2 (3 bit)
access : read-write


FC0_INTERVAL

The test interval is 0.98us * 2**interval, but let's call it 1us * 2**interval The default gives a test interval of 250us
address_offset : 0x9C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FC0_INTERVAL FC0_INTERVAL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FC0_INTERVAL

FC0_INTERVAL :
bits : 0 - 3 (4 bit)
access : read-write


FC0_SRC

Clock sent to frequency counter, set to 0 when not required Writing to this register initiates the frequency count
address_offset : 0xA0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FC0_SRC FC0_SRC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FC0_SRC

FC0_SRC :
bits : 0 - 7 (8 bit)
access : read-write

Enumeration:

0 : NULL


1 : pll_sys_clksrc_primary


2 : pll_usb_clksrc_primary


3 : rosc_clksrc


4 : rosc_clksrc_ph


5 : xosc_clksrc


6 : clksrc_gpin0


7 : clksrc_gpin1


8 : clk_ref


9 : clk_sys


10 : clk_peri


11 : clk_usb


12 : clk_adc


13 : clk_hstx


14 : lposc_clksrc


15 : otp_clk2fc


16 : pll_usb_clksrc_primary_dft


End of enumeration elements list.


FC0_STATUS

Frequency counter status
address_offset : 0xA4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FC0_STATUS FC0_STATUS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PASS DONE RUNNING WAITING FAIL SLOW FAST DIED

PASS : Test passed
bits : 0 - 0 (1 bit)
access : read-only

DONE : Test complete
bits : 4 - 4 (1 bit)
access : read-only

RUNNING : Test running
bits : 8 - 8 (1 bit)
access : read-only

WAITING : Waiting for test clock to start
bits : 12 - 12 (1 bit)
access : read-only

FAIL : Test failed
bits : 16 - 16 (1 bit)
access : read-only

SLOW : Test clock slower than expected, only valid when status_done=1
bits : 20 - 20 (1 bit)
access : read-only

FAST : Test clock faster than expected, only valid when status_done=1
bits : 24 - 24 (1 bit)
access : read-only

DIED : Test clock stopped during test
bits : 28 - 28 (1 bit)
access : read-only


FC0_RESULT

Result of frequency measurement, only valid when status_done=1
address_offset : 0xA8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FC0_RESULT FC0_RESULT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FRAC KHZ

FRAC :
bits : 0 - 4 (5 bit)
access : read-only

KHZ :
bits : 5 - 29 (25 bit)
access : read-only


WAKE_EN0

enable clock in wake mode
address_offset : 0xAC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

WAKE_EN0 WAKE_EN0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CLK_SYS_CLOCKS CLK_SYS_ACCESSCTRL CLK_ADC CLK_SYS_ADC CLK_SYS_BOOTRAM CLK_SYS_BUSCTRL CLK_SYS_BUSFABRIC CLK_SYS_DMA CLK_SYS_GLITCH_DETECTOR CLK_HSTX CLK_SYS_HSTX CLK_SYS_I2C0 CLK_SYS_I2C1 CLK_SYS_IO CLK_SYS_JTAG CLK_REF_OTP CLK_SYS_OTP CLK_SYS_PADS CLK_SYS_PIO0 CLK_SYS_PIO1 CLK_SYS_PIO2 CLK_SYS_PLL_SYS CLK_SYS_PLL_USB CLK_REF_POWMAN CLK_SYS_POWMAN CLK_SYS_PWM CLK_SYS_RESETS CLK_SYS_ROM CLK_SYS_ROSC CLK_SYS_PSM CLK_SYS_SHA256 CLK_SYS_SIO

CLK_SYS_CLOCKS :
bits : 0 - 0 (1 bit)
access : read-write

CLK_SYS_ACCESSCTRL :
bits : 1 - 1 (1 bit)
access : read-write

CLK_ADC :
bits : 2 - 2 (1 bit)
access : read-write

CLK_SYS_ADC :
bits : 3 - 3 (1 bit)
access : read-write

CLK_SYS_BOOTRAM :
bits : 4 - 4 (1 bit)
access : read-write

CLK_SYS_BUSCTRL :
bits : 5 - 5 (1 bit)
access : read-write

CLK_SYS_BUSFABRIC :
bits : 6 - 6 (1 bit)
access : read-write

CLK_SYS_DMA :
bits : 7 - 7 (1 bit)
access : read-write

CLK_SYS_GLITCH_DETECTOR :
bits : 8 - 8 (1 bit)
access : read-write

CLK_HSTX :
bits : 9 - 9 (1 bit)
access : read-write

CLK_SYS_HSTX :
bits : 10 - 10 (1 bit)
access : read-write

CLK_SYS_I2C0 :
bits : 11 - 11 (1 bit)
access : read-write

CLK_SYS_I2C1 :
bits : 12 - 12 (1 bit)
access : read-write

CLK_SYS_IO :
bits : 13 - 13 (1 bit)
access : read-write

CLK_SYS_JTAG :
bits : 14 - 14 (1 bit)
access : read-write

CLK_REF_OTP :
bits : 15 - 15 (1 bit)
access : read-write

CLK_SYS_OTP :
bits : 16 - 16 (1 bit)
access : read-write

CLK_SYS_PADS :
bits : 17 - 17 (1 bit)
access : read-write

CLK_SYS_PIO0 :
bits : 18 - 18 (1 bit)
access : read-write

CLK_SYS_PIO1 :
bits : 19 - 19 (1 bit)
access : read-write

CLK_SYS_PIO2 :
bits : 20 - 20 (1 bit)
access : read-write

CLK_SYS_PLL_SYS :
bits : 21 - 21 (1 bit)
access : read-write

CLK_SYS_PLL_USB :
bits : 22 - 22 (1 bit)
access : read-write

CLK_REF_POWMAN :
bits : 23 - 23 (1 bit)
access : read-write

CLK_SYS_POWMAN :
bits : 24 - 24 (1 bit)
access : read-write

CLK_SYS_PWM :
bits : 25 - 25 (1 bit)
access : read-write

CLK_SYS_RESETS :
bits : 26 - 26 (1 bit)
access : read-write

CLK_SYS_ROM :
bits : 27 - 27 (1 bit)
access : read-write

CLK_SYS_ROSC :
bits : 28 - 28 (1 bit)
access : read-write

CLK_SYS_PSM :
bits : 29 - 29 (1 bit)
access : read-write

CLK_SYS_SHA256 :
bits : 30 - 30 (1 bit)
access : read-write

CLK_SYS_SIO :
bits : 31 - 31 (1 bit)
access : read-write


WAKE_EN1

enable clock in wake mode
address_offset : 0xB0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

WAKE_EN1 WAKE_EN1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CLK_PERI_SPI0 CLK_SYS_SPI0 CLK_PERI_SPI1 CLK_SYS_SPI1 CLK_SYS_SRAM0 CLK_SYS_SRAM1 CLK_SYS_SRAM2 CLK_SYS_SRAM3 CLK_SYS_SRAM4 CLK_SYS_SRAM5 CLK_SYS_SRAM6 CLK_SYS_SRAM7 CLK_SYS_SRAM8 CLK_SYS_SRAM9 CLK_SYS_SYSCFG CLK_SYS_SYSINFO CLK_SYS_TBMAN CLK_REF_TICKS CLK_SYS_TICKS CLK_SYS_TIMER0 CLK_SYS_TIMER1 CLK_SYS_TRNG CLK_PERI_UART0 CLK_SYS_UART0 CLK_PERI_UART1 CLK_SYS_UART1 CLK_SYS_USBCTRL CLK_USB CLK_SYS_WATCHDOG CLK_SYS_XIP CLK_SYS_XOSC

CLK_PERI_SPI0 :
bits : 0 - 0 (1 bit)
access : read-write

CLK_SYS_SPI0 :
bits : 1 - 1 (1 bit)
access : read-write

CLK_PERI_SPI1 :
bits : 2 - 2 (1 bit)
access : read-write

CLK_SYS_SPI1 :
bits : 3 - 3 (1 bit)
access : read-write

CLK_SYS_SRAM0 :
bits : 4 - 4 (1 bit)
access : read-write

CLK_SYS_SRAM1 :
bits : 5 - 5 (1 bit)
access : read-write

CLK_SYS_SRAM2 :
bits : 6 - 6 (1 bit)
access : read-write

CLK_SYS_SRAM3 :
bits : 7 - 7 (1 bit)
access : read-write

CLK_SYS_SRAM4 :
bits : 8 - 8 (1 bit)
access : read-write

CLK_SYS_SRAM5 :
bits : 9 - 9 (1 bit)
access : read-write

CLK_SYS_SRAM6 :
bits : 10 - 10 (1 bit)
access : read-write

CLK_SYS_SRAM7 :
bits : 11 - 11 (1 bit)
access : read-write

CLK_SYS_SRAM8 :
bits : 12 - 12 (1 bit)
access : read-write

CLK_SYS_SRAM9 :
bits : 13 - 13 (1 bit)
access : read-write

CLK_SYS_SYSCFG :
bits : 14 - 14 (1 bit)
access : read-write

CLK_SYS_SYSINFO :
bits : 15 - 15 (1 bit)
access : read-write

CLK_SYS_TBMAN :
bits : 16 - 16 (1 bit)
access : read-write

CLK_REF_TICKS :
bits : 17 - 17 (1 bit)
access : read-write

CLK_SYS_TICKS :
bits : 18 - 18 (1 bit)
access : read-write

CLK_SYS_TIMER0 :
bits : 19 - 19 (1 bit)
access : read-write

CLK_SYS_TIMER1 :
bits : 20 - 20 (1 bit)
access : read-write

CLK_SYS_TRNG :
bits : 21 - 21 (1 bit)
access : read-write

CLK_PERI_UART0 :
bits : 22 - 22 (1 bit)
access : read-write

CLK_SYS_UART0 :
bits : 23 - 23 (1 bit)
access : read-write

CLK_PERI_UART1 :
bits : 24 - 24 (1 bit)
access : read-write

CLK_SYS_UART1 :
bits : 25 - 25 (1 bit)
access : read-write

CLK_SYS_USBCTRL :
bits : 26 - 26 (1 bit)
access : read-write

CLK_USB :
bits : 27 - 27 (1 bit)
access : read-write

CLK_SYS_WATCHDOG :
bits : 28 - 28 (1 bit)
access : read-write

CLK_SYS_XIP :
bits : 29 - 29 (1 bit)
access : read-write

CLK_SYS_XOSC :
bits : 30 - 30 (1 bit)
access : read-write


SLEEP_EN0

enable clock in sleep mode
address_offset : 0xB4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SLEEP_EN0 SLEEP_EN0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CLK_SYS_CLOCKS CLK_SYS_ACCESSCTRL CLK_ADC CLK_SYS_ADC CLK_SYS_BOOTRAM CLK_SYS_BUSCTRL CLK_SYS_BUSFABRIC CLK_SYS_DMA CLK_SYS_GLITCH_DETECTOR CLK_HSTX CLK_SYS_HSTX CLK_SYS_I2C0 CLK_SYS_I2C1 CLK_SYS_IO CLK_SYS_JTAG CLK_REF_OTP CLK_SYS_OTP CLK_SYS_PADS CLK_SYS_PIO0 CLK_SYS_PIO1 CLK_SYS_PIO2 CLK_SYS_PLL_SYS CLK_SYS_PLL_USB CLK_REF_POWMAN CLK_SYS_POWMAN CLK_SYS_PWM CLK_SYS_RESETS CLK_SYS_ROM CLK_SYS_ROSC CLK_SYS_PSM CLK_SYS_SHA256 CLK_SYS_SIO

CLK_SYS_CLOCKS :
bits : 0 - 0 (1 bit)
access : read-write

CLK_SYS_ACCESSCTRL :
bits : 1 - 1 (1 bit)
access : read-write

CLK_ADC :
bits : 2 - 2 (1 bit)
access : read-write

CLK_SYS_ADC :
bits : 3 - 3 (1 bit)
access : read-write

CLK_SYS_BOOTRAM :
bits : 4 - 4 (1 bit)
access : read-write

CLK_SYS_BUSCTRL :
bits : 5 - 5 (1 bit)
access : read-write

CLK_SYS_BUSFABRIC :
bits : 6 - 6 (1 bit)
access : read-write

CLK_SYS_DMA :
bits : 7 - 7 (1 bit)
access : read-write

CLK_SYS_GLITCH_DETECTOR :
bits : 8 - 8 (1 bit)
access : read-write

CLK_HSTX :
bits : 9 - 9 (1 bit)
access : read-write

CLK_SYS_HSTX :
bits : 10 - 10 (1 bit)
access : read-write

CLK_SYS_I2C0 :
bits : 11 - 11 (1 bit)
access : read-write

CLK_SYS_I2C1 :
bits : 12 - 12 (1 bit)
access : read-write

CLK_SYS_IO :
bits : 13 - 13 (1 bit)
access : read-write

CLK_SYS_JTAG :
bits : 14 - 14 (1 bit)
access : read-write

CLK_REF_OTP :
bits : 15 - 15 (1 bit)
access : read-write

CLK_SYS_OTP :
bits : 16 - 16 (1 bit)
access : read-write

CLK_SYS_PADS :
bits : 17 - 17 (1 bit)
access : read-write

CLK_SYS_PIO0 :
bits : 18 - 18 (1 bit)
access : read-write

CLK_SYS_PIO1 :
bits : 19 - 19 (1 bit)
access : read-write

CLK_SYS_PIO2 :
bits : 20 - 20 (1 bit)
access : read-write

CLK_SYS_PLL_SYS :
bits : 21 - 21 (1 bit)
access : read-write

CLK_SYS_PLL_USB :
bits : 22 - 22 (1 bit)
access : read-write

CLK_REF_POWMAN :
bits : 23 - 23 (1 bit)
access : read-write

CLK_SYS_POWMAN :
bits : 24 - 24 (1 bit)
access : read-write

CLK_SYS_PWM :
bits : 25 - 25 (1 bit)
access : read-write

CLK_SYS_RESETS :
bits : 26 - 26 (1 bit)
access : read-write

CLK_SYS_ROM :
bits : 27 - 27 (1 bit)
access : read-write

CLK_SYS_ROSC :
bits : 28 - 28 (1 bit)
access : read-write

CLK_SYS_PSM :
bits : 29 - 29 (1 bit)
access : read-write

CLK_SYS_SHA256 :
bits : 30 - 30 (1 bit)
access : read-write

CLK_SYS_SIO :
bits : 31 - 31 (1 bit)
access : read-write


SLEEP_EN1

enable clock in sleep mode
address_offset : 0xB8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SLEEP_EN1 SLEEP_EN1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CLK_PERI_SPI0 CLK_SYS_SPI0 CLK_PERI_SPI1 CLK_SYS_SPI1 CLK_SYS_SRAM0 CLK_SYS_SRAM1 CLK_SYS_SRAM2 CLK_SYS_SRAM3 CLK_SYS_SRAM4 CLK_SYS_SRAM5 CLK_SYS_SRAM6 CLK_SYS_SRAM7 CLK_SYS_SRAM8 CLK_SYS_SRAM9 CLK_SYS_SYSCFG CLK_SYS_SYSINFO CLK_SYS_TBMAN CLK_REF_TICKS CLK_SYS_TICKS CLK_SYS_TIMER0 CLK_SYS_TIMER1 CLK_SYS_TRNG CLK_PERI_UART0 CLK_SYS_UART0 CLK_PERI_UART1 CLK_SYS_UART1 CLK_SYS_USBCTRL CLK_USB CLK_SYS_WATCHDOG CLK_SYS_XIP CLK_SYS_XOSC

CLK_PERI_SPI0 :
bits : 0 - 0 (1 bit)
access : read-write

CLK_SYS_SPI0 :
bits : 1 - 1 (1 bit)
access : read-write

CLK_PERI_SPI1 :
bits : 2 - 2 (1 bit)
access : read-write

CLK_SYS_SPI1 :
bits : 3 - 3 (1 bit)
access : read-write

CLK_SYS_SRAM0 :
bits : 4 - 4 (1 bit)
access : read-write

CLK_SYS_SRAM1 :
bits : 5 - 5 (1 bit)
access : read-write

CLK_SYS_SRAM2 :
bits : 6 - 6 (1 bit)
access : read-write

CLK_SYS_SRAM3 :
bits : 7 - 7 (1 bit)
access : read-write

CLK_SYS_SRAM4 :
bits : 8 - 8 (1 bit)
access : read-write

CLK_SYS_SRAM5 :
bits : 9 - 9 (1 bit)
access : read-write

CLK_SYS_SRAM6 :
bits : 10 - 10 (1 bit)
access : read-write

CLK_SYS_SRAM7 :
bits : 11 - 11 (1 bit)
access : read-write

CLK_SYS_SRAM8 :
bits : 12 - 12 (1 bit)
access : read-write

CLK_SYS_SRAM9 :
bits : 13 - 13 (1 bit)
access : read-write

CLK_SYS_SYSCFG :
bits : 14 - 14 (1 bit)
access : read-write

CLK_SYS_SYSINFO :
bits : 15 - 15 (1 bit)
access : read-write

CLK_SYS_TBMAN :
bits : 16 - 16 (1 bit)
access : read-write

CLK_REF_TICKS :
bits : 17 - 17 (1 bit)
access : read-write

CLK_SYS_TICKS :
bits : 18 - 18 (1 bit)
access : read-write

CLK_SYS_TIMER0 :
bits : 19 - 19 (1 bit)
access : read-write

CLK_SYS_TIMER1 :
bits : 20 - 20 (1 bit)
access : read-write

CLK_SYS_TRNG :
bits : 21 - 21 (1 bit)
access : read-write

CLK_PERI_UART0 :
bits : 22 - 22 (1 bit)
access : read-write

CLK_SYS_UART0 :
bits : 23 - 23 (1 bit)
access : read-write

CLK_PERI_UART1 :
bits : 24 - 24 (1 bit)
access : read-write

CLK_SYS_UART1 :
bits : 25 - 25 (1 bit)
access : read-write

CLK_SYS_USBCTRL :
bits : 26 - 26 (1 bit)
access : read-write

CLK_USB :
bits : 27 - 27 (1 bit)
access : read-write

CLK_SYS_WATCHDOG :
bits : 28 - 28 (1 bit)
access : read-write

CLK_SYS_XIP :
bits : 29 - 29 (1 bit)
access : read-write

CLK_SYS_XOSC :
bits : 30 - 30 (1 bit)
access : read-write


ENABLED0

indicates the state of the clock enable
address_offset : 0xBC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ENABLED0 ENABLED0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CLK_SYS_CLOCKS CLK_SYS_ACCESSCTRL CLK_ADC CLK_SYS_ADC CLK_SYS_BOOTRAM CLK_SYS_BUSCTRL CLK_SYS_BUSFABRIC CLK_SYS_DMA CLK_SYS_GLITCH_DETECTOR CLK_HSTX CLK_SYS_HSTX CLK_SYS_I2C0 CLK_SYS_I2C1 CLK_SYS_IO CLK_SYS_JTAG CLK_REF_OTP CLK_SYS_OTP CLK_SYS_PADS CLK_SYS_PIO0 CLK_SYS_PIO1 CLK_SYS_PIO2 CLK_SYS_PLL_SYS CLK_SYS_PLL_USB CLK_REF_POWMAN CLK_SYS_POWMAN CLK_SYS_PWM CLK_SYS_RESETS CLK_SYS_ROM CLK_SYS_ROSC CLK_SYS_PSM CLK_SYS_SHA256 CLK_SYS_SIO

CLK_SYS_CLOCKS :
bits : 0 - 0 (1 bit)
access : read-only

CLK_SYS_ACCESSCTRL :
bits : 1 - 1 (1 bit)
access : read-only

CLK_ADC :
bits : 2 - 2 (1 bit)
access : read-only

CLK_SYS_ADC :
bits : 3 - 3 (1 bit)
access : read-only

CLK_SYS_BOOTRAM :
bits : 4 - 4 (1 bit)
access : read-only

CLK_SYS_BUSCTRL :
bits : 5 - 5 (1 bit)
access : read-only

CLK_SYS_BUSFABRIC :
bits : 6 - 6 (1 bit)
access : read-only

CLK_SYS_DMA :
bits : 7 - 7 (1 bit)
access : read-only

CLK_SYS_GLITCH_DETECTOR :
bits : 8 - 8 (1 bit)
access : read-only

CLK_HSTX :
bits : 9 - 9 (1 bit)
access : read-only

CLK_SYS_HSTX :
bits : 10 - 10 (1 bit)
access : read-only

CLK_SYS_I2C0 :
bits : 11 - 11 (1 bit)
access : read-only

CLK_SYS_I2C1 :
bits : 12 - 12 (1 bit)
access : read-only

CLK_SYS_IO :
bits : 13 - 13 (1 bit)
access : read-only

CLK_SYS_JTAG :
bits : 14 - 14 (1 bit)
access : read-only

CLK_REF_OTP :
bits : 15 - 15 (1 bit)
access : read-only

CLK_SYS_OTP :
bits : 16 - 16 (1 bit)
access : read-only

CLK_SYS_PADS :
bits : 17 - 17 (1 bit)
access : read-only

CLK_SYS_PIO0 :
bits : 18 - 18 (1 bit)
access : read-only

CLK_SYS_PIO1 :
bits : 19 - 19 (1 bit)
access : read-only

CLK_SYS_PIO2 :
bits : 20 - 20 (1 bit)
access : read-only

CLK_SYS_PLL_SYS :
bits : 21 - 21 (1 bit)
access : read-only

CLK_SYS_PLL_USB :
bits : 22 - 22 (1 bit)
access : read-only

CLK_REF_POWMAN :
bits : 23 - 23 (1 bit)
access : read-only

CLK_SYS_POWMAN :
bits : 24 - 24 (1 bit)
access : read-only

CLK_SYS_PWM :
bits : 25 - 25 (1 bit)
access : read-only

CLK_SYS_RESETS :
bits : 26 - 26 (1 bit)
access : read-only

CLK_SYS_ROM :
bits : 27 - 27 (1 bit)
access : read-only

CLK_SYS_ROSC :
bits : 28 - 28 (1 bit)
access : read-only

CLK_SYS_PSM :
bits : 29 - 29 (1 bit)
access : read-only

CLK_SYS_SHA256 :
bits : 30 - 30 (1 bit)
access : read-only

CLK_SYS_SIO :
bits : 31 - 31 (1 bit)
access : read-only


CLK_GPOUT1_CTRL

Clock control, can be changed on-the-fly (except for auxsrc)
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CLK_GPOUT1_CTRL CLK_GPOUT1_CTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AUXSRC KILL ENABLE DC50 PHASE NUDGE ENABLED

AUXSRC : Selects the auxiliary clock source, will glitch when switching
bits : 5 - 8 (4 bit)
access : read-write

Enumeration:

0 : clksrc_pll_sys


1 : clksrc_gpin0


2 : clksrc_gpin1


3 : clksrc_pll_usb


4 : clksrc_pll_usb_primary_ref_opcg


5 : rosc_clksrc


6 : xosc_clksrc


7 : lposc_clksrc


8 : clk_sys


9 : clk_usb


10 : clk_adc


11 : clk_ref


12 : clk_peri


13 : clk_hstx


14 : otp_clk2fc


End of enumeration elements list.

KILL : Asynchronously kills the clock generator, enable must be set low before deasserting kill
bits : 10 - 10 (1 bit)
access : read-write

ENABLE : Starts and stops the clock generator cleanly
bits : 11 - 11 (1 bit)
access : read-write

DC50 : Enables duty cycle correction for odd divisors, can be changed on-the-fly
bits : 12 - 12 (1 bit)
access : read-write

PHASE : This delays the enable signal by up to 3 cycles of the input clock This must be set before the clock is enabled to have any effect
bits : 16 - 17 (2 bit)
access : read-write

NUDGE : An edge on this signal shifts the phase of the output by 1 cycle of the input clock This can be done at any time
bits : 20 - 20 (1 bit)
access : read-write

ENABLED : clock generator is enabled
bits : 28 - 28 (1 bit)
access : read-only


ENABLED1

indicates the state of the clock enable
address_offset : 0xC0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ENABLED1 ENABLED1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CLK_PERI_SPI0 CLK_SYS_SPI0 CLK_PERI_SPI1 CLK_SYS_SPI1 CLK_SYS_SRAM0 CLK_SYS_SRAM1 CLK_SYS_SRAM2 CLK_SYS_SRAM3 CLK_SYS_SRAM4 CLK_SYS_SRAM5 CLK_SYS_SRAM6 CLK_SYS_SRAM7 CLK_SYS_SRAM8 CLK_SYS_SRAM9 CLK_SYS_SYSCFG CLK_SYS_SYSINFO CLK_SYS_TBMAN CLK_REF_TICKS CLK_SYS_TICKS CLK_SYS_TIMER0 CLK_SYS_TIMER1 CLK_SYS_TRNG CLK_PERI_UART0 CLK_SYS_UART0 CLK_PERI_UART1 CLK_SYS_UART1 CLK_SYS_USBCTRL CLK_USB CLK_SYS_WATCHDOG CLK_SYS_XIP CLK_SYS_XOSC

CLK_PERI_SPI0 :
bits : 0 - 0 (1 bit)
access : read-only

CLK_SYS_SPI0 :
bits : 1 - 1 (1 bit)
access : read-only

CLK_PERI_SPI1 :
bits : 2 - 2 (1 bit)
access : read-only

CLK_SYS_SPI1 :
bits : 3 - 3 (1 bit)
access : read-only

CLK_SYS_SRAM0 :
bits : 4 - 4 (1 bit)
access : read-only

CLK_SYS_SRAM1 :
bits : 5 - 5 (1 bit)
access : read-only

CLK_SYS_SRAM2 :
bits : 6 - 6 (1 bit)
access : read-only

CLK_SYS_SRAM3 :
bits : 7 - 7 (1 bit)
access : read-only

CLK_SYS_SRAM4 :
bits : 8 - 8 (1 bit)
access : read-only

CLK_SYS_SRAM5 :
bits : 9 - 9 (1 bit)
access : read-only

CLK_SYS_SRAM6 :
bits : 10 - 10 (1 bit)
access : read-only

CLK_SYS_SRAM7 :
bits : 11 - 11 (1 bit)
access : read-only

CLK_SYS_SRAM8 :
bits : 12 - 12 (1 bit)
access : read-only

CLK_SYS_SRAM9 :
bits : 13 - 13 (1 bit)
access : read-only

CLK_SYS_SYSCFG :
bits : 14 - 14 (1 bit)
access : read-only

CLK_SYS_SYSINFO :
bits : 15 - 15 (1 bit)
access : read-only

CLK_SYS_TBMAN :
bits : 16 - 16 (1 bit)
access : read-only

CLK_REF_TICKS :
bits : 17 - 17 (1 bit)
access : read-only

CLK_SYS_TICKS :
bits : 18 - 18 (1 bit)
access : read-only

CLK_SYS_TIMER0 :
bits : 19 - 19 (1 bit)
access : read-only

CLK_SYS_TIMER1 :
bits : 20 - 20 (1 bit)
access : read-only

CLK_SYS_TRNG :
bits : 21 - 21 (1 bit)
access : read-only

CLK_PERI_UART0 :
bits : 22 - 22 (1 bit)
access : read-only

CLK_SYS_UART0 :
bits : 23 - 23 (1 bit)
access : read-only

CLK_PERI_UART1 :
bits : 24 - 24 (1 bit)
access : read-only

CLK_SYS_UART1 :
bits : 25 - 25 (1 bit)
access : read-only

CLK_SYS_USBCTRL :
bits : 26 - 26 (1 bit)
access : read-only

CLK_USB :
bits : 27 - 27 (1 bit)
access : read-only

CLK_SYS_WATCHDOG :
bits : 28 - 28 (1 bit)
access : read-only

CLK_SYS_XIP :
bits : 29 - 29 (1 bit)
access : read-only

CLK_SYS_XOSC :
bits : 30 - 30 (1 bit)
access : read-only


INTR

Raw Interrupts
address_offset : 0xC4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

INTR INTR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CLK_SYS_RESUS

CLK_SYS_RESUS :
bits : 0 - 0 (1 bit)
access : read-only


INTE

Interrupt Enable
address_offset : 0xC8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

INTE INTE read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CLK_SYS_RESUS

CLK_SYS_RESUS :
bits : 0 - 0 (1 bit)
access : read-write


INTF

Interrupt Force
address_offset : 0xCC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

INTF INTF read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CLK_SYS_RESUS

CLK_SYS_RESUS :
bits : 0 - 0 (1 bit)
access : read-write


INTS

Interrupt status after masking & forcing
address_offset : 0xD0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

INTS INTS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CLK_SYS_RESUS

CLK_SYS_RESUS :
bits : 0 - 0 (1 bit)
access : read-only



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