IO_QSPI

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x240 byte (0x0)
mem_usage : registers
protection :

Registers

USBPHY_DP_STATUS

GPIO_QSPI_SCLK_STATUS

GPIO_QSPI_SCLK_CTRL

GPIO_QSPI_SS_STATUS

GPIO_QSPI_SS_CTRL

GPIO_QSPI_SD0_STATUS

IRQSUMMARY_PROC0_SECURE

IRQSUMMARY_PROC0_NONSECURE

IRQSUMMARY_PROC1_SECURE

IRQSUMMARY_PROC1_NONSECURE

IRQSUMMARY_DORMANT_WAKE_SECURE

IRQSUMMARY_DORMANT_WAKE_NONSECURE

INTR

PROC0_INTE

PROC0_INTF

PROC0_INTS

PROC1_INTE

PROC1_INTF

PROC1_INTS

DORMANT_WAKE_INTE

DORMANT_WAKE_INTF

DORMANT_WAKE_INTS

GPIO_QSPI_SD0_CTRL

GPIO_QSPI_SD1_STATUS

GPIO_QSPI_SD1_CTRL

GPIO_QSPI_SD2_STATUS

GPIO_QSPI_SD2_CTRL

GPIO_QSPI_SD3_STATUS

GPIO_QSPI_SD3_CTRL

USBPHY_DP_CTRL

USBPHY_DM_STATUS

USBPHY_DM_CTRL


USBPHY_DP_STATUS


address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USBPHY_DP_STATUS USBPHY_DP_STATUS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OUTTOPAD OETOPAD INFROMPAD IRQTOPROC

OUTTOPAD : output signal to pad after register override is applied
bits : 9 - 9 (1 bit)
access : read-only

OETOPAD : output enable to pad after register override is applied
bits : 13 - 13 (1 bit)
access : read-only

INFROMPAD : input signal from pad, before filtering and override are applied
bits : 17 - 17 (1 bit)
access : read-only

IRQTOPROC : interrupt to processors, after override is applied
bits : 26 - 26 (1 bit)
access : read-only


GPIO_QSPI_SCLK_STATUS


address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GPIO_QSPI_SCLK_STATUS GPIO_QSPI_SCLK_STATUS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OUTTOPAD OETOPAD INFROMPAD IRQTOPROC

OUTTOPAD : output signal to pad after register override is applied
bits : 9 - 9 (1 bit)
access : read-only

OETOPAD : output enable to pad after register override is applied
bits : 13 - 13 (1 bit)
access : read-only

INFROMPAD : input signal from pad, before filtering and override are applied
bits : 17 - 17 (1 bit)
access : read-only

IRQTOPROC : interrupt to processors, after override is applied
bits : 26 - 26 (1 bit)
access : read-only


GPIO_QSPI_SCLK_CTRL


address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GPIO_QSPI_SCLK_CTRL GPIO_QSPI_SCLK_CTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FUNCSEL OUTOVER OEOVER INOVER IRQOVER

FUNCSEL : 0-31 -> selects pin function according to the gpio table 31 == NULL
bits : 0 - 4 (5 bit)
access : read-write

Enumeration:

0 : xip_sclk


2 : uart1_cts


3 : i2c1_sda


5 : siob_proc_58


11 : uart1_tx


31 : null


End of enumeration elements list.

OUTOVER :
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : NORMAL

drive output from peripheral signal selected by funcsel

1 : INVERT

drive output from inverse of peripheral signal selected by funcsel

2 : LOW

drive output low

3 : HIGH

drive output high

End of enumeration elements list.

OEOVER :
bits : 14 - 15 (2 bit)
access : read-write

Enumeration:

0 : NORMAL

drive output enable from peripheral signal selected by funcsel

1 : INVERT

drive output enable from inverse of peripheral signal selected by funcsel

2 : DISABLE

disable output

3 : ENABLE

enable output

End of enumeration elements list.

INOVER :
bits : 16 - 17 (2 bit)
access : read-write

Enumeration:

0 : NORMAL

don't invert the peri input

1 : INVERT

invert the peri input

2 : LOW

drive peri input low

3 : HIGH

drive peri input high

End of enumeration elements list.

IRQOVER :
bits : 28 - 29 (2 bit)
access : read-write

Enumeration:

0 : NORMAL

don't invert the interrupt

1 : INVERT

invert the interrupt

2 : LOW

drive interrupt low

3 : HIGH

drive interrupt high

End of enumeration elements list.


GPIO_QSPI_SS_STATUS


address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GPIO_QSPI_SS_STATUS GPIO_QSPI_SS_STATUS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OUTTOPAD OETOPAD INFROMPAD IRQTOPROC

OUTTOPAD : output signal to pad after register override is applied
bits : 9 - 9 (1 bit)
access : read-only

OETOPAD : output enable to pad after register override is applied
bits : 13 - 13 (1 bit)
access : read-only

INFROMPAD : input signal from pad, before filtering and override are applied
bits : 17 - 17 (1 bit)
access : read-only

IRQTOPROC : interrupt to processors, after override is applied
bits : 26 - 26 (1 bit)
access : read-only


GPIO_QSPI_SS_CTRL


address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GPIO_QSPI_SS_CTRL GPIO_QSPI_SS_CTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FUNCSEL OUTOVER OEOVER INOVER IRQOVER

FUNCSEL : 0-31 -> selects pin function according to the gpio table 31 == NULL
bits : 0 - 4 (5 bit)
access : read-write

Enumeration:

0 : xip_ss_n_0


2 : uart1_rts


3 : i2c1_scl


5 : siob_proc_59


11 : uart1_rx


31 : null


End of enumeration elements list.

OUTOVER :
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : NORMAL

drive output from peripheral signal selected by funcsel

1 : INVERT

drive output from inverse of peripheral signal selected by funcsel

2 : LOW

drive output low

3 : HIGH

drive output high

End of enumeration elements list.

OEOVER :
bits : 14 - 15 (2 bit)
access : read-write

Enumeration:

0 : NORMAL

drive output enable from peripheral signal selected by funcsel

1 : INVERT

drive output enable from inverse of peripheral signal selected by funcsel

2 : DISABLE

disable output

3 : ENABLE

enable output

End of enumeration elements list.

INOVER :
bits : 16 - 17 (2 bit)
access : read-write

Enumeration:

0 : NORMAL

don't invert the peri input

1 : INVERT

invert the peri input

2 : LOW

drive peri input low

3 : HIGH

drive peri input high

End of enumeration elements list.

IRQOVER :
bits : 28 - 29 (2 bit)
access : read-write

Enumeration:

0 : NORMAL

don't invert the interrupt

1 : INVERT

invert the interrupt

2 : LOW

drive interrupt low

3 : HIGH

drive interrupt high

End of enumeration elements list.


GPIO_QSPI_SD0_STATUS


address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GPIO_QSPI_SD0_STATUS GPIO_QSPI_SD0_STATUS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OUTTOPAD OETOPAD INFROMPAD IRQTOPROC

OUTTOPAD : output signal to pad after register override is applied
bits : 9 - 9 (1 bit)
access : read-only

OETOPAD : output enable to pad after register override is applied
bits : 13 - 13 (1 bit)
access : read-only

INFROMPAD : input signal from pad, before filtering and override are applied
bits : 17 - 17 (1 bit)
access : read-only

IRQTOPROC : interrupt to processors, after override is applied
bits : 26 - 26 (1 bit)
access : read-only


IRQSUMMARY_PROC0_SECURE


address_offset : 0x200 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IRQSUMMARY_PROC0_SECURE IRQSUMMARY_PROC0_SECURE read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 USBPHY_DP USBPHY_DM GPIO_QSPI_SCLK GPIO_QSPI_SS GPIO_QSPI_SD0 GPIO_QSPI_SD1 GPIO_QSPI_SD2 GPIO_QSPI_SD3

USBPHY_DP :
bits : 0 - 0 (1 bit)
access : read-only

USBPHY_DM :
bits : 1 - 1 (1 bit)
access : read-only

GPIO_QSPI_SCLK :
bits : 2 - 2 (1 bit)
access : read-only

GPIO_QSPI_SS :
bits : 3 - 3 (1 bit)
access : read-only

GPIO_QSPI_SD0 :
bits : 4 - 4 (1 bit)
access : read-only

GPIO_QSPI_SD1 :
bits : 5 - 5 (1 bit)
access : read-only

GPIO_QSPI_SD2 :
bits : 6 - 6 (1 bit)
access : read-only

GPIO_QSPI_SD3 :
bits : 7 - 7 (1 bit)
access : read-only


IRQSUMMARY_PROC0_NONSECURE


address_offset : 0x204 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IRQSUMMARY_PROC0_NONSECURE IRQSUMMARY_PROC0_NONSECURE read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 USBPHY_DP USBPHY_DM GPIO_QSPI_SCLK GPIO_QSPI_SS GPIO_QSPI_SD0 GPIO_QSPI_SD1 GPIO_QSPI_SD2 GPIO_QSPI_SD3

USBPHY_DP :
bits : 0 - 0 (1 bit)
access : read-only

USBPHY_DM :
bits : 1 - 1 (1 bit)
access : read-only

GPIO_QSPI_SCLK :
bits : 2 - 2 (1 bit)
access : read-only

GPIO_QSPI_SS :
bits : 3 - 3 (1 bit)
access : read-only

GPIO_QSPI_SD0 :
bits : 4 - 4 (1 bit)
access : read-only

GPIO_QSPI_SD1 :
bits : 5 - 5 (1 bit)
access : read-only

GPIO_QSPI_SD2 :
bits : 6 - 6 (1 bit)
access : read-only

GPIO_QSPI_SD3 :
bits : 7 - 7 (1 bit)
access : read-only


IRQSUMMARY_PROC1_SECURE


address_offset : 0x208 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IRQSUMMARY_PROC1_SECURE IRQSUMMARY_PROC1_SECURE read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 USBPHY_DP USBPHY_DM GPIO_QSPI_SCLK GPIO_QSPI_SS GPIO_QSPI_SD0 GPIO_QSPI_SD1 GPIO_QSPI_SD2 GPIO_QSPI_SD3

USBPHY_DP :
bits : 0 - 0 (1 bit)
access : read-only

USBPHY_DM :
bits : 1 - 1 (1 bit)
access : read-only

GPIO_QSPI_SCLK :
bits : 2 - 2 (1 bit)
access : read-only

GPIO_QSPI_SS :
bits : 3 - 3 (1 bit)
access : read-only

GPIO_QSPI_SD0 :
bits : 4 - 4 (1 bit)
access : read-only

GPIO_QSPI_SD1 :
bits : 5 - 5 (1 bit)
access : read-only

GPIO_QSPI_SD2 :
bits : 6 - 6 (1 bit)
access : read-only

GPIO_QSPI_SD3 :
bits : 7 - 7 (1 bit)
access : read-only


IRQSUMMARY_PROC1_NONSECURE


address_offset : 0x20C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IRQSUMMARY_PROC1_NONSECURE IRQSUMMARY_PROC1_NONSECURE read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 USBPHY_DP USBPHY_DM GPIO_QSPI_SCLK GPIO_QSPI_SS GPIO_QSPI_SD0 GPIO_QSPI_SD1 GPIO_QSPI_SD2 GPIO_QSPI_SD3

USBPHY_DP :
bits : 0 - 0 (1 bit)
access : read-only

USBPHY_DM :
bits : 1 - 1 (1 bit)
access : read-only

GPIO_QSPI_SCLK :
bits : 2 - 2 (1 bit)
access : read-only

GPIO_QSPI_SS :
bits : 3 - 3 (1 bit)
access : read-only

GPIO_QSPI_SD0 :
bits : 4 - 4 (1 bit)
access : read-only

GPIO_QSPI_SD1 :
bits : 5 - 5 (1 bit)
access : read-only

GPIO_QSPI_SD2 :
bits : 6 - 6 (1 bit)
access : read-only

GPIO_QSPI_SD3 :
bits : 7 - 7 (1 bit)
access : read-only


IRQSUMMARY_DORMANT_WAKE_SECURE


address_offset : 0x210 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IRQSUMMARY_DORMANT_WAKE_SECURE IRQSUMMARY_DORMANT_WAKE_SECURE read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 USBPHY_DP USBPHY_DM GPIO_QSPI_SCLK GPIO_QSPI_SS GPIO_QSPI_SD0 GPIO_QSPI_SD1 GPIO_QSPI_SD2 GPIO_QSPI_SD3

USBPHY_DP :
bits : 0 - 0 (1 bit)
access : read-only

USBPHY_DM :
bits : 1 - 1 (1 bit)
access : read-only

GPIO_QSPI_SCLK :
bits : 2 - 2 (1 bit)
access : read-only

GPIO_QSPI_SS :
bits : 3 - 3 (1 bit)
access : read-only

GPIO_QSPI_SD0 :
bits : 4 - 4 (1 bit)
access : read-only

GPIO_QSPI_SD1 :
bits : 5 - 5 (1 bit)
access : read-only

GPIO_QSPI_SD2 :
bits : 6 - 6 (1 bit)
access : read-only

GPIO_QSPI_SD3 :
bits : 7 - 7 (1 bit)
access : read-only


IRQSUMMARY_DORMANT_WAKE_NONSECURE


address_offset : 0x214 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IRQSUMMARY_DORMANT_WAKE_NONSECURE IRQSUMMARY_DORMANT_WAKE_NONSECURE read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 USBPHY_DP USBPHY_DM GPIO_QSPI_SCLK GPIO_QSPI_SS GPIO_QSPI_SD0 GPIO_QSPI_SD1 GPIO_QSPI_SD2 GPIO_QSPI_SD3

USBPHY_DP :
bits : 0 - 0 (1 bit)
access : read-only

USBPHY_DM :
bits : 1 - 1 (1 bit)
access : read-only

GPIO_QSPI_SCLK :
bits : 2 - 2 (1 bit)
access : read-only

GPIO_QSPI_SS :
bits : 3 - 3 (1 bit)
access : read-only

GPIO_QSPI_SD0 :
bits : 4 - 4 (1 bit)
access : read-only

GPIO_QSPI_SD1 :
bits : 5 - 5 (1 bit)
access : read-only

GPIO_QSPI_SD2 :
bits : 6 - 6 (1 bit)
access : read-only

GPIO_QSPI_SD3 :
bits : 7 - 7 (1 bit)
access : read-only


INTR

Raw Interrupts
address_offset : 0x218 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

INTR INTR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 USBPHY_DP_LEVEL_LOW USBPHY_DP_LEVEL_HIGH USBPHY_DP_EDGE_LOW USBPHY_DP_EDGE_HIGH USBPHY_DM_LEVEL_LOW USBPHY_DM_LEVEL_HIGH USBPHY_DM_EDGE_LOW USBPHY_DM_EDGE_HIGH GPIO_QSPI_SCLK_LEVEL_LOW GPIO_QSPI_SCLK_LEVEL_HIGH GPIO_QSPI_SCLK_EDGE_LOW GPIO_QSPI_SCLK_EDGE_HIGH GPIO_QSPI_SS_LEVEL_LOW GPIO_QSPI_SS_LEVEL_HIGH GPIO_QSPI_SS_EDGE_LOW GPIO_QSPI_SS_EDGE_HIGH GPIO_QSPI_SD0_LEVEL_LOW GPIO_QSPI_SD0_LEVEL_HIGH GPIO_QSPI_SD0_EDGE_LOW GPIO_QSPI_SD0_EDGE_HIGH GPIO_QSPI_SD1_LEVEL_LOW GPIO_QSPI_SD1_LEVEL_HIGH GPIO_QSPI_SD1_EDGE_LOW GPIO_QSPI_SD1_EDGE_HIGH GPIO_QSPI_SD2_LEVEL_LOW GPIO_QSPI_SD2_LEVEL_HIGH GPIO_QSPI_SD2_EDGE_LOW GPIO_QSPI_SD2_EDGE_HIGH GPIO_QSPI_SD3_LEVEL_LOW GPIO_QSPI_SD3_LEVEL_HIGH GPIO_QSPI_SD3_EDGE_LOW GPIO_QSPI_SD3_EDGE_HIGH

USBPHY_DP_LEVEL_LOW :
bits : 0 - 0 (1 bit)
access : read-only

USBPHY_DP_LEVEL_HIGH :
bits : 1 - 1 (1 bit)
access : read-only

USBPHY_DP_EDGE_LOW :
bits : 2 - 2 (1 bit)
access : read-write

USBPHY_DP_EDGE_HIGH :
bits : 3 - 3 (1 bit)
access : read-write

USBPHY_DM_LEVEL_LOW :
bits : 4 - 4 (1 bit)
access : read-only

USBPHY_DM_LEVEL_HIGH :
bits : 5 - 5 (1 bit)
access : read-only

USBPHY_DM_EDGE_LOW :
bits : 6 - 6 (1 bit)
access : read-write

USBPHY_DM_EDGE_HIGH :
bits : 7 - 7 (1 bit)
access : read-write

GPIO_QSPI_SCLK_LEVEL_LOW :
bits : 8 - 8 (1 bit)
access : read-only

GPIO_QSPI_SCLK_LEVEL_HIGH :
bits : 9 - 9 (1 bit)
access : read-only

GPIO_QSPI_SCLK_EDGE_LOW :
bits : 10 - 10 (1 bit)
access : read-write

GPIO_QSPI_SCLK_EDGE_HIGH :
bits : 11 - 11 (1 bit)
access : read-write

GPIO_QSPI_SS_LEVEL_LOW :
bits : 12 - 12 (1 bit)
access : read-only

GPIO_QSPI_SS_LEVEL_HIGH :
bits : 13 - 13 (1 bit)
access : read-only

GPIO_QSPI_SS_EDGE_LOW :
bits : 14 - 14 (1 bit)
access : read-write

GPIO_QSPI_SS_EDGE_HIGH :
bits : 15 - 15 (1 bit)
access : read-write

GPIO_QSPI_SD0_LEVEL_LOW :
bits : 16 - 16 (1 bit)
access : read-only

GPIO_QSPI_SD0_LEVEL_HIGH :
bits : 17 - 17 (1 bit)
access : read-only

GPIO_QSPI_SD0_EDGE_LOW :
bits : 18 - 18 (1 bit)
access : read-write

GPIO_QSPI_SD0_EDGE_HIGH :
bits : 19 - 19 (1 bit)
access : read-write

GPIO_QSPI_SD1_LEVEL_LOW :
bits : 20 - 20 (1 bit)
access : read-only

GPIO_QSPI_SD1_LEVEL_HIGH :
bits : 21 - 21 (1 bit)
access : read-only

GPIO_QSPI_SD1_EDGE_LOW :
bits : 22 - 22 (1 bit)
access : read-write

GPIO_QSPI_SD1_EDGE_HIGH :
bits : 23 - 23 (1 bit)
access : read-write

GPIO_QSPI_SD2_LEVEL_LOW :
bits : 24 - 24 (1 bit)
access : read-only

GPIO_QSPI_SD2_LEVEL_HIGH :
bits : 25 - 25 (1 bit)
access : read-only

GPIO_QSPI_SD2_EDGE_LOW :
bits : 26 - 26 (1 bit)
access : read-write

GPIO_QSPI_SD2_EDGE_HIGH :
bits : 27 - 27 (1 bit)
access : read-write

GPIO_QSPI_SD3_LEVEL_LOW :
bits : 28 - 28 (1 bit)
access : read-only

GPIO_QSPI_SD3_LEVEL_HIGH :
bits : 29 - 29 (1 bit)
access : read-only

GPIO_QSPI_SD3_EDGE_LOW :
bits : 30 - 30 (1 bit)
access : read-write

GPIO_QSPI_SD3_EDGE_HIGH :
bits : 31 - 31 (1 bit)
access : read-write


PROC0_INTE

Interrupt Enable for proc0
address_offset : 0x21C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PROC0_INTE PROC0_INTE read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 USBPHY_DP_LEVEL_LOW USBPHY_DP_LEVEL_HIGH USBPHY_DP_EDGE_LOW USBPHY_DP_EDGE_HIGH USBPHY_DM_LEVEL_LOW USBPHY_DM_LEVEL_HIGH USBPHY_DM_EDGE_LOW USBPHY_DM_EDGE_HIGH GPIO_QSPI_SCLK_LEVEL_LOW GPIO_QSPI_SCLK_LEVEL_HIGH GPIO_QSPI_SCLK_EDGE_LOW GPIO_QSPI_SCLK_EDGE_HIGH GPIO_QSPI_SS_LEVEL_LOW GPIO_QSPI_SS_LEVEL_HIGH GPIO_QSPI_SS_EDGE_LOW GPIO_QSPI_SS_EDGE_HIGH GPIO_QSPI_SD0_LEVEL_LOW GPIO_QSPI_SD0_LEVEL_HIGH GPIO_QSPI_SD0_EDGE_LOW GPIO_QSPI_SD0_EDGE_HIGH GPIO_QSPI_SD1_LEVEL_LOW GPIO_QSPI_SD1_LEVEL_HIGH GPIO_QSPI_SD1_EDGE_LOW GPIO_QSPI_SD1_EDGE_HIGH GPIO_QSPI_SD2_LEVEL_LOW GPIO_QSPI_SD2_LEVEL_HIGH GPIO_QSPI_SD2_EDGE_LOW GPIO_QSPI_SD2_EDGE_HIGH GPIO_QSPI_SD3_LEVEL_LOW GPIO_QSPI_SD3_LEVEL_HIGH GPIO_QSPI_SD3_EDGE_LOW GPIO_QSPI_SD3_EDGE_HIGH

USBPHY_DP_LEVEL_LOW :
bits : 0 - 0 (1 bit)
access : read-write

USBPHY_DP_LEVEL_HIGH :
bits : 1 - 1 (1 bit)
access : read-write

USBPHY_DP_EDGE_LOW :
bits : 2 - 2 (1 bit)
access : read-write

USBPHY_DP_EDGE_HIGH :
bits : 3 - 3 (1 bit)
access : read-write

USBPHY_DM_LEVEL_LOW :
bits : 4 - 4 (1 bit)
access : read-write

USBPHY_DM_LEVEL_HIGH :
bits : 5 - 5 (1 bit)
access : read-write

USBPHY_DM_EDGE_LOW :
bits : 6 - 6 (1 bit)
access : read-write

USBPHY_DM_EDGE_HIGH :
bits : 7 - 7 (1 bit)
access : read-write

GPIO_QSPI_SCLK_LEVEL_LOW :
bits : 8 - 8 (1 bit)
access : read-write

GPIO_QSPI_SCLK_LEVEL_HIGH :
bits : 9 - 9 (1 bit)
access : read-write

GPIO_QSPI_SCLK_EDGE_LOW :
bits : 10 - 10 (1 bit)
access : read-write

GPIO_QSPI_SCLK_EDGE_HIGH :
bits : 11 - 11 (1 bit)
access : read-write

GPIO_QSPI_SS_LEVEL_LOW :
bits : 12 - 12 (1 bit)
access : read-write

GPIO_QSPI_SS_LEVEL_HIGH :
bits : 13 - 13 (1 bit)
access : read-write

GPIO_QSPI_SS_EDGE_LOW :
bits : 14 - 14 (1 bit)
access : read-write

GPIO_QSPI_SS_EDGE_HIGH :
bits : 15 - 15 (1 bit)
access : read-write

GPIO_QSPI_SD0_LEVEL_LOW :
bits : 16 - 16 (1 bit)
access : read-write

GPIO_QSPI_SD0_LEVEL_HIGH :
bits : 17 - 17 (1 bit)
access : read-write

GPIO_QSPI_SD0_EDGE_LOW :
bits : 18 - 18 (1 bit)
access : read-write

GPIO_QSPI_SD0_EDGE_HIGH :
bits : 19 - 19 (1 bit)
access : read-write

GPIO_QSPI_SD1_LEVEL_LOW :
bits : 20 - 20 (1 bit)
access : read-write

GPIO_QSPI_SD1_LEVEL_HIGH :
bits : 21 - 21 (1 bit)
access : read-write

GPIO_QSPI_SD1_EDGE_LOW :
bits : 22 - 22 (1 bit)
access : read-write

GPIO_QSPI_SD1_EDGE_HIGH :
bits : 23 - 23 (1 bit)
access : read-write

GPIO_QSPI_SD2_LEVEL_LOW :
bits : 24 - 24 (1 bit)
access : read-write

GPIO_QSPI_SD2_LEVEL_HIGH :
bits : 25 - 25 (1 bit)
access : read-write

GPIO_QSPI_SD2_EDGE_LOW :
bits : 26 - 26 (1 bit)
access : read-write

GPIO_QSPI_SD2_EDGE_HIGH :
bits : 27 - 27 (1 bit)
access : read-write

GPIO_QSPI_SD3_LEVEL_LOW :
bits : 28 - 28 (1 bit)
access : read-write

GPIO_QSPI_SD3_LEVEL_HIGH :
bits : 29 - 29 (1 bit)
access : read-write

GPIO_QSPI_SD3_EDGE_LOW :
bits : 30 - 30 (1 bit)
access : read-write

GPIO_QSPI_SD3_EDGE_HIGH :
bits : 31 - 31 (1 bit)
access : read-write


PROC0_INTF

Interrupt Force for proc0
address_offset : 0x220 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PROC0_INTF PROC0_INTF read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 USBPHY_DP_LEVEL_LOW USBPHY_DP_LEVEL_HIGH USBPHY_DP_EDGE_LOW USBPHY_DP_EDGE_HIGH USBPHY_DM_LEVEL_LOW USBPHY_DM_LEVEL_HIGH USBPHY_DM_EDGE_LOW USBPHY_DM_EDGE_HIGH GPIO_QSPI_SCLK_LEVEL_LOW GPIO_QSPI_SCLK_LEVEL_HIGH GPIO_QSPI_SCLK_EDGE_LOW GPIO_QSPI_SCLK_EDGE_HIGH GPIO_QSPI_SS_LEVEL_LOW GPIO_QSPI_SS_LEVEL_HIGH GPIO_QSPI_SS_EDGE_LOW GPIO_QSPI_SS_EDGE_HIGH GPIO_QSPI_SD0_LEVEL_LOW GPIO_QSPI_SD0_LEVEL_HIGH GPIO_QSPI_SD0_EDGE_LOW GPIO_QSPI_SD0_EDGE_HIGH GPIO_QSPI_SD1_LEVEL_LOW GPIO_QSPI_SD1_LEVEL_HIGH GPIO_QSPI_SD1_EDGE_LOW GPIO_QSPI_SD1_EDGE_HIGH GPIO_QSPI_SD2_LEVEL_LOW GPIO_QSPI_SD2_LEVEL_HIGH GPIO_QSPI_SD2_EDGE_LOW GPIO_QSPI_SD2_EDGE_HIGH GPIO_QSPI_SD3_LEVEL_LOW GPIO_QSPI_SD3_LEVEL_HIGH GPIO_QSPI_SD3_EDGE_LOW GPIO_QSPI_SD3_EDGE_HIGH

USBPHY_DP_LEVEL_LOW :
bits : 0 - 0 (1 bit)
access : read-write

USBPHY_DP_LEVEL_HIGH :
bits : 1 - 1 (1 bit)
access : read-write

USBPHY_DP_EDGE_LOW :
bits : 2 - 2 (1 bit)
access : read-write

USBPHY_DP_EDGE_HIGH :
bits : 3 - 3 (1 bit)
access : read-write

USBPHY_DM_LEVEL_LOW :
bits : 4 - 4 (1 bit)
access : read-write

USBPHY_DM_LEVEL_HIGH :
bits : 5 - 5 (1 bit)
access : read-write

USBPHY_DM_EDGE_LOW :
bits : 6 - 6 (1 bit)
access : read-write

USBPHY_DM_EDGE_HIGH :
bits : 7 - 7 (1 bit)
access : read-write

GPIO_QSPI_SCLK_LEVEL_LOW :
bits : 8 - 8 (1 bit)
access : read-write

GPIO_QSPI_SCLK_LEVEL_HIGH :
bits : 9 - 9 (1 bit)
access : read-write

GPIO_QSPI_SCLK_EDGE_LOW :
bits : 10 - 10 (1 bit)
access : read-write

GPIO_QSPI_SCLK_EDGE_HIGH :
bits : 11 - 11 (1 bit)
access : read-write

GPIO_QSPI_SS_LEVEL_LOW :
bits : 12 - 12 (1 bit)
access : read-write

GPIO_QSPI_SS_LEVEL_HIGH :
bits : 13 - 13 (1 bit)
access : read-write

GPIO_QSPI_SS_EDGE_LOW :
bits : 14 - 14 (1 bit)
access : read-write

GPIO_QSPI_SS_EDGE_HIGH :
bits : 15 - 15 (1 bit)
access : read-write

GPIO_QSPI_SD0_LEVEL_LOW :
bits : 16 - 16 (1 bit)
access : read-write

GPIO_QSPI_SD0_LEVEL_HIGH :
bits : 17 - 17 (1 bit)
access : read-write

GPIO_QSPI_SD0_EDGE_LOW :
bits : 18 - 18 (1 bit)
access : read-write

GPIO_QSPI_SD0_EDGE_HIGH :
bits : 19 - 19 (1 bit)
access : read-write

GPIO_QSPI_SD1_LEVEL_LOW :
bits : 20 - 20 (1 bit)
access : read-write

GPIO_QSPI_SD1_LEVEL_HIGH :
bits : 21 - 21 (1 bit)
access : read-write

GPIO_QSPI_SD1_EDGE_LOW :
bits : 22 - 22 (1 bit)
access : read-write

GPIO_QSPI_SD1_EDGE_HIGH :
bits : 23 - 23 (1 bit)
access : read-write

GPIO_QSPI_SD2_LEVEL_LOW :
bits : 24 - 24 (1 bit)
access : read-write

GPIO_QSPI_SD2_LEVEL_HIGH :
bits : 25 - 25 (1 bit)
access : read-write

GPIO_QSPI_SD2_EDGE_LOW :
bits : 26 - 26 (1 bit)
access : read-write

GPIO_QSPI_SD2_EDGE_HIGH :
bits : 27 - 27 (1 bit)
access : read-write

GPIO_QSPI_SD3_LEVEL_LOW :
bits : 28 - 28 (1 bit)
access : read-write

GPIO_QSPI_SD3_LEVEL_HIGH :
bits : 29 - 29 (1 bit)
access : read-write

GPIO_QSPI_SD3_EDGE_LOW :
bits : 30 - 30 (1 bit)
access : read-write

GPIO_QSPI_SD3_EDGE_HIGH :
bits : 31 - 31 (1 bit)
access : read-write


PROC0_INTS

Interrupt status after masking & forcing for proc0
address_offset : 0x224 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PROC0_INTS PROC0_INTS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 USBPHY_DP_LEVEL_LOW USBPHY_DP_LEVEL_HIGH USBPHY_DP_EDGE_LOW USBPHY_DP_EDGE_HIGH USBPHY_DM_LEVEL_LOW USBPHY_DM_LEVEL_HIGH USBPHY_DM_EDGE_LOW USBPHY_DM_EDGE_HIGH GPIO_QSPI_SCLK_LEVEL_LOW GPIO_QSPI_SCLK_LEVEL_HIGH GPIO_QSPI_SCLK_EDGE_LOW GPIO_QSPI_SCLK_EDGE_HIGH GPIO_QSPI_SS_LEVEL_LOW GPIO_QSPI_SS_LEVEL_HIGH GPIO_QSPI_SS_EDGE_LOW GPIO_QSPI_SS_EDGE_HIGH GPIO_QSPI_SD0_LEVEL_LOW GPIO_QSPI_SD0_LEVEL_HIGH GPIO_QSPI_SD0_EDGE_LOW GPIO_QSPI_SD0_EDGE_HIGH GPIO_QSPI_SD1_LEVEL_LOW GPIO_QSPI_SD1_LEVEL_HIGH GPIO_QSPI_SD1_EDGE_LOW GPIO_QSPI_SD1_EDGE_HIGH GPIO_QSPI_SD2_LEVEL_LOW GPIO_QSPI_SD2_LEVEL_HIGH GPIO_QSPI_SD2_EDGE_LOW GPIO_QSPI_SD2_EDGE_HIGH GPIO_QSPI_SD3_LEVEL_LOW GPIO_QSPI_SD3_LEVEL_HIGH GPIO_QSPI_SD3_EDGE_LOW GPIO_QSPI_SD3_EDGE_HIGH

USBPHY_DP_LEVEL_LOW :
bits : 0 - 0 (1 bit)
access : read-only

USBPHY_DP_LEVEL_HIGH :
bits : 1 - 1 (1 bit)
access : read-only

USBPHY_DP_EDGE_LOW :
bits : 2 - 2 (1 bit)
access : read-only

USBPHY_DP_EDGE_HIGH :
bits : 3 - 3 (1 bit)
access : read-only

USBPHY_DM_LEVEL_LOW :
bits : 4 - 4 (1 bit)
access : read-only

USBPHY_DM_LEVEL_HIGH :
bits : 5 - 5 (1 bit)
access : read-only

USBPHY_DM_EDGE_LOW :
bits : 6 - 6 (1 bit)
access : read-only

USBPHY_DM_EDGE_HIGH :
bits : 7 - 7 (1 bit)
access : read-only

GPIO_QSPI_SCLK_LEVEL_LOW :
bits : 8 - 8 (1 bit)
access : read-only

GPIO_QSPI_SCLK_LEVEL_HIGH :
bits : 9 - 9 (1 bit)
access : read-only

GPIO_QSPI_SCLK_EDGE_LOW :
bits : 10 - 10 (1 bit)
access : read-only

GPIO_QSPI_SCLK_EDGE_HIGH :
bits : 11 - 11 (1 bit)
access : read-only

GPIO_QSPI_SS_LEVEL_LOW :
bits : 12 - 12 (1 bit)
access : read-only

GPIO_QSPI_SS_LEVEL_HIGH :
bits : 13 - 13 (1 bit)
access : read-only

GPIO_QSPI_SS_EDGE_LOW :
bits : 14 - 14 (1 bit)
access : read-only

GPIO_QSPI_SS_EDGE_HIGH :
bits : 15 - 15 (1 bit)
access : read-only

GPIO_QSPI_SD0_LEVEL_LOW :
bits : 16 - 16 (1 bit)
access : read-only

GPIO_QSPI_SD0_LEVEL_HIGH :
bits : 17 - 17 (1 bit)
access : read-only

GPIO_QSPI_SD0_EDGE_LOW :
bits : 18 - 18 (1 bit)
access : read-only

GPIO_QSPI_SD0_EDGE_HIGH :
bits : 19 - 19 (1 bit)
access : read-only

GPIO_QSPI_SD1_LEVEL_LOW :
bits : 20 - 20 (1 bit)
access : read-only

GPIO_QSPI_SD1_LEVEL_HIGH :
bits : 21 - 21 (1 bit)
access : read-only

GPIO_QSPI_SD1_EDGE_LOW :
bits : 22 - 22 (1 bit)
access : read-only

GPIO_QSPI_SD1_EDGE_HIGH :
bits : 23 - 23 (1 bit)
access : read-only

GPIO_QSPI_SD2_LEVEL_LOW :
bits : 24 - 24 (1 bit)
access : read-only

GPIO_QSPI_SD2_LEVEL_HIGH :
bits : 25 - 25 (1 bit)
access : read-only

GPIO_QSPI_SD2_EDGE_LOW :
bits : 26 - 26 (1 bit)
access : read-only

GPIO_QSPI_SD2_EDGE_HIGH :
bits : 27 - 27 (1 bit)
access : read-only

GPIO_QSPI_SD3_LEVEL_LOW :
bits : 28 - 28 (1 bit)
access : read-only

GPIO_QSPI_SD3_LEVEL_HIGH :
bits : 29 - 29 (1 bit)
access : read-only

GPIO_QSPI_SD3_EDGE_LOW :
bits : 30 - 30 (1 bit)
access : read-only

GPIO_QSPI_SD3_EDGE_HIGH :
bits : 31 - 31 (1 bit)
access : read-only


PROC1_INTE

Interrupt Enable for proc1
address_offset : 0x228 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PROC1_INTE PROC1_INTE read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 USBPHY_DP_LEVEL_LOW USBPHY_DP_LEVEL_HIGH USBPHY_DP_EDGE_LOW USBPHY_DP_EDGE_HIGH USBPHY_DM_LEVEL_LOW USBPHY_DM_LEVEL_HIGH USBPHY_DM_EDGE_LOW USBPHY_DM_EDGE_HIGH GPIO_QSPI_SCLK_LEVEL_LOW GPIO_QSPI_SCLK_LEVEL_HIGH GPIO_QSPI_SCLK_EDGE_LOW GPIO_QSPI_SCLK_EDGE_HIGH GPIO_QSPI_SS_LEVEL_LOW GPIO_QSPI_SS_LEVEL_HIGH GPIO_QSPI_SS_EDGE_LOW GPIO_QSPI_SS_EDGE_HIGH GPIO_QSPI_SD0_LEVEL_LOW GPIO_QSPI_SD0_LEVEL_HIGH GPIO_QSPI_SD0_EDGE_LOW GPIO_QSPI_SD0_EDGE_HIGH GPIO_QSPI_SD1_LEVEL_LOW GPIO_QSPI_SD1_LEVEL_HIGH GPIO_QSPI_SD1_EDGE_LOW GPIO_QSPI_SD1_EDGE_HIGH GPIO_QSPI_SD2_LEVEL_LOW GPIO_QSPI_SD2_LEVEL_HIGH GPIO_QSPI_SD2_EDGE_LOW GPIO_QSPI_SD2_EDGE_HIGH GPIO_QSPI_SD3_LEVEL_LOW GPIO_QSPI_SD3_LEVEL_HIGH GPIO_QSPI_SD3_EDGE_LOW GPIO_QSPI_SD3_EDGE_HIGH

USBPHY_DP_LEVEL_LOW :
bits : 0 - 0 (1 bit)
access : read-write

USBPHY_DP_LEVEL_HIGH :
bits : 1 - 1 (1 bit)
access : read-write

USBPHY_DP_EDGE_LOW :
bits : 2 - 2 (1 bit)
access : read-write

USBPHY_DP_EDGE_HIGH :
bits : 3 - 3 (1 bit)
access : read-write

USBPHY_DM_LEVEL_LOW :
bits : 4 - 4 (1 bit)
access : read-write

USBPHY_DM_LEVEL_HIGH :
bits : 5 - 5 (1 bit)
access : read-write

USBPHY_DM_EDGE_LOW :
bits : 6 - 6 (1 bit)
access : read-write

USBPHY_DM_EDGE_HIGH :
bits : 7 - 7 (1 bit)
access : read-write

GPIO_QSPI_SCLK_LEVEL_LOW :
bits : 8 - 8 (1 bit)
access : read-write

GPIO_QSPI_SCLK_LEVEL_HIGH :
bits : 9 - 9 (1 bit)
access : read-write

GPIO_QSPI_SCLK_EDGE_LOW :
bits : 10 - 10 (1 bit)
access : read-write

GPIO_QSPI_SCLK_EDGE_HIGH :
bits : 11 - 11 (1 bit)
access : read-write

GPIO_QSPI_SS_LEVEL_LOW :
bits : 12 - 12 (1 bit)
access : read-write

GPIO_QSPI_SS_LEVEL_HIGH :
bits : 13 - 13 (1 bit)
access : read-write

GPIO_QSPI_SS_EDGE_LOW :
bits : 14 - 14 (1 bit)
access : read-write

GPIO_QSPI_SS_EDGE_HIGH :
bits : 15 - 15 (1 bit)
access : read-write

GPIO_QSPI_SD0_LEVEL_LOW :
bits : 16 - 16 (1 bit)
access : read-write

GPIO_QSPI_SD0_LEVEL_HIGH :
bits : 17 - 17 (1 bit)
access : read-write

GPIO_QSPI_SD0_EDGE_LOW :
bits : 18 - 18 (1 bit)
access : read-write

GPIO_QSPI_SD0_EDGE_HIGH :
bits : 19 - 19 (1 bit)
access : read-write

GPIO_QSPI_SD1_LEVEL_LOW :
bits : 20 - 20 (1 bit)
access : read-write

GPIO_QSPI_SD1_LEVEL_HIGH :
bits : 21 - 21 (1 bit)
access : read-write

GPIO_QSPI_SD1_EDGE_LOW :
bits : 22 - 22 (1 bit)
access : read-write

GPIO_QSPI_SD1_EDGE_HIGH :
bits : 23 - 23 (1 bit)
access : read-write

GPIO_QSPI_SD2_LEVEL_LOW :
bits : 24 - 24 (1 bit)
access : read-write

GPIO_QSPI_SD2_LEVEL_HIGH :
bits : 25 - 25 (1 bit)
access : read-write

GPIO_QSPI_SD2_EDGE_LOW :
bits : 26 - 26 (1 bit)
access : read-write

GPIO_QSPI_SD2_EDGE_HIGH :
bits : 27 - 27 (1 bit)
access : read-write

GPIO_QSPI_SD3_LEVEL_LOW :
bits : 28 - 28 (1 bit)
access : read-write

GPIO_QSPI_SD3_LEVEL_HIGH :
bits : 29 - 29 (1 bit)
access : read-write

GPIO_QSPI_SD3_EDGE_LOW :
bits : 30 - 30 (1 bit)
access : read-write

GPIO_QSPI_SD3_EDGE_HIGH :
bits : 31 - 31 (1 bit)
access : read-write


PROC1_INTF

Interrupt Force for proc1
address_offset : 0x22C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PROC1_INTF PROC1_INTF read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 USBPHY_DP_LEVEL_LOW USBPHY_DP_LEVEL_HIGH USBPHY_DP_EDGE_LOW USBPHY_DP_EDGE_HIGH USBPHY_DM_LEVEL_LOW USBPHY_DM_LEVEL_HIGH USBPHY_DM_EDGE_LOW USBPHY_DM_EDGE_HIGH GPIO_QSPI_SCLK_LEVEL_LOW GPIO_QSPI_SCLK_LEVEL_HIGH GPIO_QSPI_SCLK_EDGE_LOW GPIO_QSPI_SCLK_EDGE_HIGH GPIO_QSPI_SS_LEVEL_LOW GPIO_QSPI_SS_LEVEL_HIGH GPIO_QSPI_SS_EDGE_LOW GPIO_QSPI_SS_EDGE_HIGH GPIO_QSPI_SD0_LEVEL_LOW GPIO_QSPI_SD0_LEVEL_HIGH GPIO_QSPI_SD0_EDGE_LOW GPIO_QSPI_SD0_EDGE_HIGH GPIO_QSPI_SD1_LEVEL_LOW GPIO_QSPI_SD1_LEVEL_HIGH GPIO_QSPI_SD1_EDGE_LOW GPIO_QSPI_SD1_EDGE_HIGH GPIO_QSPI_SD2_LEVEL_LOW GPIO_QSPI_SD2_LEVEL_HIGH GPIO_QSPI_SD2_EDGE_LOW GPIO_QSPI_SD2_EDGE_HIGH GPIO_QSPI_SD3_LEVEL_LOW GPIO_QSPI_SD3_LEVEL_HIGH GPIO_QSPI_SD3_EDGE_LOW GPIO_QSPI_SD3_EDGE_HIGH

USBPHY_DP_LEVEL_LOW :
bits : 0 - 0 (1 bit)
access : read-write

USBPHY_DP_LEVEL_HIGH :
bits : 1 - 1 (1 bit)
access : read-write

USBPHY_DP_EDGE_LOW :
bits : 2 - 2 (1 bit)
access : read-write

USBPHY_DP_EDGE_HIGH :
bits : 3 - 3 (1 bit)
access : read-write

USBPHY_DM_LEVEL_LOW :
bits : 4 - 4 (1 bit)
access : read-write

USBPHY_DM_LEVEL_HIGH :
bits : 5 - 5 (1 bit)
access : read-write

USBPHY_DM_EDGE_LOW :
bits : 6 - 6 (1 bit)
access : read-write

USBPHY_DM_EDGE_HIGH :
bits : 7 - 7 (1 bit)
access : read-write

GPIO_QSPI_SCLK_LEVEL_LOW :
bits : 8 - 8 (1 bit)
access : read-write

GPIO_QSPI_SCLK_LEVEL_HIGH :
bits : 9 - 9 (1 bit)
access : read-write

GPIO_QSPI_SCLK_EDGE_LOW :
bits : 10 - 10 (1 bit)
access : read-write

GPIO_QSPI_SCLK_EDGE_HIGH :
bits : 11 - 11 (1 bit)
access : read-write

GPIO_QSPI_SS_LEVEL_LOW :
bits : 12 - 12 (1 bit)
access : read-write

GPIO_QSPI_SS_LEVEL_HIGH :
bits : 13 - 13 (1 bit)
access : read-write

GPIO_QSPI_SS_EDGE_LOW :
bits : 14 - 14 (1 bit)
access : read-write

GPIO_QSPI_SS_EDGE_HIGH :
bits : 15 - 15 (1 bit)
access : read-write

GPIO_QSPI_SD0_LEVEL_LOW :
bits : 16 - 16 (1 bit)
access : read-write

GPIO_QSPI_SD0_LEVEL_HIGH :
bits : 17 - 17 (1 bit)
access : read-write

GPIO_QSPI_SD0_EDGE_LOW :
bits : 18 - 18 (1 bit)
access : read-write

GPIO_QSPI_SD0_EDGE_HIGH :
bits : 19 - 19 (1 bit)
access : read-write

GPIO_QSPI_SD1_LEVEL_LOW :
bits : 20 - 20 (1 bit)
access : read-write

GPIO_QSPI_SD1_LEVEL_HIGH :
bits : 21 - 21 (1 bit)
access : read-write

GPIO_QSPI_SD1_EDGE_LOW :
bits : 22 - 22 (1 bit)
access : read-write

GPIO_QSPI_SD1_EDGE_HIGH :
bits : 23 - 23 (1 bit)
access : read-write

GPIO_QSPI_SD2_LEVEL_LOW :
bits : 24 - 24 (1 bit)
access : read-write

GPIO_QSPI_SD2_LEVEL_HIGH :
bits : 25 - 25 (1 bit)
access : read-write

GPIO_QSPI_SD2_EDGE_LOW :
bits : 26 - 26 (1 bit)
access : read-write

GPIO_QSPI_SD2_EDGE_HIGH :
bits : 27 - 27 (1 bit)
access : read-write

GPIO_QSPI_SD3_LEVEL_LOW :
bits : 28 - 28 (1 bit)
access : read-write

GPIO_QSPI_SD3_LEVEL_HIGH :
bits : 29 - 29 (1 bit)
access : read-write

GPIO_QSPI_SD3_EDGE_LOW :
bits : 30 - 30 (1 bit)
access : read-write

GPIO_QSPI_SD3_EDGE_HIGH :
bits : 31 - 31 (1 bit)
access : read-write


PROC1_INTS

Interrupt status after masking & forcing for proc1
address_offset : 0x230 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PROC1_INTS PROC1_INTS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 USBPHY_DP_LEVEL_LOW USBPHY_DP_LEVEL_HIGH USBPHY_DP_EDGE_LOW USBPHY_DP_EDGE_HIGH USBPHY_DM_LEVEL_LOW USBPHY_DM_LEVEL_HIGH USBPHY_DM_EDGE_LOW USBPHY_DM_EDGE_HIGH GPIO_QSPI_SCLK_LEVEL_LOW GPIO_QSPI_SCLK_LEVEL_HIGH GPIO_QSPI_SCLK_EDGE_LOW GPIO_QSPI_SCLK_EDGE_HIGH GPIO_QSPI_SS_LEVEL_LOW GPIO_QSPI_SS_LEVEL_HIGH GPIO_QSPI_SS_EDGE_LOW GPIO_QSPI_SS_EDGE_HIGH GPIO_QSPI_SD0_LEVEL_LOW GPIO_QSPI_SD0_LEVEL_HIGH GPIO_QSPI_SD0_EDGE_LOW GPIO_QSPI_SD0_EDGE_HIGH GPIO_QSPI_SD1_LEVEL_LOW GPIO_QSPI_SD1_LEVEL_HIGH GPIO_QSPI_SD1_EDGE_LOW GPIO_QSPI_SD1_EDGE_HIGH GPIO_QSPI_SD2_LEVEL_LOW GPIO_QSPI_SD2_LEVEL_HIGH GPIO_QSPI_SD2_EDGE_LOW GPIO_QSPI_SD2_EDGE_HIGH GPIO_QSPI_SD3_LEVEL_LOW GPIO_QSPI_SD3_LEVEL_HIGH GPIO_QSPI_SD3_EDGE_LOW GPIO_QSPI_SD3_EDGE_HIGH

USBPHY_DP_LEVEL_LOW :
bits : 0 - 0 (1 bit)
access : read-only

USBPHY_DP_LEVEL_HIGH :
bits : 1 - 1 (1 bit)
access : read-only

USBPHY_DP_EDGE_LOW :
bits : 2 - 2 (1 bit)
access : read-only

USBPHY_DP_EDGE_HIGH :
bits : 3 - 3 (1 bit)
access : read-only

USBPHY_DM_LEVEL_LOW :
bits : 4 - 4 (1 bit)
access : read-only

USBPHY_DM_LEVEL_HIGH :
bits : 5 - 5 (1 bit)
access : read-only

USBPHY_DM_EDGE_LOW :
bits : 6 - 6 (1 bit)
access : read-only

USBPHY_DM_EDGE_HIGH :
bits : 7 - 7 (1 bit)
access : read-only

GPIO_QSPI_SCLK_LEVEL_LOW :
bits : 8 - 8 (1 bit)
access : read-only

GPIO_QSPI_SCLK_LEVEL_HIGH :
bits : 9 - 9 (1 bit)
access : read-only

GPIO_QSPI_SCLK_EDGE_LOW :
bits : 10 - 10 (1 bit)
access : read-only

GPIO_QSPI_SCLK_EDGE_HIGH :
bits : 11 - 11 (1 bit)
access : read-only

GPIO_QSPI_SS_LEVEL_LOW :
bits : 12 - 12 (1 bit)
access : read-only

GPIO_QSPI_SS_LEVEL_HIGH :
bits : 13 - 13 (1 bit)
access : read-only

GPIO_QSPI_SS_EDGE_LOW :
bits : 14 - 14 (1 bit)
access : read-only

GPIO_QSPI_SS_EDGE_HIGH :
bits : 15 - 15 (1 bit)
access : read-only

GPIO_QSPI_SD0_LEVEL_LOW :
bits : 16 - 16 (1 bit)
access : read-only

GPIO_QSPI_SD0_LEVEL_HIGH :
bits : 17 - 17 (1 bit)
access : read-only

GPIO_QSPI_SD0_EDGE_LOW :
bits : 18 - 18 (1 bit)
access : read-only

GPIO_QSPI_SD0_EDGE_HIGH :
bits : 19 - 19 (1 bit)
access : read-only

GPIO_QSPI_SD1_LEVEL_LOW :
bits : 20 - 20 (1 bit)
access : read-only

GPIO_QSPI_SD1_LEVEL_HIGH :
bits : 21 - 21 (1 bit)
access : read-only

GPIO_QSPI_SD1_EDGE_LOW :
bits : 22 - 22 (1 bit)
access : read-only

GPIO_QSPI_SD1_EDGE_HIGH :
bits : 23 - 23 (1 bit)
access : read-only

GPIO_QSPI_SD2_LEVEL_LOW :
bits : 24 - 24 (1 bit)
access : read-only

GPIO_QSPI_SD2_LEVEL_HIGH :
bits : 25 - 25 (1 bit)
access : read-only

GPIO_QSPI_SD2_EDGE_LOW :
bits : 26 - 26 (1 bit)
access : read-only

GPIO_QSPI_SD2_EDGE_HIGH :
bits : 27 - 27 (1 bit)
access : read-only

GPIO_QSPI_SD3_LEVEL_LOW :
bits : 28 - 28 (1 bit)
access : read-only

GPIO_QSPI_SD3_LEVEL_HIGH :
bits : 29 - 29 (1 bit)
access : read-only

GPIO_QSPI_SD3_EDGE_LOW :
bits : 30 - 30 (1 bit)
access : read-only

GPIO_QSPI_SD3_EDGE_HIGH :
bits : 31 - 31 (1 bit)
access : read-only


DORMANT_WAKE_INTE

Interrupt Enable for dormant_wake
address_offset : 0x234 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DORMANT_WAKE_INTE DORMANT_WAKE_INTE read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 USBPHY_DP_LEVEL_LOW USBPHY_DP_LEVEL_HIGH USBPHY_DP_EDGE_LOW USBPHY_DP_EDGE_HIGH USBPHY_DM_LEVEL_LOW USBPHY_DM_LEVEL_HIGH USBPHY_DM_EDGE_LOW USBPHY_DM_EDGE_HIGH GPIO_QSPI_SCLK_LEVEL_LOW GPIO_QSPI_SCLK_LEVEL_HIGH GPIO_QSPI_SCLK_EDGE_LOW GPIO_QSPI_SCLK_EDGE_HIGH GPIO_QSPI_SS_LEVEL_LOW GPIO_QSPI_SS_LEVEL_HIGH GPIO_QSPI_SS_EDGE_LOW GPIO_QSPI_SS_EDGE_HIGH GPIO_QSPI_SD0_LEVEL_LOW GPIO_QSPI_SD0_LEVEL_HIGH GPIO_QSPI_SD0_EDGE_LOW GPIO_QSPI_SD0_EDGE_HIGH GPIO_QSPI_SD1_LEVEL_LOW GPIO_QSPI_SD1_LEVEL_HIGH GPIO_QSPI_SD1_EDGE_LOW GPIO_QSPI_SD1_EDGE_HIGH GPIO_QSPI_SD2_LEVEL_LOW GPIO_QSPI_SD2_LEVEL_HIGH GPIO_QSPI_SD2_EDGE_LOW GPIO_QSPI_SD2_EDGE_HIGH GPIO_QSPI_SD3_LEVEL_LOW GPIO_QSPI_SD3_LEVEL_HIGH GPIO_QSPI_SD3_EDGE_LOW GPIO_QSPI_SD3_EDGE_HIGH

USBPHY_DP_LEVEL_LOW :
bits : 0 - 0 (1 bit)
access : read-write

USBPHY_DP_LEVEL_HIGH :
bits : 1 - 1 (1 bit)
access : read-write

USBPHY_DP_EDGE_LOW :
bits : 2 - 2 (1 bit)
access : read-write

USBPHY_DP_EDGE_HIGH :
bits : 3 - 3 (1 bit)
access : read-write

USBPHY_DM_LEVEL_LOW :
bits : 4 - 4 (1 bit)
access : read-write

USBPHY_DM_LEVEL_HIGH :
bits : 5 - 5 (1 bit)
access : read-write

USBPHY_DM_EDGE_LOW :
bits : 6 - 6 (1 bit)
access : read-write

USBPHY_DM_EDGE_HIGH :
bits : 7 - 7 (1 bit)
access : read-write

GPIO_QSPI_SCLK_LEVEL_LOW :
bits : 8 - 8 (1 bit)
access : read-write

GPIO_QSPI_SCLK_LEVEL_HIGH :
bits : 9 - 9 (1 bit)
access : read-write

GPIO_QSPI_SCLK_EDGE_LOW :
bits : 10 - 10 (1 bit)
access : read-write

GPIO_QSPI_SCLK_EDGE_HIGH :
bits : 11 - 11 (1 bit)
access : read-write

GPIO_QSPI_SS_LEVEL_LOW :
bits : 12 - 12 (1 bit)
access : read-write

GPIO_QSPI_SS_LEVEL_HIGH :
bits : 13 - 13 (1 bit)
access : read-write

GPIO_QSPI_SS_EDGE_LOW :
bits : 14 - 14 (1 bit)
access : read-write

GPIO_QSPI_SS_EDGE_HIGH :
bits : 15 - 15 (1 bit)
access : read-write

GPIO_QSPI_SD0_LEVEL_LOW :
bits : 16 - 16 (1 bit)
access : read-write

GPIO_QSPI_SD0_LEVEL_HIGH :
bits : 17 - 17 (1 bit)
access : read-write

GPIO_QSPI_SD0_EDGE_LOW :
bits : 18 - 18 (1 bit)
access : read-write

GPIO_QSPI_SD0_EDGE_HIGH :
bits : 19 - 19 (1 bit)
access : read-write

GPIO_QSPI_SD1_LEVEL_LOW :
bits : 20 - 20 (1 bit)
access : read-write

GPIO_QSPI_SD1_LEVEL_HIGH :
bits : 21 - 21 (1 bit)
access : read-write

GPIO_QSPI_SD1_EDGE_LOW :
bits : 22 - 22 (1 bit)
access : read-write

GPIO_QSPI_SD1_EDGE_HIGH :
bits : 23 - 23 (1 bit)
access : read-write

GPIO_QSPI_SD2_LEVEL_LOW :
bits : 24 - 24 (1 bit)
access : read-write

GPIO_QSPI_SD2_LEVEL_HIGH :
bits : 25 - 25 (1 bit)
access : read-write

GPIO_QSPI_SD2_EDGE_LOW :
bits : 26 - 26 (1 bit)
access : read-write

GPIO_QSPI_SD2_EDGE_HIGH :
bits : 27 - 27 (1 bit)
access : read-write

GPIO_QSPI_SD3_LEVEL_LOW :
bits : 28 - 28 (1 bit)
access : read-write

GPIO_QSPI_SD3_LEVEL_HIGH :
bits : 29 - 29 (1 bit)
access : read-write

GPIO_QSPI_SD3_EDGE_LOW :
bits : 30 - 30 (1 bit)
access : read-write

GPIO_QSPI_SD3_EDGE_HIGH :
bits : 31 - 31 (1 bit)
access : read-write


DORMANT_WAKE_INTF

Interrupt Force for dormant_wake
address_offset : 0x238 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DORMANT_WAKE_INTF DORMANT_WAKE_INTF read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 USBPHY_DP_LEVEL_LOW USBPHY_DP_LEVEL_HIGH USBPHY_DP_EDGE_LOW USBPHY_DP_EDGE_HIGH USBPHY_DM_LEVEL_LOW USBPHY_DM_LEVEL_HIGH USBPHY_DM_EDGE_LOW USBPHY_DM_EDGE_HIGH GPIO_QSPI_SCLK_LEVEL_LOW GPIO_QSPI_SCLK_LEVEL_HIGH GPIO_QSPI_SCLK_EDGE_LOW GPIO_QSPI_SCLK_EDGE_HIGH GPIO_QSPI_SS_LEVEL_LOW GPIO_QSPI_SS_LEVEL_HIGH GPIO_QSPI_SS_EDGE_LOW GPIO_QSPI_SS_EDGE_HIGH GPIO_QSPI_SD0_LEVEL_LOW GPIO_QSPI_SD0_LEVEL_HIGH GPIO_QSPI_SD0_EDGE_LOW GPIO_QSPI_SD0_EDGE_HIGH GPIO_QSPI_SD1_LEVEL_LOW GPIO_QSPI_SD1_LEVEL_HIGH GPIO_QSPI_SD1_EDGE_LOW GPIO_QSPI_SD1_EDGE_HIGH GPIO_QSPI_SD2_LEVEL_LOW GPIO_QSPI_SD2_LEVEL_HIGH GPIO_QSPI_SD2_EDGE_LOW GPIO_QSPI_SD2_EDGE_HIGH GPIO_QSPI_SD3_LEVEL_LOW GPIO_QSPI_SD3_LEVEL_HIGH GPIO_QSPI_SD3_EDGE_LOW GPIO_QSPI_SD3_EDGE_HIGH

USBPHY_DP_LEVEL_LOW :
bits : 0 - 0 (1 bit)
access : read-write

USBPHY_DP_LEVEL_HIGH :
bits : 1 - 1 (1 bit)
access : read-write

USBPHY_DP_EDGE_LOW :
bits : 2 - 2 (1 bit)
access : read-write

USBPHY_DP_EDGE_HIGH :
bits : 3 - 3 (1 bit)
access : read-write

USBPHY_DM_LEVEL_LOW :
bits : 4 - 4 (1 bit)
access : read-write

USBPHY_DM_LEVEL_HIGH :
bits : 5 - 5 (1 bit)
access : read-write

USBPHY_DM_EDGE_LOW :
bits : 6 - 6 (1 bit)
access : read-write

USBPHY_DM_EDGE_HIGH :
bits : 7 - 7 (1 bit)
access : read-write

GPIO_QSPI_SCLK_LEVEL_LOW :
bits : 8 - 8 (1 bit)
access : read-write

GPIO_QSPI_SCLK_LEVEL_HIGH :
bits : 9 - 9 (1 bit)
access : read-write

GPIO_QSPI_SCLK_EDGE_LOW :
bits : 10 - 10 (1 bit)
access : read-write

GPIO_QSPI_SCLK_EDGE_HIGH :
bits : 11 - 11 (1 bit)
access : read-write

GPIO_QSPI_SS_LEVEL_LOW :
bits : 12 - 12 (1 bit)
access : read-write

GPIO_QSPI_SS_LEVEL_HIGH :
bits : 13 - 13 (1 bit)
access : read-write

GPIO_QSPI_SS_EDGE_LOW :
bits : 14 - 14 (1 bit)
access : read-write

GPIO_QSPI_SS_EDGE_HIGH :
bits : 15 - 15 (1 bit)
access : read-write

GPIO_QSPI_SD0_LEVEL_LOW :
bits : 16 - 16 (1 bit)
access : read-write

GPIO_QSPI_SD0_LEVEL_HIGH :
bits : 17 - 17 (1 bit)
access : read-write

GPIO_QSPI_SD0_EDGE_LOW :
bits : 18 - 18 (1 bit)
access : read-write

GPIO_QSPI_SD0_EDGE_HIGH :
bits : 19 - 19 (1 bit)
access : read-write

GPIO_QSPI_SD1_LEVEL_LOW :
bits : 20 - 20 (1 bit)
access : read-write

GPIO_QSPI_SD1_LEVEL_HIGH :
bits : 21 - 21 (1 bit)
access : read-write

GPIO_QSPI_SD1_EDGE_LOW :
bits : 22 - 22 (1 bit)
access : read-write

GPIO_QSPI_SD1_EDGE_HIGH :
bits : 23 - 23 (1 bit)
access : read-write

GPIO_QSPI_SD2_LEVEL_LOW :
bits : 24 - 24 (1 bit)
access : read-write

GPIO_QSPI_SD2_LEVEL_HIGH :
bits : 25 - 25 (1 bit)
access : read-write

GPIO_QSPI_SD2_EDGE_LOW :
bits : 26 - 26 (1 bit)
access : read-write

GPIO_QSPI_SD2_EDGE_HIGH :
bits : 27 - 27 (1 bit)
access : read-write

GPIO_QSPI_SD3_LEVEL_LOW :
bits : 28 - 28 (1 bit)
access : read-write

GPIO_QSPI_SD3_LEVEL_HIGH :
bits : 29 - 29 (1 bit)
access : read-write

GPIO_QSPI_SD3_EDGE_LOW :
bits : 30 - 30 (1 bit)
access : read-write

GPIO_QSPI_SD3_EDGE_HIGH :
bits : 31 - 31 (1 bit)
access : read-write


DORMANT_WAKE_INTS

Interrupt status after masking & forcing for dormant_wake
address_offset : 0x23C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DORMANT_WAKE_INTS DORMANT_WAKE_INTS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 USBPHY_DP_LEVEL_LOW USBPHY_DP_LEVEL_HIGH USBPHY_DP_EDGE_LOW USBPHY_DP_EDGE_HIGH USBPHY_DM_LEVEL_LOW USBPHY_DM_LEVEL_HIGH USBPHY_DM_EDGE_LOW USBPHY_DM_EDGE_HIGH GPIO_QSPI_SCLK_LEVEL_LOW GPIO_QSPI_SCLK_LEVEL_HIGH GPIO_QSPI_SCLK_EDGE_LOW GPIO_QSPI_SCLK_EDGE_HIGH GPIO_QSPI_SS_LEVEL_LOW GPIO_QSPI_SS_LEVEL_HIGH GPIO_QSPI_SS_EDGE_LOW GPIO_QSPI_SS_EDGE_HIGH GPIO_QSPI_SD0_LEVEL_LOW GPIO_QSPI_SD0_LEVEL_HIGH GPIO_QSPI_SD0_EDGE_LOW GPIO_QSPI_SD0_EDGE_HIGH GPIO_QSPI_SD1_LEVEL_LOW GPIO_QSPI_SD1_LEVEL_HIGH GPIO_QSPI_SD1_EDGE_LOW GPIO_QSPI_SD1_EDGE_HIGH GPIO_QSPI_SD2_LEVEL_LOW GPIO_QSPI_SD2_LEVEL_HIGH GPIO_QSPI_SD2_EDGE_LOW GPIO_QSPI_SD2_EDGE_HIGH GPIO_QSPI_SD3_LEVEL_LOW GPIO_QSPI_SD3_LEVEL_HIGH GPIO_QSPI_SD3_EDGE_LOW GPIO_QSPI_SD3_EDGE_HIGH

USBPHY_DP_LEVEL_LOW :
bits : 0 - 0 (1 bit)
access : read-only

USBPHY_DP_LEVEL_HIGH :
bits : 1 - 1 (1 bit)
access : read-only

USBPHY_DP_EDGE_LOW :
bits : 2 - 2 (1 bit)
access : read-only

USBPHY_DP_EDGE_HIGH :
bits : 3 - 3 (1 bit)
access : read-only

USBPHY_DM_LEVEL_LOW :
bits : 4 - 4 (1 bit)
access : read-only

USBPHY_DM_LEVEL_HIGH :
bits : 5 - 5 (1 bit)
access : read-only

USBPHY_DM_EDGE_LOW :
bits : 6 - 6 (1 bit)
access : read-only

USBPHY_DM_EDGE_HIGH :
bits : 7 - 7 (1 bit)
access : read-only

GPIO_QSPI_SCLK_LEVEL_LOW :
bits : 8 - 8 (1 bit)
access : read-only

GPIO_QSPI_SCLK_LEVEL_HIGH :
bits : 9 - 9 (1 bit)
access : read-only

GPIO_QSPI_SCLK_EDGE_LOW :
bits : 10 - 10 (1 bit)
access : read-only

GPIO_QSPI_SCLK_EDGE_HIGH :
bits : 11 - 11 (1 bit)
access : read-only

GPIO_QSPI_SS_LEVEL_LOW :
bits : 12 - 12 (1 bit)
access : read-only

GPIO_QSPI_SS_LEVEL_HIGH :
bits : 13 - 13 (1 bit)
access : read-only

GPIO_QSPI_SS_EDGE_LOW :
bits : 14 - 14 (1 bit)
access : read-only

GPIO_QSPI_SS_EDGE_HIGH :
bits : 15 - 15 (1 bit)
access : read-only

GPIO_QSPI_SD0_LEVEL_LOW :
bits : 16 - 16 (1 bit)
access : read-only

GPIO_QSPI_SD0_LEVEL_HIGH :
bits : 17 - 17 (1 bit)
access : read-only

GPIO_QSPI_SD0_EDGE_LOW :
bits : 18 - 18 (1 bit)
access : read-only

GPIO_QSPI_SD0_EDGE_HIGH :
bits : 19 - 19 (1 bit)
access : read-only

GPIO_QSPI_SD1_LEVEL_LOW :
bits : 20 - 20 (1 bit)
access : read-only

GPIO_QSPI_SD1_LEVEL_HIGH :
bits : 21 - 21 (1 bit)
access : read-only

GPIO_QSPI_SD1_EDGE_LOW :
bits : 22 - 22 (1 bit)
access : read-only

GPIO_QSPI_SD1_EDGE_HIGH :
bits : 23 - 23 (1 bit)
access : read-only

GPIO_QSPI_SD2_LEVEL_LOW :
bits : 24 - 24 (1 bit)
access : read-only

GPIO_QSPI_SD2_LEVEL_HIGH :
bits : 25 - 25 (1 bit)
access : read-only

GPIO_QSPI_SD2_EDGE_LOW :
bits : 26 - 26 (1 bit)
access : read-only

GPIO_QSPI_SD2_EDGE_HIGH :
bits : 27 - 27 (1 bit)
access : read-only

GPIO_QSPI_SD3_LEVEL_LOW :
bits : 28 - 28 (1 bit)
access : read-only

GPIO_QSPI_SD3_LEVEL_HIGH :
bits : 29 - 29 (1 bit)
access : read-only

GPIO_QSPI_SD3_EDGE_LOW :
bits : 30 - 30 (1 bit)
access : read-only

GPIO_QSPI_SD3_EDGE_HIGH :
bits : 31 - 31 (1 bit)
access : read-only


GPIO_QSPI_SD0_CTRL


address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GPIO_QSPI_SD0_CTRL GPIO_QSPI_SD0_CTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FUNCSEL OUTOVER OEOVER INOVER IRQOVER

FUNCSEL : 0-31 -> selects pin function according to the gpio table 31 == NULL
bits : 0 - 4 (5 bit)
access : read-write

Enumeration:

0 : xip_sd0


2 : uart0_tx


3 : i2c0_sda


5 : siob_proc_60


31 : null


End of enumeration elements list.

OUTOVER :
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : NORMAL

drive output from peripheral signal selected by funcsel

1 : INVERT

drive output from inverse of peripheral signal selected by funcsel

2 : LOW

drive output low

3 : HIGH

drive output high

End of enumeration elements list.

OEOVER :
bits : 14 - 15 (2 bit)
access : read-write

Enumeration:

0 : NORMAL

drive output enable from peripheral signal selected by funcsel

1 : INVERT

drive output enable from inverse of peripheral signal selected by funcsel

2 : DISABLE

disable output

3 : ENABLE

enable output

End of enumeration elements list.

INOVER :
bits : 16 - 17 (2 bit)
access : read-write

Enumeration:

0 : NORMAL

don't invert the peri input

1 : INVERT

invert the peri input

2 : LOW

drive peri input low

3 : HIGH

drive peri input high

End of enumeration elements list.

IRQOVER :
bits : 28 - 29 (2 bit)
access : read-write

Enumeration:

0 : NORMAL

don't invert the interrupt

1 : INVERT

invert the interrupt

2 : LOW

drive interrupt low

3 : HIGH

drive interrupt high

End of enumeration elements list.


GPIO_QSPI_SD1_STATUS


address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GPIO_QSPI_SD1_STATUS GPIO_QSPI_SD1_STATUS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OUTTOPAD OETOPAD INFROMPAD IRQTOPROC

OUTTOPAD : output signal to pad after register override is applied
bits : 9 - 9 (1 bit)
access : read-only

OETOPAD : output enable to pad after register override is applied
bits : 13 - 13 (1 bit)
access : read-only

INFROMPAD : input signal from pad, before filtering and override are applied
bits : 17 - 17 (1 bit)
access : read-only

IRQTOPROC : interrupt to processors, after override is applied
bits : 26 - 26 (1 bit)
access : read-only


GPIO_QSPI_SD1_CTRL


address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GPIO_QSPI_SD1_CTRL GPIO_QSPI_SD1_CTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FUNCSEL OUTOVER OEOVER INOVER IRQOVER

FUNCSEL : 0-31 -> selects pin function according to the gpio table 31 == NULL
bits : 0 - 4 (5 bit)
access : read-write

Enumeration:

0 : xip_sd1


2 : uart0_rx


3 : i2c0_scl


5 : siob_proc_61


31 : null


End of enumeration elements list.

OUTOVER :
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : NORMAL

drive output from peripheral signal selected by funcsel

1 : INVERT

drive output from inverse of peripheral signal selected by funcsel

2 : LOW

drive output low

3 : HIGH

drive output high

End of enumeration elements list.

OEOVER :
bits : 14 - 15 (2 bit)
access : read-write

Enumeration:

0 : NORMAL

drive output enable from peripheral signal selected by funcsel

1 : INVERT

drive output enable from inverse of peripheral signal selected by funcsel

2 : DISABLE

disable output

3 : ENABLE

enable output

End of enumeration elements list.

INOVER :
bits : 16 - 17 (2 bit)
access : read-write

Enumeration:

0 : NORMAL

don't invert the peri input

1 : INVERT

invert the peri input

2 : LOW

drive peri input low

3 : HIGH

drive peri input high

End of enumeration elements list.

IRQOVER :
bits : 28 - 29 (2 bit)
access : read-write

Enumeration:

0 : NORMAL

don't invert the interrupt

1 : INVERT

invert the interrupt

2 : LOW

drive interrupt low

3 : HIGH

drive interrupt high

End of enumeration elements list.


GPIO_QSPI_SD2_STATUS


address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GPIO_QSPI_SD2_STATUS GPIO_QSPI_SD2_STATUS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OUTTOPAD OETOPAD INFROMPAD IRQTOPROC

OUTTOPAD : output signal to pad after register override is applied
bits : 9 - 9 (1 bit)
access : read-only

OETOPAD : output enable to pad after register override is applied
bits : 13 - 13 (1 bit)
access : read-only

INFROMPAD : input signal from pad, before filtering and override are applied
bits : 17 - 17 (1 bit)
access : read-only

IRQTOPROC : interrupt to processors, after override is applied
bits : 26 - 26 (1 bit)
access : read-only


GPIO_QSPI_SD2_CTRL


address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GPIO_QSPI_SD2_CTRL GPIO_QSPI_SD2_CTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FUNCSEL OUTOVER OEOVER INOVER IRQOVER

FUNCSEL : 0-31 -> selects pin function according to the gpio table 31 == NULL
bits : 0 - 4 (5 bit)
access : read-write

Enumeration:

0 : xip_sd2


2 : uart0_cts


3 : i2c1_sda


5 : siob_proc_62


11 : uart0_tx


31 : null


End of enumeration elements list.

OUTOVER :
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : NORMAL

drive output from peripheral signal selected by funcsel

1 : INVERT

drive output from inverse of peripheral signal selected by funcsel

2 : LOW

drive output low

3 : HIGH

drive output high

End of enumeration elements list.

OEOVER :
bits : 14 - 15 (2 bit)
access : read-write

Enumeration:

0 : NORMAL

drive output enable from peripheral signal selected by funcsel

1 : INVERT

drive output enable from inverse of peripheral signal selected by funcsel

2 : DISABLE

disable output

3 : ENABLE

enable output

End of enumeration elements list.

INOVER :
bits : 16 - 17 (2 bit)
access : read-write

Enumeration:

0 : NORMAL

don't invert the peri input

1 : INVERT

invert the peri input

2 : LOW

drive peri input low

3 : HIGH

drive peri input high

End of enumeration elements list.

IRQOVER :
bits : 28 - 29 (2 bit)
access : read-write

Enumeration:

0 : NORMAL

don't invert the interrupt

1 : INVERT

invert the interrupt

2 : LOW

drive interrupt low

3 : HIGH

drive interrupt high

End of enumeration elements list.


GPIO_QSPI_SD3_STATUS


address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GPIO_QSPI_SD3_STATUS GPIO_QSPI_SD3_STATUS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OUTTOPAD OETOPAD INFROMPAD IRQTOPROC

OUTTOPAD : output signal to pad after register override is applied
bits : 9 - 9 (1 bit)
access : read-only

OETOPAD : output enable to pad after register override is applied
bits : 13 - 13 (1 bit)
access : read-only

INFROMPAD : input signal from pad, before filtering and override are applied
bits : 17 - 17 (1 bit)
access : read-only

IRQTOPROC : interrupt to processors, after override is applied
bits : 26 - 26 (1 bit)
access : read-only


GPIO_QSPI_SD3_CTRL


address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GPIO_QSPI_SD3_CTRL GPIO_QSPI_SD3_CTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FUNCSEL OUTOVER OEOVER INOVER IRQOVER

FUNCSEL : 0-31 -> selects pin function according to the gpio table 31 == NULL
bits : 0 - 4 (5 bit)
access : read-write

Enumeration:

0 : xip_sd3


2 : uart0_rts


3 : i2c1_scl


5 : siob_proc_63


11 : uart0_rx


31 : null


End of enumeration elements list.

OUTOVER :
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : NORMAL

drive output from peripheral signal selected by funcsel

1 : INVERT

drive output from inverse of peripheral signal selected by funcsel

2 : LOW

drive output low

3 : HIGH

drive output high

End of enumeration elements list.

OEOVER :
bits : 14 - 15 (2 bit)
access : read-write

Enumeration:

0 : NORMAL

drive output enable from peripheral signal selected by funcsel

1 : INVERT

drive output enable from inverse of peripheral signal selected by funcsel

2 : DISABLE

disable output

3 : ENABLE

enable output

End of enumeration elements list.

INOVER :
bits : 16 - 17 (2 bit)
access : read-write

Enumeration:

0 : NORMAL

don't invert the peri input

1 : INVERT

invert the peri input

2 : LOW

drive peri input low

3 : HIGH

drive peri input high

End of enumeration elements list.

IRQOVER :
bits : 28 - 29 (2 bit)
access : read-write

Enumeration:

0 : NORMAL

don't invert the interrupt

1 : INVERT

invert the interrupt

2 : LOW

drive interrupt low

3 : HIGH

drive interrupt high

End of enumeration elements list.


USBPHY_DP_CTRL


address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USBPHY_DP_CTRL USBPHY_DP_CTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FUNCSEL OUTOVER OEOVER INOVER IRQOVER

FUNCSEL : 0-31 -> selects pin function according to the gpio table 31 == NULL
bits : 0 - 4 (5 bit)
access : read-write

Enumeration:

2 : uart1_tx


3 : i2c0_sda


5 : siob_proc_56


31 : null


End of enumeration elements list.

OUTOVER :
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : NORMAL

drive output from peripheral signal selected by funcsel

1 : INVERT

drive output from inverse of peripheral signal selected by funcsel

2 : LOW

drive output low

3 : HIGH

drive output high

End of enumeration elements list.

OEOVER :
bits : 14 - 15 (2 bit)
access : read-write

Enumeration:

0 : NORMAL

drive output enable from peripheral signal selected by funcsel

1 : INVERT

drive output enable from inverse of peripheral signal selected by funcsel

2 : DISABLE

disable output

3 : ENABLE

enable output

End of enumeration elements list.

INOVER :
bits : 16 - 17 (2 bit)
access : read-write

Enumeration:

0 : NORMAL

don't invert the peri input

1 : INVERT

invert the peri input

2 : LOW

drive peri input low

3 : HIGH

drive peri input high

End of enumeration elements list.

IRQOVER :
bits : 28 - 29 (2 bit)
access : read-write

Enumeration:

0 : NORMAL

don't invert the interrupt

1 : INVERT

invert the interrupt

2 : LOW

drive interrupt low

3 : HIGH

drive interrupt high

End of enumeration elements list.


USBPHY_DM_STATUS


address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USBPHY_DM_STATUS USBPHY_DM_STATUS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OUTTOPAD OETOPAD INFROMPAD IRQTOPROC

OUTTOPAD : output signal to pad after register override is applied
bits : 9 - 9 (1 bit)
access : read-only

OETOPAD : output enable to pad after register override is applied
bits : 13 - 13 (1 bit)
access : read-only

INFROMPAD : input signal from pad, before filtering and override are applied
bits : 17 - 17 (1 bit)
access : read-only

IRQTOPROC : interrupt to processors, after override is applied
bits : 26 - 26 (1 bit)
access : read-only


USBPHY_DM_CTRL


address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USBPHY_DM_CTRL USBPHY_DM_CTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FUNCSEL OUTOVER OEOVER INOVER IRQOVER

FUNCSEL : 0-31 -> selects pin function according to the gpio table 31 == NULL
bits : 0 - 4 (5 bit)
access : read-write

Enumeration:

2 : uart1_rx


3 : i2c0_scl


5 : siob_proc_57


31 : null


End of enumeration elements list.

OUTOVER :
bits : 12 - 13 (2 bit)
access : read-write

Enumeration:

0 : NORMAL

drive output from peripheral signal selected by funcsel

1 : INVERT

drive output from inverse of peripheral signal selected by funcsel

2 : LOW

drive output low

3 : HIGH

drive output high

End of enumeration elements list.

OEOVER :
bits : 14 - 15 (2 bit)
access : read-write

Enumeration:

0 : NORMAL

drive output enable from peripheral signal selected by funcsel

1 : INVERT

drive output enable from inverse of peripheral signal selected by funcsel

2 : DISABLE

disable output

3 : ENABLE

enable output

End of enumeration elements list.

INOVER :
bits : 16 - 17 (2 bit)
access : read-write

Enumeration:

0 : NORMAL

don't invert the peri input

1 : INVERT

invert the peri input

2 : LOW

drive peri input low

3 : HIGH

drive peri input high

End of enumeration elements list.

IRQOVER :
bits : 28 - 29 (2 bit)
access : read-write

Enumeration:

0 : NORMAL

don't invert the interrupt

1 : INVERT

invert the interrupt

2 : LOW

drive interrupt low

3 : HIGH

drive interrupt high

End of enumeration elements list.



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