SYSINFO

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x18 byte (0x0)
mem_usage : registers
protection :

Registers

CHIP_ID

GITREF_RP2350

PACKAGE_SEL

PLATFORM


CHIP_ID

JEDEC JEP-106 compliant chip identifier.
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHIP_ID CHIP_ID read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 STOP_BIT MANUFACTURER PART REVISION

STOP_BIT :
bits : 0 - 0 (1 bit)
access : read-only

MANUFACTURER :
bits : 1 - 11 (11 bit)
access : read-only

PART :
bits : 12 - 27 (16 bit)
access : read-only

REVISION :
bits : 28 - 31 (4 bit)
access : read-only


GITREF_RP2350

Git hash of the chip source. Used to identify chip version.
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GITREF_RP2350 GITREF_RP2350 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 GITREF_RP2350

GITREF_RP2350 :
bits : 0 - 31 (32 bit)
access : read-only


PACKAGE_SEL


address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PACKAGE_SEL PACKAGE_SEL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PACKAGE_SEL

PACKAGE_SEL :
bits : 0 - 0 (1 bit)
access : read-only


PLATFORM

Platform register. Allows software to know what environment it is running in during pre-production development. Post-production, the PLATFORM is always ASIC, non-SIM.
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PLATFORM PLATFORM read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FPGA ASIC HDLSIM BATCHSIM GATESIM

FPGA :
bits : 0 - 0 (1 bit)
access : read-only

ASIC :
bits : 1 - 1 (1 bit)
access : read-only

HDLSIM :
bits : 2 - 2 (1 bit)
access : read-only

BATCHSIM :
bits : 3 - 3 (1 bit)
access : read-only

GATESIM :
bits : 4 - 4 (1 bit)
access : read-only



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