CSR

SUM2

SUM3

SUM4

SUM5

SUM6

SUM7

WDATA

SUM0

SUM1

START : Write 1 to prepare the SHA-256 core for a new checksum. The SUMx registers are initialised to the proper values (fractional bits of square roots of first 8 primes) and internal counters are cleared. This immediately forces WDATA_RDY and SUM_VLD high. START must be written before initiating a DMA transfer to the SHA-256 core, because the core will always request 16 transfers at a time (1 512-bit block). Additionally, the DMA channel should be configured for a multiple of 16 32-bit transfers.
bits : 0 - 0 (1 bit)
access : write-only

WDATA_RDY : If 1, the SHA-256 core is ready to accept more data through the WDATA register. After writing 16 words, this flag will go low for 57 cycles whilst the core completes its digest.
bits : 1 - 1 (1 bit)
access : read-only

SUM_VLD : If 1, the SHA-256 checksum presented in registers SUM0 through SUM7 is currently valid. Goes low when WDATA is first written, then returns high once 16 words have been written and the digest of the current 512-bit block has subsequently completed.
bits : 2 - 2 (1 bit)
access : read-only

ERR_WDATA_NOT_RDY : Set when a write occurs whilst the SHA-256 core is not ready for data (WDATA_RDY is low). Write one to clear.
bits : 4 - 4 (1 bit)
access : read-write

DMA_SIZE : Configure DREQ logic for the correct DMA data size. Must be configured before the DMA channel is triggered. The SHA-256 core's DREQ logic requests one entire block of data at once, since there is no FIFO, and data goes straight into the core's message schedule and digest hardware. Therefore, when transferring data with DMA, CSR_DMA_SIZE must be configured in advance so that the correct number of transfers can be requested per block.
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

End of enumeration elements list.

BSWAP : Enable byte swapping of 32-bit values at the point they are committed to the SHA message scheduler. This block's bus interface assembles byte/halfword data into message words in little-endian order, so that DMAing the same buffer with different transfer sizes always gives the same result on a little-endian system like RP2350. However, when marshalling bytes into blocks, SHA expects that the first byte is the *most significant* in each message word. To resolve this, once the bus interface has accumulated 32 bits of data (either a word write, two halfword writes in little-endian order, or four byte writes in little-endian order) the final value can be byte-swapped before passing to the actual SHA core. This feature is enabled by default because using the SHA core to checksum byte buffers is expected to be more common than having preformatted SHA message words lying around.
bits : 12 - 12 (1 bit)
access : read-write

SUM2 :
bits : 0 - 31 (32 bit)
access : read-only

SUM3 :
bits : 0 - 31 (32 bit)
access : read-only

SUM4 :
bits : 0 - 31 (32 bit)
access : read-only

SUM5 :
bits : 0 - 31 (32 bit)
access : read-only

SUM6 :
bits : 0 - 31 (32 bit)
access : read-only

SUM7 :
bits : 0 - 31 (32 bit)
access : read-only

WDATA : After pulsing START and writing 16 words of data to this register, WDATA_RDY will go low and the SHA-256 core will complete the digest of the current 512-bit block. Software is responsible for ensuring the data is correctly padded and terminated to a whole number of 512-bit blocks. After this, WDATA_RDY will return high, and more data can be written (if any). This register supports word, halfword and byte writes, so that DMA from non-word-aligned buffers can be supported. The total amount of data per block remains the same (16 words, 32 halfwords or 64 bytes) and byte/halfword transfers must not be mixed within a block.
bits : 0 - 31 (32 bit)
access : write-only

SUM0 :
bits : 0 - 31 (32 bit)
access : read-only

SUM1 :
bits : 0 - 31 (32 bit)
access : read-only