EPPB

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0xC byte (0x0)
mem_usage : registers
protection :

Registers

NMI_MASK0

NMI_MASK1

SLEEPCTRL


NMI_MASK0

NMI mask for IRQs 0 through 31. This register is core-local, and is reset by a processor warm reset.
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NMI_MASK0 NMI_MASK0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NMI_MASK0

NMI_MASK0 :
bits : 0 - 31 (32 bit)
access : read-write


NMI_MASK1

NMI mask for IRQs 0 though 51. This register is core-local, and is reset by a processor warm reset.
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NMI_MASK1 NMI_MASK1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NMI_MASK1

NMI_MASK1 :
bits : 0 - 19 (20 bit)
access : read-write


SLEEPCTRL

Nonstandard sleep control register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SLEEPCTRL SLEEPCTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LIGHT_SLEEP WICENREQ WICENACK

LIGHT_SLEEP : By default, any processor sleep will deassert the system-level clock request. Reenabling the clocks incurs 5 cycles of additional latency on wakeup. Setting LIGHT_SLEEP to 1 keeps the clock request asserted during a normal sleep (Arm SCR.SLEEPDEEP = 0), for faster wakeup. Processor deep sleep (Arm SCR.SLEEPDEEP = 1) is not affected, and will always deassert the system-level clock request.
bits : 0 - 0 (1 bit)
access : read-write

WICENREQ : Request that the next processor deep sleep is a WIC sleep. After setting this bit, before sleeping, poll WICENACK to ensure the processor interrupt controller has acknowledged the change.
bits : 1 - 1 (1 bit)
access : read-write

WICENACK : Status signal from the processor's interrupt controller. Changes to WICENREQ are eventually reflected in WICENACK.
bits : 2 - 2 (1 bit)
access : read-only



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