Embeetle, an IDE designed from scratch for embedded software developers.address_offset : 0x0 Bytes (0x0)
size : 0x43000 byte (0x0)
mem_usage : registers
protection :
Provides the interface for generating Instrumentation packets
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
STIMULUS : Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated.
bits : 0 - 31 (32 bit)
access : read-write
Provides the interface for generating Instrumentation packets
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
STIMULUS : Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated.
bits : 0 - 31 (32 bit)
access : read-write
Provides configuration and status information for the DWT unit, and used to control features of the unit
address_offset : 0x1000 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CYCCNTENA : Enables CYCCNT
bits : 0 - 0 (1 bit)
access : read-write
POSTPRESET : Reload value for the POSTCNT counter
bits : 1 - 4 (4 bit)
access : read-write
POSTINIT : Initial value for the POSTCNT counter
bits : 5 - 8 (4 bit)
access : read-write
CYCTAP : Selects the position of the POSTCNT tap on the CYCCNT counter
bits : 9 - 9 (1 bit)
access : read-write
SYNCTAP : Selects the position of the synchronization packet counter tap on the CYCCNT counter. This determines the Synchronization packet rate
bits : 10 - 11 (2 bit)
access : read-write
PCSAMPLENA : Enables use of POSTCNT counter as a timer for Periodic PC Sample packet generation
bits : 12 - 12 (1 bit)
access : read-write
EXTTRCENA : Enables generation of Exception Trace packets
bits : 16 - 16 (1 bit)
access : read-write
CPIEVTENA : Enables DWT_CPICNT counter
bits : 17 - 17 (1 bit)
access : read-write
EXCEVTENA : Enables DWT_EXCCNT counter
bits : 18 - 18 (1 bit)
access : read-write
SLEEPEVTENA : Enable DWT_SLEEPCNT counter
bits : 19 - 19 (1 bit)
access : read-write
LSUEVTENA : Enables DWT_LSUCNT counter
bits : 20 - 20 (1 bit)
access : read-write
FOLDEVTENA : Enables DWT_FOLDCNT counter
bits : 21 - 21 (1 bit)
access : read-write
CYCEVTENA : Enables Event Counter packet generation on POSTCNT underflow
bits : 22 - 22 (1 bit)
access : read-write
CYCDISS : Controls whether the cycle counter is disabled in Secure state
bits : 23 - 23 (1 bit)
access : read-write
NOPRFCNT : Indicates whether the implementation does not include the profiling counters
bits : 24 - 24 (1 bit)
access : read-only
NOCYCCNT : Indicates whether the implementation does not include a cycle counter
bits : 25 - 25 (1 bit)
access : read-only
NOEXTTRIG : Reserved, RAZ
bits : 26 - 26 (1 bit)
access : read-only
NOTRCPKT : Indicates whether the implementation does not support trace
bits : 27 - 27 (1 bit)
access : read-only
NUMCOMP : Number of DWT comparators implemented
bits : 28 - 31 (4 bit)
access : read-only
Shows or sets the value of the processor cycle counter, CYCCNT
address_offset : 0x1004 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CYCCNT : Increments one on each processor clock cycle when DWT_CTRL.CYCCNTENA == 1 and DEMCR.TRCENA == 1. On overflow, CYCCNT wraps to zero
bits : 0 - 31 (32 bit)
access : read-write
Counts the total cycles spent in exception processing
address_offset : 0x100C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EXCCNT : Counts one on each cycle when all of the following are true: - DWT_CTRL.EXCEVTENA == 1 and DEMCR.TRCENA == 1. - No instruction is executed, see DWT_CPICNT. - An exception-entry or exception-exit related operation is in progress. - Either SecureNoninvasiveDebugAllowed() == TRUE, or NS-Req for the operation is set to Non-secure and NoninvasiveDebugAllowed() == TRUE.
bits : 0 - 7 (8 bit)
access : read-write
Increments on the additional cycles required to execute all load or store instructions
address_offset : 0x1014 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LSUCNT : Counts one on each cycle when all of the following are true: - DWT_CTRL.LSUEVTENA == 1 and DEMCR.TRCENA == 1. - No instruction is executed, see DWT_CPICNT. - No exception-entry or exception-exit operation is in progress, see DWT_EXCCNT. - A load-store operation is in progress. - Either SecureNoninvasiveDebugAllowed() == TRUE, or NS-Req for the operation is set to Non-secure and NoninvasiveDebugAllowed() == TRUE.
bits : 0 - 7 (8 bit)
access : read-write
Increments on the additional cycles required to execute all load or store instructions
address_offset : 0x1018 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FOLDCNT : Counts on each cycle when all of the following are true: - DWT_CTRL.FOLDEVTENA == 1 and DEMCR.TRCENA == 1. - At least two instructions are executed, see DWT_CPICNT. - Either SecureNoninvasiveDebugAllowed() == TRUE, or the PE is in Non-secure state and NoninvasiveDebugAllowed() == TRUE. The counter is incremented by the number of instructions executed, minus one
bits : 0 - 7 (8 bit)
access : read-write
Provides a reference value for use by watchpoint comparator 0
address_offset : 0x1020 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DWT_COMP0 :
bits : 0 - 31 (32 bit)
access : read-write
Controls the operation of watchpoint comparator 0
address_offset : 0x1028 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MATCH : Controls the type of match generated by this comparator
bits : 0 - 3 (4 bit)
access : read-write
ACTION : Defines the action on a match. This field is ignored and the comparator generates no actions if it is disabled by MATCH
bits : 4 - 5 (2 bit)
access : read-write
DATAVSIZE : Defines the size of the object being watched for by Data Value and Data Address comparators
bits : 10 - 11 (2 bit)
access : read-write
MATCHED : Set to 1 when the comparator matches
bits : 24 - 24 (1 bit)
access : read-only
ID : Identifies the capabilities for MATCH for comparator *n
bits : 27 - 31 (5 bit)
access : read-only
Provides a reference value for use by watchpoint comparator 1
address_offset : 0x1030 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DWT_COMP1 :
bits : 0 - 31 (32 bit)
access : read-write
Controls the operation of watchpoint comparator 1
address_offset : 0x1038 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MATCH : Controls the type of match generated by this comparator
bits : 0 - 3 (4 bit)
access : read-write
ACTION : Defines the action on a match. This field is ignored and the comparator generates no actions if it is disabled by MATCH
bits : 4 - 5 (2 bit)
access : read-write
DATAVSIZE : Defines the size of the object being watched for by Data Value and Data Address comparators
bits : 10 - 11 (2 bit)
access : read-write
MATCHED : Set to 1 when the comparator matches
bits : 24 - 24 (1 bit)
access : read-only
ID : Identifies the capabilities for MATCH for comparator *n
bits : 27 - 31 (5 bit)
access : read-only
Provides a reference value for use by watchpoint comparator 2
address_offset : 0x1040 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DWT_COMP2 :
bits : 0 - 31 (32 bit)
access : read-write
Controls the operation of watchpoint comparator 2
address_offset : 0x1048 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MATCH : Controls the type of match generated by this comparator
bits : 0 - 3 (4 bit)
access : read-write
ACTION : Defines the action on a match. This field is ignored and the comparator generates no actions if it is disabled by MATCH
bits : 4 - 5 (2 bit)
access : read-write
DATAVSIZE : Defines the size of the object being watched for by Data Value and Data Address comparators
bits : 10 - 11 (2 bit)
access : read-write
MATCHED : Set to 1 when the comparator matches
bits : 24 - 24 (1 bit)
access : read-only
ID : Identifies the capabilities for MATCH for comparator *n
bits : 27 - 31 (5 bit)
access : read-only
Provides a reference value for use by watchpoint comparator 3
address_offset : 0x1050 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DWT_COMP3 :
bits : 0 - 31 (32 bit)
access : read-write
Controls the operation of watchpoint comparator 3
address_offset : 0x1058 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MATCH : Controls the type of match generated by this comparator
bits : 0 - 3 (4 bit)
access : read-write
ACTION : Defines the action on a match. This field is ignored and the comparator generates no actions if it is disabled by MATCH
bits : 4 - 5 (2 bit)
access : read-write
DATAVSIZE : Defines the size of the object being watched for by Data Value and Data Address comparators
bits : 10 - 11 (2 bit)
access : read-write
MATCHED : Set to 1 when the comparator matches
bits : 24 - 24 (1 bit)
access : read-only
ID : Identifies the capabilities for MATCH for comparator *n
bits : 27 - 31 (5 bit)
access : read-only
Provides the interface for generating Instrumentation packets
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
STIMULUS : Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated.
bits : 0 - 31 (32 bit)
access : read-write
Provides the interface for generating Instrumentation packets
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
STIMULUS : Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated.
bits : 0 - 31 (32 bit)
access : read-write
Provides the interface for generating Instrumentation packets
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
STIMULUS : Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated.
bits : 0 - 31 (32 bit)
access : read-write
Provides CoreSight discovery information for the DWT
address_offset : 0x1FBC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ARCHPART : Defines the architecture of the component
bits : 0 - 11 (12 bit)
access : read-only
ARCHVER : Defines the architecture version of the component
bits : 12 - 15 (4 bit)
access : read-only
REVISION : Defines the architecture revision of the component
bits : 16 - 19 (4 bit)
access : read-only
PRESENT : Defines that the DEVARCH register is present
bits : 20 - 20 (1 bit)
access : read-only
ARCHITECT : Defines the architect of the component. Bits [31:28] are the JEP106 continuation code (JEP106 bank ID, minus 1) and bits [27:21] are the JEP106 ID code.
bits : 21 - 31 (11 bit)
access : read-only
Provides CoreSight discovery information for the DWT
address_offset : 0x1FCC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MAJOR : Component major type
bits : 0 - 3 (4 bit)
access : read-only
SUB : Component sub-type
bits : 4 - 7 (4 bit)
access : read-only
Provides CoreSight discovery information for the DWT
address_offset : 0x1FD0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DES_2 : See CoreSight Architecture Specification
bits : 0 - 3 (4 bit)
access : read-only
SIZE : See CoreSight Architecture Specification
bits : 4 - 7 (4 bit)
access : read-only
Provides CoreSight discovery information for the DWT
address_offset : 0x1FD4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DWT_PIDR5 :
bits : 0 - 31 (32 bit)
access : read-write
Provides CoreSight discovery information for the DWT
address_offset : 0x1FD8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DWT_PIDR6 :
bits : 0 - 31 (32 bit)
access : read-write
Provides CoreSight discovery information for the DWT
address_offset : 0x1FDC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DWT_PIDR7 :
bits : 0 - 31 (32 bit)
access : read-write
Provides CoreSight discovery information for the DWT
address_offset : 0x1FE0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PART_0 : See CoreSight Architecture Specification
bits : 0 - 7 (8 bit)
access : read-only
Provides CoreSight discovery information for the DWT
address_offset : 0x1FE4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PART_1 : See CoreSight Architecture Specification
bits : 0 - 3 (4 bit)
access : read-only
DES_0 : See CoreSight Architecture Specification
bits : 4 - 7 (4 bit)
access : read-only
Provides CoreSight discovery information for the DWT
address_offset : 0x1FE8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DES_1 : See CoreSight Architecture Specification
bits : 0 - 2 (3 bit)
access : read-only
JEDEC : See CoreSight Architecture Specification
bits : 3 - 3 (1 bit)
access : read-only
REVISION : See CoreSight Architecture Specification
bits : 4 - 7 (4 bit)
access : read-only
Provides CoreSight discovery information for the DWT
address_offset : 0x1FEC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CMOD : See CoreSight Architecture Specification
bits : 0 - 3 (4 bit)
access : read-only
REVAND : See CoreSight Architecture Specification
bits : 4 - 7 (4 bit)
access : read-only
Provides CoreSight discovery information for the DWT
address_offset : 0x1FF0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRMBL_0 : See CoreSight Architecture Specification
bits : 0 - 7 (8 bit)
access : read-only
Provides CoreSight discovery information for the DWT
address_offset : 0x1FF4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRMBL_1 : See CoreSight Architecture Specification
bits : 0 - 3 (4 bit)
access : read-only
CLASS : See CoreSight Architecture Specification
bits : 4 - 7 (4 bit)
access : read-only
Provides CoreSight discovery information for the DWT
address_offset : 0x1FF8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRMBL_2 : See CoreSight Architecture Specification
bits : 0 - 7 (8 bit)
access : read-only
Provides CoreSight discovery information for the DWT
address_offset : 0x1FFC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRMBL_3 : See CoreSight Architecture Specification
bits : 0 - 7 (8 bit)
access : read-only
Provides the interface for generating Instrumentation packets
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
STIMULUS : Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated.
bits : 0 - 31 (32 bit)
access : read-write
Provides FPB implementation information, and the global enable for the FPB unit
address_offset : 0x2000 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ENABLE : Enables the FPB
bits : 0 - 0 (1 bit)
access : read-write
KEY : Writes to the FP_CTRL are ignored unless KEY is concurrently written to one
bits : 1 - 1 (1 bit)
access : read-write
NUM_CODE_7_4_ : Indicates the number of implemented instruction address comparators. Zero indicates no Instruction Address comparators are implemented. The Instruction Address comparators are numbered from 0 to NUM_CODE - 1
bits : 4 - 7 (4 bit)
access : read-only
NUM_LIT : Indicates the number of implemented literal address comparators. The Literal Address comparators are numbered from NUM_CODE to NUM_CODE + NUM_LIT - 1
bits : 8 - 11 (4 bit)
access : read-only
NUM_CODE_14_12_ : Indicates the number of implemented instruction address comparators. Zero indicates no Instruction Address comparators are implemented. The Instruction Address comparators are numbered from 0 to NUM_CODE - 1
bits : 12 - 14 (3 bit)
access : read-only
REV : Flash Patch and Breakpoint Unit architecture revision
bits : 28 - 31 (4 bit)
access : read-only
Indicates whether the implementation supports Flash Patch remap and, if it does, holds the target address for remap
address_offset : 0x2004 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
REMAP : Holds the bits[28:5] of the Flash Patch remap address
bits : 5 - 28 (24 bit)
access : read-only
RMPSPT : Indicates whether the FPB unit supports the Flash Patch remap function
bits : 29 - 29 (1 bit)
access : read-only
Holds an address for comparison. The effect of the match depends on the configuration of the FPB and whether the comparator is an instruction address comparator or a literal address comparator
address_offset : 0x2008 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BE : Selects between flashpatch and breakpoint functionality
bits : 0 - 0 (1 bit)
access : read-write
Holds an address for comparison. The effect of the match depends on the configuration of the FPB and whether the comparator is an instruction address comparator or a literal address comparator
address_offset : 0x200C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BE : Selects between flashpatch and breakpoint functionality
bits : 0 - 0 (1 bit)
access : read-write
Holds an address for comparison. The effect of the match depends on the configuration of the FPB and whether the comparator is an instruction address comparator or a literal address comparator
address_offset : 0x2010 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BE : Selects between flashpatch and breakpoint functionality
bits : 0 - 0 (1 bit)
access : read-write
Holds an address for comparison. The effect of the match depends on the configuration of the FPB and whether the comparator is an instruction address comparator or a literal address comparator
address_offset : 0x2014 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BE : Selects between flashpatch and breakpoint functionality
bits : 0 - 0 (1 bit)
access : read-write
Holds an address for comparison. The effect of the match depends on the configuration of the FPB and whether the comparator is an instruction address comparator or a literal address comparator
address_offset : 0x2018 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BE : Selects between flashpatch and breakpoint functionality
bits : 0 - 0 (1 bit)
access : read-write
Holds an address for comparison. The effect of the match depends on the configuration of the FPB and whether the comparator is an instruction address comparator or a literal address comparator
address_offset : 0x201C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BE : Selects between flashpatch and breakpoint functionality
bits : 0 - 0 (1 bit)
access : read-write
Holds an address for comparison. The effect of the match depends on the configuration of the FPB and whether the comparator is an instruction address comparator or a literal address comparator
address_offset : 0x2020 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BE : Selects between flashpatch and breakpoint functionality
bits : 0 - 0 (1 bit)
access : read-write
Holds an address for comparison. The effect of the match depends on the configuration of the FPB and whether the comparator is an instruction address comparator or a literal address comparator
address_offset : 0x2024 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BE : Selects between flashpatch and breakpoint functionality
bits : 0 - 0 (1 bit)
access : read-write
Provides the interface for generating Instrumentation packets
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
STIMULUS : Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated.
bits : 0 - 31 (32 bit)
access : read-write
Provides the interface for generating Instrumentation packets
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
STIMULUS : Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated.
bits : 0 - 31 (32 bit)
access : read-write
Provides the interface for generating Instrumentation packets
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
STIMULUS : Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated.
bits : 0 - 31 (32 bit)
access : read-write
Provides CoreSight discovery information for the FPB
address_offset : 0x2FBC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ARCHPART : Defines the architecture of the component
bits : 0 - 11 (12 bit)
access : read-only
ARCHVER : Defines the architecture version of the component
bits : 12 - 15 (4 bit)
access : read-only
REVISION : Defines the architecture revision of the component
bits : 16 - 19 (4 bit)
access : read-only
PRESENT : Defines that the DEVARCH register is present
bits : 20 - 20 (1 bit)
access : read-only
ARCHITECT : Defines the architect of the component. Bits [31:28] are the JEP106 continuation code (JEP106 bank ID, minus 1) and bits [27:21] are the JEP106 ID code.
bits : 21 - 31 (11 bit)
access : read-only
Provides CoreSight discovery information for the FPB
address_offset : 0x2FCC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MAJOR : Component major type
bits : 0 - 3 (4 bit)
access : read-only
SUB : Component sub-type
bits : 4 - 7 (4 bit)
access : read-only
Provides CoreSight discovery information for the FP
address_offset : 0x2FD0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DES_2 : See CoreSight Architecture Specification
bits : 0 - 3 (4 bit)
access : read-only
SIZE : See CoreSight Architecture Specification
bits : 4 - 7 (4 bit)
access : read-only
Provides CoreSight discovery information for the FP
address_offset : 0x2FD4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FP_PIDR5 :
bits : 0 - 31 (32 bit)
access : read-write
Provides CoreSight discovery information for the FP
address_offset : 0x2FD8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FP_PIDR6 :
bits : 0 - 31 (32 bit)
access : read-write
Provides CoreSight discovery information for the FP
address_offset : 0x2FDC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FP_PIDR7 :
bits : 0 - 31 (32 bit)
access : read-write
Provides CoreSight discovery information for the FP
address_offset : 0x2FE0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PART_0 : See CoreSight Architecture Specification
bits : 0 - 7 (8 bit)
access : read-only
Provides CoreSight discovery information for the FP
address_offset : 0x2FE4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PART_1 : See CoreSight Architecture Specification
bits : 0 - 3 (4 bit)
access : read-only
DES_0 : See CoreSight Architecture Specification
bits : 4 - 7 (4 bit)
access : read-only
Provides CoreSight discovery information for the FP
address_offset : 0x2FE8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DES_1 : See CoreSight Architecture Specification
bits : 0 - 2 (3 bit)
access : read-only
JEDEC : See CoreSight Architecture Specification
bits : 3 - 3 (1 bit)
access : read-only
REVISION : See CoreSight Architecture Specification
bits : 4 - 7 (4 bit)
access : read-only
Provides CoreSight discovery information for the FP
address_offset : 0x2FEC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CMOD : See CoreSight Architecture Specification
bits : 0 - 3 (4 bit)
access : read-only
REVAND : See CoreSight Architecture Specification
bits : 4 - 7 (4 bit)
access : read-only
Provides CoreSight discovery information for the FP
address_offset : 0x2FF0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRMBL_0 : See CoreSight Architecture Specification
bits : 0 - 7 (8 bit)
access : read-only
Provides CoreSight discovery information for the FP
address_offset : 0x2FF4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRMBL_1 : See CoreSight Architecture Specification
bits : 0 - 3 (4 bit)
access : read-only
CLASS : See CoreSight Architecture Specification
bits : 4 - 7 (4 bit)
access : read-only
Provides CoreSight discovery information for the FP
address_offset : 0x2FF8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRMBL_2 : See CoreSight Architecture Specification
bits : 0 - 7 (8 bit)
access : read-only
Provides CoreSight discovery information for the FP
address_offset : 0x2FFC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRMBL_3 : See CoreSight Architecture Specification
bits : 0 - 7 (8 bit)
access : read-only
Provides the interface for generating Instrumentation packets
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
STIMULUS : Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated.
bits : 0 - 31 (32 bit)
access : read-write
Provides the interface for generating Instrumentation packets
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
STIMULUS : Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated.
bits : 0 - 31 (32 bit)
access : read-write
Provides the interface for generating Instrumentation packets
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
STIMULUS : Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated.
bits : 0 - 31 (32 bit)
access : read-write
Provides the interface for generating Instrumentation packets
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
STIMULUS : Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated.
bits : 0 - 31 (32 bit)
access : read-write
Provides the interface for generating Instrumentation packets
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
STIMULUS : Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated.
bits : 0 - 31 (32 bit)
access : read-write
Provides the interface for generating Instrumentation packets
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
STIMULUS : Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated.
bits : 0 - 31 (32 bit)
access : read-write
Programming Control Register
address_offset : 0x41004 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : Trace Unit Enable
bits : 0 - 0 (1 bit)
access : read-write
The TRCSTATR indicates the ETM-Teal status
address_offset : 0x4100C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IDLE : Indicates that the trace unit is inactive
bits : 0 - 0 (1 bit)
access : read-only
PMSTABLE : Indicates whether the ETM-Teal registers are stable and can be read
bits : 1 - 1 (1 bit)
access : read-only
The TRCCONFIGR sets the basic tracing options for the trace unit
address_offset : 0x41010 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BB : Branch broadcast mode
bits : 3 - 3 (1 bit)
access : read-write
CCI : Cycle counting in instruction trace
bits : 4 - 4 (1 bit)
access : read-write
COND : Conditional instruction tracing
bits : 5 - 10 (6 bit)
access : read-write
TS : Global timestamp tracing
bits : 11 - 11 (1 bit)
access : read-write
RS : Return stack enable
bits : 12 - 12 (1 bit)
access : read-write
The TRCEVENTCTL0R controls the tracing of events in the trace stream. The events also drive the ETM-Teal external outputs.
address_offset : 0x41020 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SEL0 : Selects the resource number, based on the value of TYPE0: When TYPE1 is 0, selects a single selected resource from 0-15 defined by SEL0[2:0]. When TYPE1 is 1, selects a Boolean combined resource pair from 0-7 defined by SEL0[2:0]
bits : 0 - 2 (3 bit)
access : read-write
TYPE0 : Selects the resource type for event 0
bits : 7 - 7 (1 bit)
access : read-write
SEL1 : Selects the resource number, based on the value of TYPE1: When TYPE1 is 0, selects a single selected resource from 0-15 defined by SEL1[2:0]. When TYPE1 is 1, selects a Boolean combined resource pair from 0-7 defined by SEL1[2:0]
bits : 8 - 10 (3 bit)
access : read-write
TYPE1 : Selects the resource type for event 1
bits : 15 - 15 (1 bit)
access : read-write
The TRCEVENTCTL1R controls how the events selected by TRCEVENTCTL0R behave
address_offset : 0x41024 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INSTEN0 : One bit per event, to enable generation of an event element in the instruction trace stream when the selected event occurs
bits : 0 - 0 (1 bit)
access : read-write
INSTEN1 : One bit per event, to enable generation of an event element in the instruction trace stream when the selected event occurs
bits : 1 - 1 (1 bit)
access : read-write
ATB : ATB enabled
bits : 11 - 11 (1 bit)
access : read-write
LPOVERRIDE : Low power state behavior override
bits : 12 - 12 (1 bit)
access : read-write
The TRCSTALLCTLR enables ETM-Teal to stall the processor if the ETM-Teal FIFO goes over the programmed level to minimize risk of overflow
address_offset : 0x4102C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LEVEL : Threshold at which stalling becomes active. This provides four levels. This level can be varied to optimize the level of invasion caused by stalling, balanced against the risk of a FIFO overflow
bits : 2 - 3 (2 bit)
access : read-write
ISTALL : Stall processor based on instruction trace buffer space
bits : 8 - 8 (1 bit)
access : read-write
INSTPRIORITY : Reserved, RES0
bits : 10 - 10 (1 bit)
access : read-only
The TRCTSCTLR controls the insertion of global timestamps into the trace stream. A timestamp is always inserted into the instruction trace stream
address_offset : 0x41030 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SEL0 : Selects the resource number, based on the value of TYPE0: When TYPE1 is 0, selects a single selected resource from 0-15 defined by SEL0[2:0]. When TYPE1 is 1, selects a Boolean combined resource pair from 0-7 defined by SEL0[2:0]
bits : 0 - 1 (2 bit)
access : read-write
TYPE0 : Selects the resource type for event 0
bits : 7 - 7 (1 bit)
access : read-write
The TRCSYNCPR specifies the period of trace synchronization of the trace streams. TRCSYNCPR defines a number of bytes of trace between requests for trace synchronization. This value is always a power of two
address_offset : 0x41034 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PERIOD : Defines the number of bytes of trace between trace synchronization requests as a total of the number of bytes generated by the instruction stream. The number of bytes is 2N where N is the value of this field: - A value of zero disables these periodic trace synchronization requests, but does not disable other trace synchronization requests. - The minimum value that can be programmed, other than zero, is 8, providing a minimum trace synchronization period of 256 bytes. - The maximum value is 20, providing a maximum trace synchronization period of 2^20 bytes
bits : 0 - 4 (5 bit)
access : read-only
The TRCCCCTLR sets the threshold value for instruction trace cycle counting. The threshold represents the minimum interval between cycle count trace packets
address_offset : 0x41038 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
THRESHOLD : Instruction trace cycle count threshold
bits : 0 - 11 (12 bit)
access : read-write
The TRCVICTLR controls instruction trace filtering
address_offset : 0x41080 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SEL0 : Selects the resource number, based on the value of TYPE0: When TYPE1 is 0, selects a single selected resource from 0-15 defined by SEL0[2:0]. When TYPE1 is 1, selects a Boolean combined resource pair from 0-7 defined by SEL0[2:0]
bits : 0 - 1 (2 bit)
access : read-write
TYPE0 : Selects the resource type for event 0
bits : 7 - 7 (1 bit)
access : read-write
SSSTATUS : Indicates the current status of the start/stop logic
bits : 9 - 9 (1 bit)
access : read-write
TRCRESET : Selects whether a reset exception must always be traced
bits : 10 - 10 (1 bit)
access : read-write
TRCERR : Selects whether a system error exception must always be traced
bits : 11 - 11 (1 bit)
access : read-write
EXLEVEL_S0 : In Secure state, each bit controls whether instruction tracing is enabled for the corresponding exception level
bits : 16 - 16 (1 bit)
access : read-write
EXLEVEL_S3 : In Secure state, each bit controls whether instruction tracing is enabled for the corresponding exception level
bits : 19 - 19 (1 bit)
access : read-write
The TRCCNTRLDVR defines the reload value for the reduced function counter
address_offset : 0x41140 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VALUE : Defines the reload value for the counter. This value is loaded into the counter each time the reload event occurs
bits : 0 - 15 (16 bit)
access : read-write
TRCIDR8
address_offset : 0x41180 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MAXSPEC : reads as `ImpDef
bits : 0 - 31 (32 bit)
access : read-only
TRCIDR9
address_offset : 0x41184 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
NUMP0KEY : reads as `ImpDef
bits : 0 - 31 (32 bit)
access : read-only
TRCIDR10
address_offset : 0x41188 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
NUMP1KEY : reads as `ImpDef
bits : 0 - 31 (32 bit)
access : read-only
TRCIDR11
address_offset : 0x4118C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
NUMP1SPC : reads as `ImpDef
bits : 0 - 31 (32 bit)
access : read-only
TRCIDR12
address_offset : 0x41190 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
NUMCONDKEY : reads as `ImpDef
bits : 0 - 31 (32 bit)
access : read-only
TRCIDR13
address_offset : 0x41194 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
NUMCONDSPC : reads as `ImpDef
bits : 0 - 31 (32 bit)
access : read-only
The TRCIMSPEC shows the presence of any IMPLEMENTATION SPECIFIC features, and enables any features that are provided
address_offset : 0x411C0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SUPPORT : Reserved, RES0
bits : 0 - 3 (4 bit)
access : read-only
TRCIDR0
address_offset : 0x411E0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RES1 : Reserved, RES1
bits : 0 - 0 (1 bit)
access : read-only
INSTP0 : reads as `ImpDef
bits : 1 - 2 (2 bit)
access : read-only
TRCDATA : reads as `ImpDef
bits : 3 - 4 (2 bit)
access : read-only
TRCBB : reads as `ImpDef
bits : 5 - 5 (1 bit)
access : read-only
TRCCOND : reads as `ImpDef
bits : 6 - 6 (1 bit)
access : read-only
TRCCCI : reads as `ImpDef
bits : 7 - 7 (1 bit)
access : read-only
RETSTACK : reads as `ImpDef
bits : 9 - 9 (1 bit)
access : read-only
NUMEVENT : reads as `ImpDef
bits : 10 - 11 (2 bit)
access : read-only
CONDTYPE : reads as `ImpDef
bits : 12 - 13 (2 bit)
access : read-only
QFILT : reads as `ImpDef
bits : 14 - 14 (1 bit)
access : read-only
QSUPP : reads as `ImpDef
bits : 15 - 16 (2 bit)
access : read-only
TRCEXDATA : reads as `ImpDef
bits : 17 - 17 (1 bit)
access : read-only
TSSIZE : reads as `ImpDef
bits : 24 - 28 (5 bit)
access : read-only
COMMOPT : reads as `ImpDef
bits : 29 - 29 (1 bit)
access : read-only
TRCIDR1
address_offset : 0x411E4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
REVISION : reads as `ImpDef
bits : 0 - 3 (4 bit)
access : read-only
TRCARCHMIN : reads as 0b0000
bits : 4 - 7 (4 bit)
access : read-only
TRCARCHMAJ : reads as 0b0100
bits : 8 - 11 (4 bit)
access : read-only
RES1 : Reserved, RES1
bits : 12 - 15 (4 bit)
access : read-only
DESIGNER : reads as `ImpDef
bits : 24 - 31 (8 bit)
access : read-only
TRCIDR2
address_offset : 0x411E8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IASIZE : reads as `ImpDef
bits : 0 - 4 (5 bit)
access : read-only
CIDSIZE : reads as `ImpDef
bits : 5 - 9 (5 bit)
access : read-only
VMIDSIZE : reads as `ImpDef
bits : 10 - 14 (5 bit)
access : read-only
DASIZE : reads as `ImpDef
bits : 15 - 19 (5 bit)
access : read-only
DVSIZE : reads as `ImpDef
bits : 20 - 24 (5 bit)
access : read-only
CCSIZE : reads as `ImpDef
bits : 25 - 28 (4 bit)
access : read-only
TRCIDR3
address_offset : 0x411EC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CCITMIN : reads as `ImpDef
bits : 0 - 11 (12 bit)
access : read-only
EXLEVEL_S : reads as `ImpDef
bits : 16 - 19 (4 bit)
access : read-only
EXLEVEL_NS : reads as `ImpDef
bits : 20 - 23 (4 bit)
access : read-only
TRCERR : reads as `ImpDef
bits : 24 - 24 (1 bit)
access : read-only
SYNCPR : reads as `ImpDef
bits : 25 - 25 (1 bit)
access : read-only
STALLCTL : reads as `ImpDef
bits : 26 - 26 (1 bit)
access : read-only
SYSSTALL : reads as `ImpDef
bits : 27 - 27 (1 bit)
access : read-only
NUMPROC : reads as `ImpDef
bits : 28 - 30 (3 bit)
access : read-only
NOOVERFLOW : reads as `ImpDef
bits : 31 - 31 (1 bit)
access : read-only
TRCIDR4
address_offset : 0x411F0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
NUMACPAIRS : reads as `ImpDef
bits : 0 - 3 (4 bit)
access : read-only
NUMDVC : reads as `ImpDef
bits : 4 - 7 (4 bit)
access : read-only
SUPPDAC : reads as `ImpDef
bits : 8 - 8 (1 bit)
access : read-only
NUMPC : reads as `ImpDef
bits : 12 - 15 (4 bit)
access : read-only
NUMRSPAIR : reads as `ImpDef
bits : 16 - 19 (4 bit)
access : read-only
NUMSSCC : reads as `ImpDef
bits : 20 - 23 (4 bit)
access : read-only
NUMCIDC : reads as `ImpDef
bits : 24 - 27 (4 bit)
access : read-only
NUMVMIDC : reads as `ImpDef
bits : 28 - 31 (4 bit)
access : read-only
TRCIDR5
address_offset : 0x411F4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
NUMEXTIN : reads as `ImpDef
bits : 0 - 8 (9 bit)
access : read-only
NUMEXTINSEL : reads as `ImpDef
bits : 9 - 11 (3 bit)
access : read-only
TRACEIDSIZE : reads as 0x07
bits : 16 - 21 (6 bit)
access : read-only
ATBTRIG : reads as `ImpDef
bits : 22 - 22 (1 bit)
access : read-only
LPOVERRIDE : reads as `ImpDef
bits : 23 - 23 (1 bit)
access : read-only
NUMSEQSTATE : reads as `ImpDef
bits : 25 - 27 (3 bit)
access : read-only
NUMCNTR : reads as `ImpDef
bits : 28 - 30 (3 bit)
access : read-only
REDFUNCNTR : reads as `ImpDef
bits : 31 - 31 (1 bit)
access : read-only
TRCIDR6
address_offset : 0x411F8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TRCIDR6 :
bits : 0 - 31 (32 bit)
access : read-write
TRCIDR7
address_offset : 0x411FC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TRCIDR7 :
bits : 0 - 31 (32 bit)
access : read-write
The TRCRSCTLR controls the trace resources
address_offset : 0x41208 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SELECT : Selects one or more resources from the wanted group. One bit is provided per resource from the group
bits : 0 - 7 (8 bit)
access : read-write
GROUP : Selects a group of resource
bits : 16 - 18 (3 bit)
access : read-write
INV : Inverts the selected resources
bits : 20 - 20 (1 bit)
access : read-write
PAIRINV : Inverts the result of a combined pair of resources. This bit is only implemented on the lower register for a pair of resource selectors
bits : 21 - 21 (1 bit)
access : read-write
The TRCRSCTLR controls the trace resources
address_offset : 0x4120C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SELECT : Selects one or more resources from the wanted group. One bit is provided per resource from the group
bits : 0 - 7 (8 bit)
access : read-write
GROUP : Selects a group of resource
bits : 16 - 18 (3 bit)
access : read-write
INV : Inverts the selected resources
bits : 20 - 20 (1 bit)
access : read-write
PAIRINV : Inverts the result of a combined pair of resources. This bit is only implemented on the lower register for a pair of resource selectors
bits : 21 - 21 (1 bit)
access : read-write
Controls the corresponding single-shot comparator resource
address_offset : 0x412A0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INST : Reserved, RES0
bits : 0 - 0 (1 bit)
access : read-only
DA : Reserved, RES0
bits : 1 - 1 (1 bit)
access : read-only
DV : Reserved, RES0
bits : 2 - 2 (1 bit)
access : read-only
PC : Reserved, RES1
bits : 3 - 3 (1 bit)
access : read-only
STATUS : Single-shot status bit. Indicates if any of the comparators, that TRCSSCCRn.SAC or TRCSSCCRn.ARC selects, have matched
bits : 31 - 31 (1 bit)
access : read-write
Selects the PE comparator inputs for Single-shot control
address_offset : 0x412C0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PC : Selects one or more PE comparator inputs for Single-shot control. TRCIDR4.NUMPC defines the size of the PC field. 1 bit is provided for each implemented PE comparator input. For example, if bit[1] == 1 this selects PE comparator input 1 for Single-shot control
bits : 0 - 3 (4 bit)
access : read-write
Requests the system to provide power to the trace unit
address_offset : 0x41310 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PU : Powerup request bit:
bits : 3 - 3 (1 bit)
access : read-write
Returns the following information about the trace unit: - OS Lock status. - Core power domain status. - Power interruption status
address_offset : 0x41314 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
POWER : Power status bit:
bits : 0 - 0 (1 bit)
access : read-only
STICKYPD : Sticky powerdown status bit. Indicates whether the trace register state is valid:
bits : 1 - 1 (1 bit)
access : read-only
OSLK : OS Lock status bit:
bits : 5 - 5 (1 bit)
access : read-only
Trace Integration ATB Identification Register
address_offset : 0x41EE4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ID : Trace ID
bits : 0 - 6 (7 bit)
access : read-write
Trace Integration Instruction ATB In Register
address_offset : 0x41EF4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ATREADYM : Integration Mode instruction ATREADYM in
bits : 0 - 0 (1 bit)
access : read-write
AFVALIDM : Integration Mode instruction AFVALIDM in
bits : 1 - 1 (1 bit)
access : read-write
Trace Integration Instruction ATB Out Register
address_offset : 0x41EFC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ATVALID : Integration Mode instruction ATVALID out
bits : 0 - 0 (1 bit)
access : read-write
AFREADY : Integration Mode instruction AFREADY out
bits : 1 - 1 (1 bit)
access : read-write
Claim Tag Set Register
address_offset : 0x41FA0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SET0 : When a write to one of these bits occurs, with the value:
bits : 0 - 0 (1 bit)
access : read-write
SET1 : When a write to one of these bits occurs, with the value:
bits : 1 - 1 (1 bit)
access : read-write
SET2 : When a write to one of these bits occurs, with the value:
bits : 2 - 2 (1 bit)
access : read-write
SET3 : When a write to one of these bits occurs, with the value:
bits : 3 - 3 (1 bit)
access : read-write
Claim Tag Clear Register
address_offset : 0x41FA4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CLR0 : When a write to one of these bits occurs, with the value:
bits : 0 - 0 (1 bit)
access : read-write
CLR1 : When a write to one of these bits occurs, with the value:
bits : 1 - 1 (1 bit)
access : read-write
CLR2 : When a write to one of these bits occurs, with the value:
bits : 2 - 2 (1 bit)
access : read-write
CLR3 : When a write to one of these bits occurs, with the value:
bits : 3 - 3 (1 bit)
access : read-write
Returns the level of tracing that the trace unit can support
address_offset : 0x41FB8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
NSID : Indicates whether the trace unit supports Non-secure invasive debug:
bits : 0 - 1 (2 bit)
access : read-only
NSNID : Indicates whether the system enables the trace unit to support Non-secure non-invasive debug:
bits : 2 - 3 (2 bit)
access : read-only
SID : Indicates whether the trace unit supports Secure invasive debug:
bits : 4 - 5 (2 bit)
access : read-only
SNID : Indicates whether the system enables the trace unit to support Secure non-invasive debug:
bits : 6 - 7 (2 bit)
access : read-only
TRCDEVARCH
address_offset : 0x41FBC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ARCHID : reads as 0b0100101000010011
bits : 0 - 15 (16 bit)
access : read-only
REVISION : reads as 0b0000
bits : 16 - 19 (4 bit)
access : read-only
PRESENT : reads as 0b1
bits : 20 - 20 (1 bit)
access : read-only
ARCHITECT : reads as 0b01000111011
bits : 21 - 31 (11 bit)
access : read-only
TRCDEVID
address_offset : 0x41FC8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TRCDEVID :
bits : 0 - 31 (32 bit)
access : read-write
TRCDEVTYPE
address_offset : 0x41FCC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MAJOR : reads as 0b0011
bits : 0 - 3 (4 bit)
access : read-only
SUB : reads as 0b0001
bits : 4 - 7 (4 bit)
access : read-only
TRCPIDR4
address_offset : 0x41FD0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DES_2 : reads as `ImpDef
bits : 0 - 3 (4 bit)
access : read-only
SIZE : reads as `ImpDef
bits : 4 - 7 (4 bit)
access : read-only
TRCPIDR5
address_offset : 0x41FD4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TRCPIDR5 :
bits : 0 - 31 (32 bit)
access : read-write
TRCPIDR6
address_offset : 0x41FD8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TRCPIDR6 :
bits : 0 - 31 (32 bit)
access : read-write
TRCPIDR7
address_offset : 0x41FDC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TRCPIDR7 :
bits : 0 - 31 (32 bit)
access : read-write
TRCPIDR0
address_offset : 0x41FE0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PART_0 : reads as `ImpDef
bits : 0 - 7 (8 bit)
access : read-only
TRCPIDR1
address_offset : 0x41FE4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PART_0 : reads as `ImpDef
bits : 0 - 3 (4 bit)
access : read-only
DES_0 : reads as `ImpDef
bits : 4 - 7 (4 bit)
access : read-only
TRCPIDR2
address_offset : 0x41FE8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DES_0 : reads as `ImpDef
bits : 0 - 2 (3 bit)
access : read-only
JEDEC : reads as 0b1
bits : 3 - 3 (1 bit)
access : read-only
REVISION : reads as `ImpDef
bits : 4 - 7 (4 bit)
access : read-only
TRCPIDR3
address_offset : 0x41FEC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CMOD : reads as `ImpDef
bits : 0 - 3 (4 bit)
access : read-only
REVAND : reads as `ImpDef
bits : 4 - 7 (4 bit)
access : read-only
TRCCIDR0
address_offset : 0x41FF0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRMBL_0 : reads as 0b00001101
bits : 0 - 7 (8 bit)
access : read-only
TRCCIDR1
address_offset : 0x41FF4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRMBL_1 : reads as 0b0000
bits : 0 - 3 (4 bit)
access : read-only
CLASS : reads as 0b1001
bits : 4 - 7 (4 bit)
access : read-only
TRCCIDR2
address_offset : 0x41FF8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRMBL_2 : reads as 0b00000101
bits : 0 - 7 (8 bit)
access : read-only
TRCCIDR3
address_offset : 0x41FFC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRMBL_3 : reads as 0b10110001
bits : 0 - 7 (8 bit)
access : read-only
CTI Control Register
address_offset : 0x42000 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GLBEN : Enables or disables the CTI
bits : 0 - 0 (1 bit)
access : read-write
CTI Interrupt Acknowledge Register
address_offset : 0x42010 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INTACK : Acknowledges the corresponding ctitrigout output. There is one bit of the register for each ctitrigout output. When a 1 is written to a bit in this register, the corresponding ctitrigout is acknowledged, causing it to be cleared.
bits : 0 - 7 (8 bit)
access : read-write
CTI Application Trigger Set Register
address_offset : 0x42014 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
APPSET : Setting a bit HIGH generates a channel event for the selected channel. There is one bit of the register for each channel
bits : 0 - 3 (4 bit)
access : read-write
CTI Application Trigger Clear Register
address_offset : 0x42018 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
APPCLEAR : Sets the corresponding bits in the CTIAPPSET to 0. There is one bit of the register for each channel.
bits : 0 - 3 (4 bit)
access : read-write
CTI Application Pulse Register
address_offset : 0x4201C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
APPULSE : Setting a bit HIGH generates a channel event pulse for the selected channel. There is one bit of the register for each channel.
bits : 0 - 3 (4 bit)
access : read-write
CTI Trigger to Channel Enable Registers
address_offset : 0x42020 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TRIGINEN : Enables a cross trigger event to the corresponding channel when a ctitrigin input is activated. There is one bit of the field for each of the four channels
bits : 0 - 3 (4 bit)
access : read-write
CTI Trigger to Channel Enable Registers
address_offset : 0x42024 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TRIGINEN : Enables a cross trigger event to the corresponding channel when a ctitrigin input is activated. There is one bit of the field for each of the four channels
bits : 0 - 3 (4 bit)
access : read-write
CTI Trigger to Channel Enable Registers
address_offset : 0x42028 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TRIGINEN : Enables a cross trigger event to the corresponding channel when a ctitrigin input is activated. There is one bit of the field for each of the four channels
bits : 0 - 3 (4 bit)
access : read-write
CTI Trigger to Channel Enable Registers
address_offset : 0x4202C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TRIGINEN : Enables a cross trigger event to the corresponding channel when a ctitrigin input is activated. There is one bit of the field for each of the four channels
bits : 0 - 3 (4 bit)
access : read-write
CTI Trigger to Channel Enable Registers
address_offset : 0x42030 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TRIGINEN : Enables a cross trigger event to the corresponding channel when a ctitrigin input is activated. There is one bit of the field for each of the four channels
bits : 0 - 3 (4 bit)
access : read-write
CTI Trigger to Channel Enable Registers
address_offset : 0x42034 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TRIGINEN : Enables a cross trigger event to the corresponding channel when a ctitrigin input is activated. There is one bit of the field for each of the four channels
bits : 0 - 3 (4 bit)
access : read-write
CTI Trigger to Channel Enable Registers
address_offset : 0x42038 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TRIGINEN : Enables a cross trigger event to the corresponding channel when a ctitrigin input is activated. There is one bit of the field for each of the four channels
bits : 0 - 3 (4 bit)
access : read-write
CTI Trigger to Channel Enable Registers
address_offset : 0x4203C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TRIGINEN : Enables a cross trigger event to the corresponding channel when a ctitrigin input is activated. There is one bit of the field for each of the four channels
bits : 0 - 3 (4 bit)
access : read-write
CTI Trigger to Channel Enable Registers
address_offset : 0x420A0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TRIGOUTEN : Enables a cross trigger event to ctitrigout when the corresponding channel is activated. There is one bit of the field for each of the four channels.
bits : 0 - 3 (4 bit)
access : read-write
CTI Trigger to Channel Enable Registers
address_offset : 0x420A4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TRIGOUTEN : Enables a cross trigger event to ctitrigout when the corresponding channel is activated. There is one bit of the field for each of the four channels.
bits : 0 - 3 (4 bit)
access : read-write
CTI Trigger to Channel Enable Registers
address_offset : 0x420A8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TRIGOUTEN : Enables a cross trigger event to ctitrigout when the corresponding channel is activated. There is one bit of the field for each of the four channels.
bits : 0 - 3 (4 bit)
access : read-write
CTI Trigger to Channel Enable Registers
address_offset : 0x420AC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TRIGOUTEN : Enables a cross trigger event to ctitrigout when the corresponding channel is activated. There is one bit of the field for each of the four channels.
bits : 0 - 3 (4 bit)
access : read-write
CTI Trigger to Channel Enable Registers
address_offset : 0x420B0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TRIGOUTEN : Enables a cross trigger event to ctitrigout when the corresponding channel is activated. There is one bit of the field for each of the four channels.
bits : 0 - 3 (4 bit)
access : read-write
CTI Trigger to Channel Enable Registers
address_offset : 0x420B4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TRIGOUTEN : Enables a cross trigger event to ctitrigout when the corresponding channel is activated. There is one bit of the field for each of the four channels.
bits : 0 - 3 (4 bit)
access : read-write
CTI Trigger to Channel Enable Registers
address_offset : 0x420B8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TRIGOUTEN : Enables a cross trigger event to ctitrigout when the corresponding channel is activated. There is one bit of the field for each of the four channels.
bits : 0 - 3 (4 bit)
access : read-write
CTI Trigger to Channel Enable Registers
address_offset : 0x420BC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TRIGOUTEN : Enables a cross trigger event to ctitrigout when the corresponding channel is activated. There is one bit of the field for each of the four channels.
bits : 0 - 3 (4 bit)
access : read-write
CTI Trigger to Channel Enable Registers
address_offset : 0x42130 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TRIGINSTATUS : Shows the status of the ctitrigin inputs. There is one bit of the field for each trigger input.Because the register provides a view of the raw ctitrigin inputs, the reset value is UNKNOWN.
bits : 0 - 7 (8 bit)
access : read-only
CTI Trigger In Status Register
address_offset : 0x42134 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TRIGOUTSTATUS : Shows the status of the ctitrigout outputs. There is one bit of the field for each trigger output.
bits : 0 - 7 (8 bit)
access : read-only
CTI Channel In Status Register
address_offset : 0x42138 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CTICHOUTSTATUS : Shows the status of the ctichout outputs. There is one bit of the field for each channel output
bits : 0 - 3 (4 bit)
access : read-only
Enable CTI Channel Gate register
address_offset : 0x42140 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CTIGATEEN0 : Enable ctichout0. Set to 0 to disable channel propagation.
bits : 0 - 0 (1 bit)
access : read-write
CTIGATEEN1 : Enable ctichout1. Set to 0 to disable channel propagation.
bits : 1 - 1 (1 bit)
access : read-write
CTIGATEEN2 : Enable ctichout2. Set to 0 to disable channel propagation.
bits : 2 - 2 (1 bit)
access : read-write
CTIGATEEN3 : Enable ctichout3. Set to 0 to disable channel propagation.
bits : 3 - 3 (1 bit)
access : read-write
External Multiplexer Control register
address_offset : 0x42144 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ASICCTL :
bits : 0 - 31 (32 bit)
access : read-write
Integration Test Channel Output register
address_offset : 0x42EE4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CTCHOUT : Sets the value of the ctichout outputs
bits : 0 - 3 (4 bit)
access : read-write
Integration Test Trigger Output register
address_offset : 0x42EE8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CTTRIGOUT : Sets the value of the ctitrigout outputs
bits : 0 - 7 (8 bit)
access : read-write
Integration Test Channel Input register
address_offset : 0x42EF4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CTCHIN : Reads the value of the ctichin inputs.
bits : 0 - 3 (4 bit)
access : read-only
Integration Mode Control register
address_offset : 0x42F00 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IME : Integration Mode Enable
bits : 0 - 0 (1 bit)
access : read-write
Device Architecture register
address_offset : 0x42FBC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ARCHID : Indicates the component
bits : 0 - 15 (16 bit)
access : read-only
REVISION : Indicates the architecture revision
bits : 16 - 19 (4 bit)
access : read-only
PRESENT : Indicates whether the DEVARCH register is present
bits : 20 - 20 (1 bit)
access : read-only
ARCHITECT : Indicates the component architect
bits : 21 - 31 (11 bit)
access : read-only
Device Configuration register
address_offset : 0x42FC8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EXTMUXNUM : Indicates the number of multiplexers available on Trigger Inputs and Trigger Outputs that are using asicctl. The default value of 0b00000 indicates that no multiplexing is present. This value of this bit depends on the Verilog define EXTMUXNUM that you must change accordingly.
bits : 0 - 4 (5 bit)
access : read-only
NUMTRIG : Number of ECT triggers available.
bits : 8 - 15 (8 bit)
access : read-only
NUMCH : Number of ECT channels available
bits : 16 - 19 (4 bit)
access : read-only
Device Type Identifier register
address_offset : 0x42FCC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MAJOR : Major classification of the type of the debug component as specified in the ARM Architecture Specification for this debug and trace component.
bits : 0 - 3 (4 bit)
access : read-only
SUB : Sub-classification of the type of the debug component as specified in the ARM Architecture Specification within the major classification as specified in the MAJOR field.
bits : 4 - 7 (4 bit)
access : read-only
CoreSight Peripheral ID4
address_offset : 0x42FD0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DES_2 : Together, PIDR1.DES_0, PIDR2.DES_1, and PIDR4.DES_2 identify the designer of the component.
bits : 0 - 3 (4 bit)
access : read-only
SIZE : Always 0b0000. Indicates that the device only occupies 4KB of memory
bits : 4 - 7 (4 bit)
access : read-only
CoreSight Peripheral ID5
address_offset : 0x42FD4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PIDR5 :
bits : 0 - 31 (32 bit)
access : read-write
CoreSight Peripheral ID6
address_offset : 0x42FD8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PIDR6 :
bits : 0 - 31 (32 bit)
access : read-write
CoreSight Peripheral ID7
address_offset : 0x42FDC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PIDR7 :
bits : 0 - 31 (32 bit)
access : read-write
CoreSight Peripheral ID0
address_offset : 0x42FE0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PART_0 : Bits[7:0] of the 12-bit part number of the component. The designer of the component assigns this part number.
bits : 0 - 7 (8 bit)
access : read-only
CoreSight Peripheral ID1
address_offset : 0x42FE4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PART_1 : Bits[11:8] of the 12-bit part number of the component. The designer of the component assigns this part number.
bits : 0 - 3 (4 bit)
access : read-only
DES_0 : Together, PIDR1.DES_0, PIDR2.DES_1, and PIDR4.DES_2 identify the designer of the component.
bits : 4 - 7 (4 bit)
access : read-only
CoreSight Peripheral ID2
address_offset : 0x42FE8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DES_1 : Together, PIDR1.DES_0, PIDR2.DES_1, and PIDR4.DES_2 identify the designer of the component.
bits : 0 - 2 (3 bit)
access : read-only
JEDEC : Always 1. Indicates that the JEDEC-assigned designer ID is used.
bits : 3 - 3 (1 bit)
access : read-only
REVISION : This device is at r1p0
bits : 4 - 7 (4 bit)
access : read-only
CoreSight Peripheral ID3
address_offset : 0x42FEC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CMOD : Customer Modified. Indicates whether the customer has modified the behavior of the component. In most cases, this field is 0b0000. Customers change this value when they make authorized modifications to this component.
bits : 0 - 3 (4 bit)
access : read-only
REVAND : Indicates minor errata fixes specific to the revision of the component being used, for example metal fixes after implementation. In most cases, this field is 0b0000. ARM recommends that the component designers ensure that a metal fix can change this field if required, for example, by driving it from registers that reset to 0b0000.
bits : 4 - 7 (4 bit)
access : read-only
CoreSight Component ID0
address_offset : 0x42FF0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRMBL_0 : Preamble[0]. Contains bits[7:0] of the component identification code
bits : 0 - 7 (8 bit)
access : read-only
CoreSight Component ID1
address_offset : 0x42FF4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRMBL_1 : Preamble[1]. Contains bits[11:8] of the component identification code.
bits : 0 - 3 (4 bit)
access : read-only
CLASS : Class of the component, for example, whether the component is a ROM table or a generic CoreSight component. Contains bits[15:12] of the component identification code.
bits : 4 - 7 (4 bit)
access : read-only
CoreSight Component ID2
address_offset : 0x42FF8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRMBL_2 : Preamble[2]. Contains bits[23:16] of the component identification code.
bits : 0 - 7 (8 bit)
access : read-only
CoreSight Component ID3
address_offset : 0x42FFC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRMBL_3 : Preamble[3]. Contains bits[31:24] of the component identification code.
bits : 0 - 7 (8 bit)
access : read-only
Provides the interface for generating Instrumentation packets
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
STIMULUS : Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated.
bits : 0 - 31 (32 bit)
access : read-write
Provides the interface for generating Instrumentation packets
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
STIMULUS : Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated.
bits : 0 - 31 (32 bit)
access : read-write
Provides the interface for generating Instrumentation packets
address_offset : 0x4C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
STIMULUS : Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated.
bits : 0 - 31 (32 bit)
access : read-write
Provides the interface for generating Instrumentation packets
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
STIMULUS : Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated.
bits : 0 - 31 (32 bit)
access : read-write
Provides the interface for generating Instrumentation packets
address_offset : 0x54 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
STIMULUS : Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated.
bits : 0 - 31 (32 bit)
access : read-write
Provides the interface for generating Instrumentation packets
address_offset : 0x58 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
STIMULUS : Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated.
bits : 0 - 31 (32 bit)
access : read-write
Provides the interface for generating Instrumentation packets
address_offset : 0x5C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
STIMULUS : Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated.
bits : 0 - 31 (32 bit)
access : read-write
Provides the interface for generating Instrumentation packets
address_offset : 0x60 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
STIMULUS : Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated.
bits : 0 - 31 (32 bit)
access : read-write
Provides the interface for generating Instrumentation packets
address_offset : 0x64 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
STIMULUS : Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated.
bits : 0 - 31 (32 bit)
access : read-write
Provides the interface for generating Instrumentation packets
address_offset : 0x68 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
STIMULUS : Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated.
bits : 0 - 31 (32 bit)
access : read-write
Provides the interface for generating Instrumentation packets
address_offset : 0x6C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
STIMULUS : Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated.
bits : 0 - 31 (32 bit)
access : read-write
Provides the interface for generating Instrumentation packets
address_offset : 0x70 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
STIMULUS : Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated.
bits : 0 - 31 (32 bit)
access : read-write
Provides the interface for generating Instrumentation packets
address_offset : 0x74 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
STIMULUS : Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated.
bits : 0 - 31 (32 bit)
access : read-write
Provides the interface for generating Instrumentation packets
address_offset : 0x78 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
STIMULUS : Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated.
bits : 0 - 31 (32 bit)
access : read-write
Provides the interface for generating Instrumentation packets
address_offset : 0x7C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
STIMULUS : Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated.
bits : 0 - 31 (32 bit)
access : read-write
Provides the interface for generating Instrumentation packets
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
STIMULUS : Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated.
bits : 0 - 31 (32 bit)
access : read-write
Provides the interface for generating Instrumentation packets
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
STIMULUS : Data to write to the Stimulus Port FIFO, for forwarding as an Instrumentation packet. The size of write access determines the type of Instrumentation packet generated.
bits : 0 - 31 (32 bit)
access : read-write
Provide an individual enable bit for each ITM_STIM register
address_offset : 0xE00 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
STIMENA : For STIMENA[m] in ITM_TER*n, controls whether ITM_STIM(32*n + m) is enabled
bits : 0 - 31 (32 bit)
access : read-write
Provides information about the interrupt controller
address_offset : 0xE004 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INTLINESNUM : Indicates the number of the highest implemented register in each of the NVIC control register sets, or in the case of NVIC_IPR*n, 4×INTLINESNUM
bits : 0 - 3 (4 bit)
access : read-only
Provides IMPLEMENTATION DEFINED configuration and control options
address_offset : 0xE008 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DISMCYCINT : Disable dual-issue.
bits : 0 - 0 (1 bit)
access : read-write
DISFOLD : Disable dual-issue.
bits : 2 - 2 (1 bit)
access : read-write
DISOOFP : Disable out-of-order FP instruction completion
bits : 9 - 9 (1 bit)
access : read-write
FPEXCODIS : Disable FPU exception outputs
bits : 10 - 10 (1 bit)
access : read-write
DISITMATBFLUSH : Disable ATB Flush
bits : 12 - 12 (1 bit)
access : read-write
EXTEXCLALL : External Exclusives Allowed with no MPU
bits : 29 - 29 (1 bit)
access : read-write
Use the SysTick Control and Status Register to enable the SysTick features.
address_offset : 0xE010 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ENABLE : Enable SysTick counter:
0 = Counter disabled.
1 = Counter enabled.
bits : 0 - 0 (1 bit)
access : read-write
TICKINT : Enables SysTick exception request:
0 = Counting down to zero does not assert the SysTick exception request.
1 = Counting down to zero to asserts the SysTick exception request.
bits : 1 - 1 (1 bit)
access : read-write
CLKSOURCE : SysTick clock source. Always reads as one if SYST_CALIB reports NOREF.
Selects the SysTick timer clock source:
0 = External reference clock.
1 = Processor clock.
bits : 2 - 2 (1 bit)
access : read-write
COUNTFLAG : Returns 1 if timer counted to 0 since last time this was read. Clears on read by application or debugger.
bits : 16 - 16 (1 bit)
access : read-only
Use the SysTick Reload Value Register to specify the start value to load into the current value register when the counter reaches 0. It can be any value between 0 and 0x00FFFFFF. A start value of 0 is possible, but has no effect because the SysTick interrupt and COUNTFLAG are activated when counting from 1 to 0. The reset value of this register is UNKNOWN.
To generate a multi-shot timer with a period of N processor clock cycles, use a RELOAD value of N-1. For example, if the SysTick interrupt is required every 100 clock pulses, set RELOAD to 99.
address_offset : 0xE014 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RELOAD : Value to load into the SysTick Current Value Register when the counter reaches 0.
bits : 0 - 23 (24 bit)
access : read-write
Use the SysTick Current Value Register to find the current value in the register. The reset value of this register is UNKNOWN.
address_offset : 0xE018 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CURRENT : Reads return the current value of the SysTick counter. This register is write-clear. Writing to it with any value clears the register to 0. Clearing this register also clears the COUNTFLAG bit of the SysTick Control and Status Register.
bits : 0 - 23 (24 bit)
access : read-write
Use the SysTick Calibration Value Register to enable software to scale to any required speed using divide and multiply.
address_offset : 0xE01C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TENMS : An optional Reload value to be used for 10ms (100Hz) timing, subject to system clock skew errors. If the value reads as 0, the calibration value is not known.
bits : 0 - 23 (24 bit)
access : read-only
SKEW : If reads as 1, the calibration value for 10ms is inexact (due to clock frequency).
bits : 30 - 30 (1 bit)
access : read-only
NOREF : If reads as 1, the Reference clock is not provided - the CLKSOURCE bit of the SysTick Control and Status register will be forced to 1 and cannot be cleared to 0.
bits : 31 - 31 (1 bit)
access : read-only
Enables or reads the enabled state of each group of 32 interrupts
address_offset : 0xE100 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SETENA : For SETENA[m] in NVIC_ISER*n, indicates whether interrupt 32*n + m is enabled
bits : 0 - 31 (32 bit)
access : read-write
Enables or reads the enabled state of each group of 32 interrupts
address_offset : 0xE104 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SETENA : For SETENA[m] in NVIC_ISER*n, indicates whether interrupt 32*n + m is enabled
bits : 0 - 31 (32 bit)
access : read-write
Clears or reads the enabled state of each group of 32 interrupts
address_offset : 0xE180 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CLRENA : For CLRENA[m] in NVIC_ICER*n, indicates whether interrupt 32*n + m is enabled
bits : 0 - 31 (32 bit)
access : read-write
Clears or reads the enabled state of each group of 32 interrupts
address_offset : 0xE184 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CLRENA : For CLRENA[m] in NVIC_ICER*n, indicates whether interrupt 32*n + m is enabled
bits : 0 - 31 (32 bit)
access : read-write
Enables or reads the pending state of each group of 32 interrupts
address_offset : 0xE200 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SETPEND : For SETPEND[m] in NVIC_ISPR*n, indicates whether interrupt 32*n + m is pending
bits : 0 - 31 (32 bit)
access : read-write
Enables or reads the pending state of each group of 32 interrupts
address_offset : 0xE204 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SETPEND : For SETPEND[m] in NVIC_ISPR*n, indicates whether interrupt 32*n + m is pending
bits : 0 - 31 (32 bit)
access : read-write
Clears or reads the pending state of each group of 32 interrupts
address_offset : 0xE280 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CLRPEND : For CLRPEND[m] in NVIC_ICPR*n, indicates whether interrupt 32*n + m is pending
bits : 0 - 31 (32 bit)
access : read-write
Clears or reads the pending state of each group of 32 interrupts
address_offset : 0xE284 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CLRPEND : For CLRPEND[m] in NVIC_ICPR*n, indicates whether interrupt 32*n + m is pending
bits : 0 - 31 (32 bit)
access : read-write
For each group of 32 interrupts, shows the active state of each interrupt
address_offset : 0xE300 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ACTIVE : For ACTIVE[m] in NVIC_IABR*n, indicates the active state for interrupt 32*n+m
bits : 0 - 31 (32 bit)
access : read-write
For each group of 32 interrupts, shows the active state of each interrupt
address_offset : 0xE304 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ACTIVE : For ACTIVE[m] in NVIC_IABR*n, indicates the active state for interrupt 32*n+m
bits : 0 - 31 (32 bit)
access : read-write
For each group of 32 interrupts, determines whether each interrupt targets Non-secure or Secure state
address_offset : 0xE380 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ITNS : For ITNS[m] in NVIC_ITNS*n, `IAAMO the target Security state for interrupt 32*n+m
bits : 0 - 31 (32 bit)
access : read-write
For each group of 32 interrupts, determines whether each interrupt targets Non-secure or Secure state
address_offset : 0xE384 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ITNS : For ITNS[m] in NVIC_ITNS*n, `IAAMO the target Security state for interrupt 32*n+m
bits : 0 - 31 (32 bit)
access : read-write
Controls which stimulus ports can be accessed by unprivileged code
address_offset : 0xE40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRIVMASK : Bit mask to enable tracing on ITM stimulus ports
bits : 0 - 3 (4 bit)
access : read-write
Sets or reads interrupt priorities
address_offset : 0xE400 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRI_N0 : For register NVIC_IPRn, the priority of interrupt number 4*n+0, or RES0 if the PE does not implement this interrupt
bits : 4 - 7 (4 bit)
access : read-write
PRI_N1 : For register NVIC_IPRn, the priority of interrupt number 4*n+1, or RES0 if the PE does not implement this interrupt
bits : 12 - 15 (4 bit)
access : read-write
PRI_N2 : For register NVIC_IPRn, the priority of interrupt number 4*n+2, or RES0 if the PE does not implement this interrupt
bits : 20 - 23 (4 bit)
access : read-write
PRI_N3 : For register NVIC_IPRn, the priority of interrupt number 4*n+3, or RES0 if the PE does not implement this interrupt
bits : 28 - 31 (4 bit)
access : read-write
Sets or reads interrupt priorities
address_offset : 0xE404 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRI_N0 : For register NVIC_IPRn, the priority of interrupt number 4*n+0, or RES0 if the PE does not implement this interrupt
bits : 4 - 7 (4 bit)
access : read-write
PRI_N1 : For register NVIC_IPRn, the priority of interrupt number 4*n+1, or RES0 if the PE does not implement this interrupt
bits : 12 - 15 (4 bit)
access : read-write
PRI_N2 : For register NVIC_IPRn, the priority of interrupt number 4*n+2, or RES0 if the PE does not implement this interrupt
bits : 20 - 23 (4 bit)
access : read-write
PRI_N3 : For register NVIC_IPRn, the priority of interrupt number 4*n+3, or RES0 if the PE does not implement this interrupt
bits : 28 - 31 (4 bit)
access : read-write
Sets or reads interrupt priorities
address_offset : 0xE408 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRI_N0 : For register NVIC_IPRn, the priority of interrupt number 4*n+0, or RES0 if the PE does not implement this interrupt
bits : 4 - 7 (4 bit)
access : read-write
PRI_N1 : For register NVIC_IPRn, the priority of interrupt number 4*n+1, or RES0 if the PE does not implement this interrupt
bits : 12 - 15 (4 bit)
access : read-write
PRI_N2 : For register NVIC_IPRn, the priority of interrupt number 4*n+2, or RES0 if the PE does not implement this interrupt
bits : 20 - 23 (4 bit)
access : read-write
PRI_N3 : For register NVIC_IPRn, the priority of interrupt number 4*n+3, or RES0 if the PE does not implement this interrupt
bits : 28 - 31 (4 bit)
access : read-write
Sets or reads interrupt priorities
address_offset : 0xE40C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRI_N0 : For register NVIC_IPRn, the priority of interrupt number 4*n+0, or RES0 if the PE does not implement this interrupt
bits : 4 - 7 (4 bit)
access : read-write
PRI_N1 : For register NVIC_IPRn, the priority of interrupt number 4*n+1, or RES0 if the PE does not implement this interrupt
bits : 12 - 15 (4 bit)
access : read-write
PRI_N2 : For register NVIC_IPRn, the priority of interrupt number 4*n+2, or RES0 if the PE does not implement this interrupt
bits : 20 - 23 (4 bit)
access : read-write
PRI_N3 : For register NVIC_IPRn, the priority of interrupt number 4*n+3, or RES0 if the PE does not implement this interrupt
bits : 28 - 31 (4 bit)
access : read-write
Sets or reads interrupt priorities
address_offset : 0xE410 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRI_N0 : For register NVIC_IPRn, the priority of interrupt number 4*n+0, or RES0 if the PE does not implement this interrupt
bits : 4 - 7 (4 bit)
access : read-write
PRI_N1 : For register NVIC_IPRn, the priority of interrupt number 4*n+1, or RES0 if the PE does not implement this interrupt
bits : 12 - 15 (4 bit)
access : read-write
PRI_N2 : For register NVIC_IPRn, the priority of interrupt number 4*n+2, or RES0 if the PE does not implement this interrupt
bits : 20 - 23 (4 bit)
access : read-write
PRI_N3 : For register NVIC_IPRn, the priority of interrupt number 4*n+3, or RES0 if the PE does not implement this interrupt
bits : 28 - 31 (4 bit)
access : read-write
Sets or reads interrupt priorities
address_offset : 0xE414 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRI_N0 : For register NVIC_IPRn, the priority of interrupt number 4*n+0, or RES0 if the PE does not implement this interrupt
bits : 4 - 7 (4 bit)
access : read-write
PRI_N1 : For register NVIC_IPRn, the priority of interrupt number 4*n+1, or RES0 if the PE does not implement this interrupt
bits : 12 - 15 (4 bit)
access : read-write
PRI_N2 : For register NVIC_IPRn, the priority of interrupt number 4*n+2, or RES0 if the PE does not implement this interrupt
bits : 20 - 23 (4 bit)
access : read-write
PRI_N3 : For register NVIC_IPRn, the priority of interrupt number 4*n+3, or RES0 if the PE does not implement this interrupt
bits : 28 - 31 (4 bit)
access : read-write
Sets or reads interrupt priorities
address_offset : 0xE418 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRI_N0 : For register NVIC_IPRn, the priority of interrupt number 4*n+0, or RES0 if the PE does not implement this interrupt
bits : 4 - 7 (4 bit)
access : read-write
PRI_N1 : For register NVIC_IPRn, the priority of interrupt number 4*n+1, or RES0 if the PE does not implement this interrupt
bits : 12 - 15 (4 bit)
access : read-write
PRI_N2 : For register NVIC_IPRn, the priority of interrupt number 4*n+2, or RES0 if the PE does not implement this interrupt
bits : 20 - 23 (4 bit)
access : read-write
PRI_N3 : For register NVIC_IPRn, the priority of interrupt number 4*n+3, or RES0 if the PE does not implement this interrupt
bits : 28 - 31 (4 bit)
access : read-write
Sets or reads interrupt priorities
address_offset : 0xE41C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRI_N0 : For register NVIC_IPRn, the priority of interrupt number 4*n+0, or RES0 if the PE does not implement this interrupt
bits : 4 - 7 (4 bit)
access : read-write
PRI_N1 : For register NVIC_IPRn, the priority of interrupt number 4*n+1, or RES0 if the PE does not implement this interrupt
bits : 12 - 15 (4 bit)
access : read-write
PRI_N2 : For register NVIC_IPRn, the priority of interrupt number 4*n+2, or RES0 if the PE does not implement this interrupt
bits : 20 - 23 (4 bit)
access : read-write
PRI_N3 : For register NVIC_IPRn, the priority of interrupt number 4*n+3, or RES0 if the PE does not implement this interrupt
bits : 28 - 31 (4 bit)
access : read-write
Sets or reads interrupt priorities
address_offset : 0xE420 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRI_N0 : For register NVIC_IPRn, the priority of interrupt number 4*n+0, or RES0 if the PE does not implement this interrupt
bits : 4 - 7 (4 bit)
access : read-write
PRI_N1 : For register NVIC_IPRn, the priority of interrupt number 4*n+1, or RES0 if the PE does not implement this interrupt
bits : 12 - 15 (4 bit)
access : read-write
PRI_N2 : For register NVIC_IPRn, the priority of interrupt number 4*n+2, or RES0 if the PE does not implement this interrupt
bits : 20 - 23 (4 bit)
access : read-write
PRI_N3 : For register NVIC_IPRn, the priority of interrupt number 4*n+3, or RES0 if the PE does not implement this interrupt
bits : 28 - 31 (4 bit)
access : read-write
Sets or reads interrupt priorities
address_offset : 0xE424 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRI_N0 : For register NVIC_IPRn, the priority of interrupt number 4*n+0, or RES0 if the PE does not implement this interrupt
bits : 4 - 7 (4 bit)
access : read-write
PRI_N1 : For register NVIC_IPRn, the priority of interrupt number 4*n+1, or RES0 if the PE does not implement this interrupt
bits : 12 - 15 (4 bit)
access : read-write
PRI_N2 : For register NVIC_IPRn, the priority of interrupt number 4*n+2, or RES0 if the PE does not implement this interrupt
bits : 20 - 23 (4 bit)
access : read-write
PRI_N3 : For register NVIC_IPRn, the priority of interrupt number 4*n+3, or RES0 if the PE does not implement this interrupt
bits : 28 - 31 (4 bit)
access : read-write
Sets or reads interrupt priorities
address_offset : 0xE428 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRI_N0 : For register NVIC_IPRn, the priority of interrupt number 4*n+0, or RES0 if the PE does not implement this interrupt
bits : 4 - 7 (4 bit)
access : read-write
PRI_N1 : For register NVIC_IPRn, the priority of interrupt number 4*n+1, or RES0 if the PE does not implement this interrupt
bits : 12 - 15 (4 bit)
access : read-write
PRI_N2 : For register NVIC_IPRn, the priority of interrupt number 4*n+2, or RES0 if the PE does not implement this interrupt
bits : 20 - 23 (4 bit)
access : read-write
PRI_N3 : For register NVIC_IPRn, the priority of interrupt number 4*n+3, or RES0 if the PE does not implement this interrupt
bits : 28 - 31 (4 bit)
access : read-write
Sets or reads interrupt priorities
address_offset : 0xE42C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRI_N0 : For register NVIC_IPRn, the priority of interrupt number 4*n+0, or RES0 if the PE does not implement this interrupt
bits : 4 - 7 (4 bit)
access : read-write
PRI_N1 : For register NVIC_IPRn, the priority of interrupt number 4*n+1, or RES0 if the PE does not implement this interrupt
bits : 12 - 15 (4 bit)
access : read-write
PRI_N2 : For register NVIC_IPRn, the priority of interrupt number 4*n+2, or RES0 if the PE does not implement this interrupt
bits : 20 - 23 (4 bit)
access : read-write
PRI_N3 : For register NVIC_IPRn, the priority of interrupt number 4*n+3, or RES0 if the PE does not implement this interrupt
bits : 28 - 31 (4 bit)
access : read-write
Sets or reads interrupt priorities
address_offset : 0xE430 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRI_N0 : For register NVIC_IPRn, the priority of interrupt number 4*n+0, or RES0 if the PE does not implement this interrupt
bits : 4 - 7 (4 bit)
access : read-write
PRI_N1 : For register NVIC_IPRn, the priority of interrupt number 4*n+1, or RES0 if the PE does not implement this interrupt
bits : 12 - 15 (4 bit)
access : read-write
PRI_N2 : For register NVIC_IPRn, the priority of interrupt number 4*n+2, or RES0 if the PE does not implement this interrupt
bits : 20 - 23 (4 bit)
access : read-write
PRI_N3 : For register NVIC_IPRn, the priority of interrupt number 4*n+3, or RES0 if the PE does not implement this interrupt
bits : 28 - 31 (4 bit)
access : read-write
Sets or reads interrupt priorities
address_offset : 0xE434 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRI_N0 : For register NVIC_IPRn, the priority of interrupt number 4*n+0, or RES0 if the PE does not implement this interrupt
bits : 4 - 7 (4 bit)
access : read-write
PRI_N1 : For register NVIC_IPRn, the priority of interrupt number 4*n+1, or RES0 if the PE does not implement this interrupt
bits : 12 - 15 (4 bit)
access : read-write
PRI_N2 : For register NVIC_IPRn, the priority of interrupt number 4*n+2, or RES0 if the PE does not implement this interrupt
bits : 20 - 23 (4 bit)
access : read-write
PRI_N3 : For register NVIC_IPRn, the priority of interrupt number 4*n+3, or RES0 if the PE does not implement this interrupt
bits : 28 - 31 (4 bit)
access : read-write
Sets or reads interrupt priorities
address_offset : 0xE438 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRI_N0 : For register NVIC_IPRn, the priority of interrupt number 4*n+0, or RES0 if the PE does not implement this interrupt
bits : 4 - 7 (4 bit)
access : read-write
PRI_N1 : For register NVIC_IPRn, the priority of interrupt number 4*n+1, or RES0 if the PE does not implement this interrupt
bits : 12 - 15 (4 bit)
access : read-write
PRI_N2 : For register NVIC_IPRn, the priority of interrupt number 4*n+2, or RES0 if the PE does not implement this interrupt
bits : 20 - 23 (4 bit)
access : read-write
PRI_N3 : For register NVIC_IPRn, the priority of interrupt number 4*n+3, or RES0 if the PE does not implement this interrupt
bits : 28 - 31 (4 bit)
access : read-write
Sets or reads interrupt priorities
address_offset : 0xE43C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRI_N0 : For register NVIC_IPRn, the priority of interrupt number 4*n+0, or RES0 if the PE does not implement this interrupt
bits : 4 - 7 (4 bit)
access : read-write
PRI_N1 : For register NVIC_IPRn, the priority of interrupt number 4*n+1, or RES0 if the PE does not implement this interrupt
bits : 12 - 15 (4 bit)
access : read-write
PRI_N2 : For register NVIC_IPRn, the priority of interrupt number 4*n+2, or RES0 if the PE does not implement this interrupt
bits : 20 - 23 (4 bit)
access : read-write
PRI_N3 : For register NVIC_IPRn, the priority of interrupt number 4*n+3, or RES0 if the PE does not implement this interrupt
bits : 28 - 31 (4 bit)
access : read-write
Configures and controls transfers through the ITM interface
address_offset : 0xE80 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ITMENA : Enables the ITM
bits : 0 - 0 (1 bit)
access : read-write
TSENA : Enables Local timestamp generation
bits : 1 - 1 (1 bit)
access : read-write
SYNCENA : Enables Synchronization packet transmission for a synchronous TPIU
bits : 2 - 2 (1 bit)
access : read-write
TXENA : Enables forwarding of hardware event packet from the DWT unit to the ITM for output to the TPIU
bits : 3 - 3 (1 bit)
access : read-write
SWOENA : Enables asynchronous clocking of the timestamp counter
bits : 4 - 4 (1 bit)
access : read-write
STALLENA : Stall the PE to guarantee delivery of Data Trace packets.
bits : 5 - 5 (1 bit)
access : read-write
TSPRESCALE : Local timestamp prescaler, used with the trace packet reference clock
bits : 8 - 9 (2 bit)
access : read-write
GTSFREQ : Defines how often the ITM generates a global timestamp, based on the global timestamp clock frequency, or disables generation of global timestamps
bits : 10 - 11 (2 bit)
access : read-write
TRACEBUSID : Identifier for multi-source trace stream formatting. If multi-source trace is in use, the debugger must write a unique non-zero trace ID value to this field
bits : 16 - 22 (7 bit)
access : read-write
BUSY : Indicates whether the ITM is currently processing events
bits : 23 - 23 (1 bit)
access : read-only
Provides identification information for the PE, including an implementer code for the device and a device ID number
address_offset : 0xED00 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
REVISION : IMPLEMENTATION DEFINED revision number for the device
bits : 0 - 3 (4 bit)
access : read-only
PARTNO : IMPLEMENTATION DEFINED primary part number for the device
bits : 4 - 15 (12 bit)
access : read-only
ARCHITECTURE : Defines the Architecture implemented by the PE
bits : 16 - 19 (4 bit)
access : read-only
VARIANT : IMPLEMENTATION DEFINED variant number. Typically, this field is used to distinguish between different product variants, or major revisions of a product
bits : 20 - 23 (4 bit)
access : read-only
IMPLEMENTER : This field must hold an implementer code that has been assigned by ARM
bits : 24 - 31 (8 bit)
access : read-only
Controls and provides status information for NMI, PendSV, SysTick and interrupts
address_offset : 0xED04 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VECTACTIVE : The exception number of the current executing exception
bits : 0 - 8 (9 bit)
access : read-only
RETTOBASE : In Handler mode, indicates whether there is more than one active exception
bits : 11 - 11 (1 bit)
access : read-only
VECTPENDING : The exception number of the highest priority pending and enabled interrupt
bits : 12 - 20 (9 bit)
access : read-only
ISRPENDING : Indicates whether an external interrupt, generated by the NVIC, is pending
bits : 22 - 22 (1 bit)
access : read-only
ISRPREEMPT : Indicates whether a pending exception will be serviced on exit from debug halt state
bits : 23 - 23 (1 bit)
access : read-only
STTNS : Controls whether in a single SysTick implementation, the SysTick is Secure or Non-secure
bits : 24 - 24 (1 bit)
access : read-write
PENDSTCLR : Allows the SysTick exception pend state to be cleared `FTSSS
bits : 25 - 25 (1 bit)
access : read-write
PENDSTSET : Indicates whether the SysTick `FTSSS exception is pending
bits : 26 - 26 (1 bit)
access : read-only
PENDSVCLR : Allows the PendSV exception pend state to be cleared `FTSSS
bits : 27 - 27 (1 bit)
access : read-write
PENDSVSET : Indicates whether the PendSV `FTSSS exception is pending
bits : 28 - 28 (1 bit)
access : read-only
PENDNMICLR : Allows the NMI exception pend state to be cleared
bits : 30 - 30 (1 bit)
access : read-write
PENDNMISET : Indicates whether the NMI exception is pending
bits : 31 - 31 (1 bit)
access : read-only
The VTOR indicates the offset of the vector table base address from memory address 0x00000000.
address_offset : 0xED08 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TBLOFF : Vector table base offset field. It contains bits[31:7] of the offset of the table base from the bottom of the memory map.
bits : 7 - 31 (25 bit)
access : read-write
Use the Application Interrupt and Reset Control Register to: determine data endianness, clear all active state information from debug halt mode, request a system reset.
address_offset : 0xED0C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VECTCLRACTIVE : Clears all active state information for fixed and configurable exceptions. This bit: is self-clearing, can only be set by the DAP when the core is halted. When set: clears all active exception status of the processor, forces a return to Thread mode, forces an IPSR of 0. A debugger must re-initialize the stack.
bits : 1 - 1 (1 bit)
access : read-write
SYSRESETREQ : Writing 1 to this bit causes the SYSRESETREQ signal to the outer system to be asserted to request a reset. The intention is to force a large system reset of all major components except for debug. The C_HALT bit in the DHCSR is cleared as a result of the system reset requested. The debugger does not lose contact with the device.
bits : 2 - 2 (1 bit)
access : read-write
SYSRESETREQS : System reset request, Secure state only.
0 SYSRESETREQ functionality is available to both Security states.
1 SYSRESETREQ functionality is only available to Secure state.
bits : 3 - 3 (1 bit)
access : read-write
PRIGROUP : Interrupt priority grouping field. This field determines the split of group priority from subpriority.
See https://developer.arm.com/documentation/100235/0004/the-cortex-m33-peripherals/system-control-block/application-interrupt-and-reset-control-register?lang=en
bits : 8 - 10 (3 bit)
access : read-write
BFHFNMINS : BusFault, HardFault, and NMI Non-secure enable.
0 BusFault, HardFault, and NMI are Secure.
1 BusFault and NMI are Non-secure and exceptions can target Non-secure HardFault.
bits : 13 - 13 (1 bit)
access : read-write
PRIS : Prioritize Secure exceptions. The value of this bit defines whether Secure exception priority boosting is enabled.
0 Priority ranges of Secure and Non-secure exceptions are identical.
1 Non-secure exceptions are de-prioritized.
bits : 14 - 14 (1 bit)
access : read-write
ENDIANESS : Data endianness implemented:
0 = Little-endian.
bits : 15 - 15 (1 bit)
access : read-only
VECTKEY : Register key:
Reads as Unknown
On writes, write 0x05FA to VECTKEY, otherwise the write is ignored.
bits : 16 - 31 (16 bit)
access : read-write
System Control Register. Use the System Control Register for power-management functions: signal to the system when the processor can enter a low power state, control how the processor enters and exits low power states.
address_offset : 0xED10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SLEEPONEXIT : Indicates sleep-on-exit when returning from Handler mode to Thread mode:
0 = Do not sleep when returning to Thread mode.
1 = Enter sleep, or deep sleep, on return from an ISR to Thread mode.
Setting this bit to 1 enables an interrupt driven application to avoid returning to an empty main application.
bits : 1 - 1 (1 bit)
access : read-write
SLEEPDEEP : Controls whether the processor uses sleep or deep sleep as its low power mode:
0 = Sleep.
1 = Deep sleep.
bits : 2 - 2 (1 bit)
access : read-write
SLEEPDEEPS : 0 SLEEPDEEP is available to both security states
1 SLEEPDEEP is only available to Secure state
bits : 3 - 3 (1 bit)
access : read-write
SEVONPEND : Send Event on Pending bit:
0 = Only enabled interrupts or events can wakeup the processor, disabled interrupts are excluded.
1 = Enabled events and all interrupts, including disabled interrupts, can wakeup the processor.
When an event or interrupt becomes pending, the event signal wakes up the processor from WFE. If the
processor is not waiting for an event, the event is registered and affects the next WFE.
The processor also wakes up on execution of an SEV instruction or an external event.
bits : 4 - 4 (1 bit)
access : read-write
Sets or returns configuration and control data
address_offset : 0xED14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RES1_1 : Reserved, RES1
bits : 0 - 0 (1 bit)
access : read-only
USERSETMPEND : Determines whether unprivileged accesses are permitted to pend interrupts via the STIR
bits : 1 - 1 (1 bit)
access : read-write
UNALIGN_TRP : Controls the trapping of unaligned word or halfword accesses
bits : 3 - 3 (1 bit)
access : read-write
DIV_0_TRP : Controls the generation of a DIVBYZERO UsageFault when attempting to perform integer division by zero
bits : 4 - 4 (1 bit)
access : read-write
BFHFNMIGN : Determines the effect of precise BusFaults on handlers running at a requested priority less than 0
bits : 8 - 8 (1 bit)
access : read-write
RES1 : Reserved, RES1
bits : 9 - 9 (1 bit)
access : read-only
STKOFHFNMIGN : Controls the effect of a stack limit violation while executing at a requested priority less than 0
bits : 10 - 10 (1 bit)
access : read-write
DC : Enables data caching of all data accesses to Normal memory `FTSSS
bits : 16 - 16 (1 bit)
access : read-only
IC : This is a global enable bit for instruction caches in the selected Security state
bits : 17 - 17 (1 bit)
access : read-only
BP : Enables program flow prediction `FTSSS
bits : 18 - 18 (1 bit)
access : read-only
Sets or returns priority for system handlers 4 - 7
address_offset : 0xED18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRI_4_3 : Priority of system handler 4, SecureFault
bits : 5 - 7 (3 bit)
access : read-write
PRI_5_3 : Priority of system handler 5, SecureFault
bits : 13 - 15 (3 bit)
access : read-write
PRI_6_3 : Priority of system handler 6, SecureFault
bits : 21 - 23 (3 bit)
access : read-write
PRI_7_3 : Priority of system handler 7, SecureFault
bits : 29 - 31 (3 bit)
access : read-write
Sets or returns priority for system handlers 8 - 11
address_offset : 0xED1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRI_8 : Reserved, RES0
bits : 0 - 7 (8 bit)
access : read-only
PRI_9 : Reserved, RES0
bits : 8 - 15 (8 bit)
access : read-only
PRI_10 : Reserved, RES0
bits : 16 - 23 (8 bit)
access : read-only
PRI_11_3 : Priority of system handler 11, SecureFault
bits : 29 - 31 (3 bit)
access : read-write
Sets or returns priority for system handlers 12 - 15
address_offset : 0xED20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRI_12_3 : Priority of system handler 12, SecureFault
bits : 5 - 7 (3 bit)
access : read-write
PRI_13 : Reserved, RES0
bits : 8 - 15 (8 bit)
access : read-only
PRI_14_3 : Priority of system handler 14, SecureFault
bits : 21 - 23 (3 bit)
access : read-write
PRI_15_3 : Priority of system handler 15, SecureFault
bits : 29 - 31 (3 bit)
access : read-write
Provides access to the active and pending status of system exceptions
address_offset : 0xED24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MEMFAULTACT : `IAAMO the active state of the MemManage exception `FTSSS
bits : 0 - 0 (1 bit)
access : read-write
BUSFAULTACT : `IAAMO the active state of the BusFault exception
bits : 1 - 1 (1 bit)
access : read-write
HARDFAULTACT : Indicates and allows limited modification of the active state of the HardFault exception `FTSSS
bits : 2 - 2 (1 bit)
access : read-write
USGFAULTACT : `IAAMO the active state of the UsageFault exception `FTSSS
bits : 3 - 3 (1 bit)
access : read-write
SECUREFAULTACT : `IAAMO the active state of the SecureFault exception
bits : 4 - 4 (1 bit)
access : read-write
NMIACT : `IAAMO the active state of the NMI exception
bits : 5 - 5 (1 bit)
access : read-write
SVCALLACT : `IAAMO the active state of the SVCall exception `FTSSS
bits : 7 - 7 (1 bit)
access : read-write
MONITORACT : `IAAMO the active state of the DebugMonitor exception
bits : 8 - 8 (1 bit)
access : read-write
PENDSVACT : `IAAMO the active state of the PendSV exception `FTSSS
bits : 10 - 10 (1 bit)
access : read-write
SYSTICKACT : `IAAMO the active state of the SysTick exception `FTSSS
bits : 11 - 11 (1 bit)
access : read-write
USGFAULTPENDED : The UsageFault exception is banked between Security states, `IAAMO the pending state of the UsageFault exception `FTSSS
bits : 12 - 12 (1 bit)
access : read-write
MEMFAULTPENDED : `IAAMO the pending state of the MemManage exception `FTSSS
bits : 13 - 13 (1 bit)
access : read-write
BUSFAULTPENDED : `IAAMO the pending state of the BusFault exception
bits : 14 - 14 (1 bit)
access : read-write
SVCALLPENDED : `IAAMO the pending state of the SVCall exception `FTSSS
bits : 15 - 15 (1 bit)
access : read-write
MEMFAULTENA : `DW the MemManage exception is enabled `FTSSS
bits : 16 - 16 (1 bit)
access : read-write
BUSFAULTENA : `DW the BusFault exception is enabled
bits : 17 - 17 (1 bit)
access : read-write
USGFAULTENA : `DW the UsageFault exception is enabled `FTSSS
bits : 18 - 18 (1 bit)
access : read-write
SECUREFAULTENA : `DW the SecureFault exception is enabled
bits : 19 - 19 (1 bit)
access : read-write
SECUREFAULTPENDED : `IAAMO the pending state of the SecureFault exception
bits : 20 - 20 (1 bit)
access : read-write
HARDFAULTPENDED : `IAAMO the pending state of the HardFault exception `CTTSSS
bits : 21 - 21 (1 bit)
access : read-write
Contains the three Configurable Fault Status Registers.
31:16 UFSR: Provides information on UsageFault exceptions
15:8 BFSR: Provides information on BusFault exceptions
7:0 MMFSR: Provides information on MemManage exceptions
address_offset : 0xED28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MMFSR : Provides information on MemManage exceptions
bits : 0 - 7 (8 bit)
access : read-write
BFSR_IBUSERR : Records whether a BusFault on an instruction prefetch has occurred
bits : 8 - 8 (1 bit)
access : read-write
BFSR_PRECISERR : Records whether a precise data access error has occurred
bits : 9 - 9 (1 bit)
access : read-write
BFSR_IMPRECISERR : Records whether an imprecise data access error has occurred
bits : 10 - 10 (1 bit)
access : read-write
BFSR_UNSTKERR : Records whether a derived BusFault occurred during exception return unstacking
bits : 11 - 11 (1 bit)
access : read-write
BFSR_STKERR : Records whether a derived BusFault occurred during exception entry stacking
bits : 12 - 12 (1 bit)
access : read-write
BFSR_LSPERR : Records whether a BusFault occurred during FP lazy state preservation
bits : 13 - 13 (1 bit)
access : read-write
BFSR_BFARVALID : Indicates validity of the contents of the BFAR register
bits : 15 - 15 (1 bit)
access : read-write
UFSR_UNDEFINSTR : Sticky flag indicating whether an undefined instruction error has occurred
bits : 16 - 16 (1 bit)
access : read-write
UFSR_INVSTATE : Sticky flag indicating whether an EPSR.T or EPSR.IT validity error has occurred
bits : 17 - 17 (1 bit)
access : read-write
UFSR_INVPC : Sticky flag indicating whether an integrity check error has occurred
bits : 18 - 18 (1 bit)
access : read-write
UFSR_NOCP : Sticky flag indicating whether a coprocessor disabled or not present error has occurred
bits : 19 - 19 (1 bit)
access : read-write
UFSR_STKOF : Sticky flag indicating whether a stack overflow error has occurred
bits : 20 - 20 (1 bit)
access : read-write
UFSR_UNALIGNED : Sticky flag indicating whether an unaligned access error has occurred
bits : 24 - 24 (1 bit)
access : read-write
UFSR_DIVBYZERO : Sticky flag indicating whether an integer division by zero error has occurred
bits : 25 - 25 (1 bit)
access : read-write
Shows the cause of any HardFaults
address_offset : 0xED2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VECTTBL : Indicates when a fault has occurred because of a vector table read error on exception processing
bits : 1 - 1 (1 bit)
access : read-write
FORCED : Indicates that a fault with configurable priority has been escalated to a HardFault exception, because it could not be made active, because of priority, or because it was disabled
bits : 30 - 30 (1 bit)
access : read-write
DEBUGEVT : Indicates when a Debug event has occurred
bits : 31 - 31 (1 bit)
access : read-write
Shows which debug event occurred
address_offset : 0xED30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HALTED : Sticky flag indicating that a Halt request debug event or Step debug event has occurred
bits : 0 - 0 (1 bit)
access : read-write
BKPT : Sticky flag indicating whether a Breakpoint debug event has occurred
bits : 1 - 1 (1 bit)
access : read-write
DWTTRAP : Sticky flag indicating whether a Watchpoint debug event has occurred
bits : 2 - 2 (1 bit)
access : read-write
VCATCH : Sticky flag indicating whether a Vector catch debug event has occurred
bits : 3 - 3 (1 bit)
access : read-write
EXTERNAL : Sticky flag indicating whether an External debug request debug event has occurred
bits : 4 - 4 (1 bit)
access : read-write
Shows the address of the memory location that caused an MPU fault
address_offset : 0xED34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADDRESS : This register is updated with the address of a location that produced a MemManage fault. The MMFSR shows the cause of the fault, and whether this field is valid. This field is valid only when MMFSR.MMARVALID is set, otherwise it is UNKNOWN
bits : 0 - 31 (32 bit)
access : read-write
Shows the address associated with a precise data access BusFault
address_offset : 0xED38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADDRESS : This register is updated with the address of a location that produced a BusFault. The BFSR shows the reason for the fault. This field is valid only when BFSR.BFARVALID is set, otherwise it is UNKNOWN
bits : 0 - 31 (32 bit)
access : read-write
Gives top-level information about the instruction set supported by the PE
address_offset : 0xED40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
STATE0 : A32 instruction set support
bits : 0 - 3 (4 bit)
access : read-only
STATE1 : T32 instruction set support
bits : 4 - 7 (4 bit)
access : read-only
Gives information about the programmers' model and Extensions support
address_offset : 0xED44 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SECURITY : Identifies whether the Security Extension is implemented
bits : 4 - 7 (4 bit)
access : read-only
MPROGMOD : Identifies support for the M-Profile programmers' model support
bits : 8 - 11 (4 bit)
access : read-only
Provides top level information about the debug system
address_offset : 0xED48 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MPROFDBG : Indicates the supported M-profile debug architecture
bits : 20 - 23 (4 bit)
access : read-only
Provides information about the IMPLEMENTATION DEFINED features of the PE
address_offset : 0xED4C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IMPDEF0 : IMPLEMENTATION DEFINED meaning
bits : 0 - 3 (4 bit)
access : read-only
IMPDEF1 : IMPLEMENTATION DEFINED meaning
bits : 4 - 7 (4 bit)
access : read-only
IMPDEF2 : IMPLEMENTATION DEFINED meaning
bits : 8 - 11 (4 bit)
access : read-only
IMPDEF3 : IMPLEMENTATION DEFINED meaning
bits : 12 - 15 (4 bit)
access : read-only
Provides information about the implemented memory model and memory management support
address_offset : 0xED50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PMSA : Indicates support for the protected memory system architecture (PMSA)
bits : 4 - 7 (4 bit)
access : read-only
OUTERSHR : Indicates the outermost shareability domain implemented
bits : 8 - 11 (4 bit)
access : read-only
SHARELVL : Indicates the number of shareability levels implemented
bits : 12 - 15 (4 bit)
access : read-only
TCM : Indicates support for tightly coupled memories (TCMs)
bits : 16 - 19 (4 bit)
access : read-only
AUXREG : Indicates support for Auxiliary Control Registers
bits : 20 - 23 (4 bit)
access : read-only
Provides information about the implemented memory model and memory management support
address_offset : 0xED54 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ID_MMFR1 :
bits : 0 - 31 (32 bit)
access : read-write
Provides information about the implemented memory model and memory management support
address_offset : 0xED58 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WFISTALL : Indicates the support for Wait For Interrupt (WFI) stalling
bits : 24 - 27 (4 bit)
access : read-only
Provides information about the implemented memory model and memory management support
address_offset : 0xED5C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CMAINTVA : Indicates the supported cache maintenance operations by address
bits : 0 - 3 (4 bit)
access : read-only
CMAINTSW : Indicates the supported cache maintenance operations by set/way
bits : 4 - 7 (4 bit)
access : read-only
BPMAINT : Indicates the supported branch predictor maintenance
bits : 8 - 11 (4 bit)
access : read-only
Provides information about the instruction set implemented by the PE
address_offset : 0xED60 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BITCOUNT : Indicates the supported bit count instructions
bits : 4 - 7 (4 bit)
access : read-only
BITFIELD : Indicates the supported bit field instructions
bits : 8 - 11 (4 bit)
access : read-only
CMPBRANCH : Indicates the supported combined Compare and Branch instructions
bits : 12 - 15 (4 bit)
access : read-only
COPROC : Indicates the supported Coprocessor instructions
bits : 16 - 19 (4 bit)
access : read-only
DEBUG : Indicates the implemented Debug instructions
bits : 20 - 23 (4 bit)
access : read-only
DIVIDE : Indicates the supported Divide instructions
bits : 24 - 27 (4 bit)
access : read-only
Provides information about the instruction set implemented by the PE
address_offset : 0xED64 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EXTEND : Indicates the implemented Extend instructions
bits : 12 - 15 (4 bit)
access : read-only
IFTHEN : Indicates the implemented If-Then instructions
bits : 16 - 19 (4 bit)
access : read-only
IMMEDIATE : Indicates the implemented for data-processing instructions with long immediates
bits : 20 - 23 (4 bit)
access : read-only
INTERWORK : Indicates the implemented Interworking instructions
bits : 24 - 27 (4 bit)
access : read-only
Provides information about the instruction set implemented by the PE
address_offset : 0xED68 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LOADSTORE : Indicates the implemented additional load/store instructions
bits : 0 - 3 (4 bit)
access : read-only
MEMHINT : Indicates the implemented Memory Hint instructions
bits : 4 - 7 (4 bit)
access : read-only
MULTIACCESSINT : Indicates the support for interruptible multi-access instructions
bits : 8 - 11 (4 bit)
access : read-only
MULT : Indicates the implemented additional Multiply instructions
bits : 12 - 15 (4 bit)
access : read-only
MULTS : Indicates the implemented advanced signed Multiply instructions
bits : 16 - 19 (4 bit)
access : read-only
MULTU : Indicates the implemented advanced unsigned Multiply instructions
bits : 20 - 23 (4 bit)
access : read-only
REVERSAL : Indicates the implemented Reversal instructions
bits : 28 - 31 (4 bit)
access : read-only
Provides information about the instruction set implemented by the PE
address_offset : 0xED6C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SATURATE : Indicates the implemented saturating instructions
bits : 0 - 3 (4 bit)
access : read-only
SIMD : Indicates the implemented SIMD instructions
bits : 4 - 7 (4 bit)
access : read-only
SVC : Indicates the implemented SVC instructions
bits : 8 - 11 (4 bit)
access : read-only
SYNCHPRIM : Used in conjunction with ID_ISAR4.SynchPrim_frac to indicate the implemented Synchronization Primitive instructions
bits : 12 - 15 (4 bit)
access : read-only
TABBRANCH : Indicates the implemented Table Branch instructions
bits : 16 - 19 (4 bit)
access : read-only
T32COPY : Indicates the support for T32 non flag-setting MOV instructions
bits : 20 - 23 (4 bit)
access : read-only
TRUENOP : Indicates the implemented true NOP instructions
bits : 24 - 27 (4 bit)
access : read-only
Provides information about the instruction set implemented by the PE
address_offset : 0xED70 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
UNPRIV : Indicates the implemented unprivileged instructions
bits : 0 - 3 (4 bit)
access : read-only
WITHSHIFTS : Indicates the support for writeback addressing modes
bits : 4 - 7 (4 bit)
access : read-only
WRITEBACK : Indicates the support for writeback addressing modes
bits : 8 - 11 (4 bit)
access : read-only
BARRIER : Indicates the implemented Barrier instructions
bits : 16 - 19 (4 bit)
access : read-only
SYNCPRIM_FRAC : Used in conjunction with ID_ISAR3.SynchPrim to indicate the implemented Synchronization Primitive instructions
bits : 20 - 23 (4 bit)
access : read-only
PSR_M : Indicates the implemented M profile instructions to modify the PSRs
bits : 24 - 27 (4 bit)
access : read-only
Provides information about the instruction set implemented by the PE
address_offset : 0xED74 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ID_ISAR5 :
bits : 0 - 31 (32 bit)
access : read-write
Provides information about the architecture of the caches. CTR is RES0 if CLIDR is zero.
address_offset : 0xED7C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IMINLINE : Log2 of the number of words in the smallest cache line of all the instruction caches that are controlled by the PE
bits : 0 - 3 (4 bit)
access : read-only
RES1_1 : Reserved, RES1
bits : 14 - 15 (2 bit)
access : read-only
DMINLINE : Log2 of the number of words in the smallest cache line of all the data caches and unified caches that are controlled by the PE
bits : 16 - 19 (4 bit)
access : read-only
ERG : Log2 of the number of words of the maximum size of the reservation granule that has been implemented for the Load-Exclusive and Store-Exclusive instructions
bits : 20 - 23 (4 bit)
access : read-only
CWG : Log2 of the number of words of the maximum size of memory that can be overwritten as a result of the eviction of a cache entry that has had a memory location in it modified
bits : 24 - 27 (4 bit)
access : read-only
RES1 : Reserved, RES1
bits : 31 - 31 (1 bit)
access : read-only
Specifies the access privileges for coprocessors and the FP Extension
address_offset : 0xED88 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CP0 : Controls access privileges for coprocessor 0
bits : 0 - 1 (2 bit)
access : read-write
CP1 : Controls access privileges for coprocessor 1
bits : 2 - 3 (2 bit)
access : read-write
CP2 : Controls access privileges for coprocessor 2
bits : 4 - 5 (2 bit)
access : read-write
CP3 : Controls access privileges for coprocessor 3
bits : 6 - 7 (2 bit)
access : read-write
CP4 : Controls access privileges for coprocessor 4
bits : 8 - 9 (2 bit)
access : read-write
CP5 : Controls access privileges for coprocessor 5
bits : 10 - 11 (2 bit)
access : read-write
CP6 : Controls access privileges for coprocessor 6
bits : 12 - 13 (2 bit)
access : read-write
CP7 : Controls access privileges for coprocessor 7
bits : 14 - 15 (2 bit)
access : read-write
CP10 : Defines the access rights for the floating-point functionality
bits : 20 - 21 (2 bit)
access : read-write
CP11 : The value in this field is ignored. If the implementation does not include the FP Extension, this field is RAZ/WI. If the value of this bit is not programmed to the same value as the CP10 field, then the value is UNKNOWN
bits : 22 - 23 (2 bit)
access : read-write
Defines the Non-secure access permissions for both the FP Extension and coprocessors CP0 to CP7
address_offset : 0xED8C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CP0 : Enables Non-secure access to coprocessor CP0
bits : 0 - 0 (1 bit)
access : read-write
CP1 : Enables Non-secure access to coprocessor CP1
bits : 1 - 1 (1 bit)
access : read-write
CP2 : Enables Non-secure access to coprocessor CP2
bits : 2 - 2 (1 bit)
access : read-write
CP3 : Enables Non-secure access to coprocessor CP3
bits : 3 - 3 (1 bit)
access : read-write
CP4 : Enables Non-secure access to coprocessor CP4
bits : 4 - 4 (1 bit)
access : read-write
CP5 : Enables Non-secure access to coprocessor CP5
bits : 5 - 5 (1 bit)
access : read-write
CP6 : Enables Non-secure access to coprocessor CP6
bits : 6 - 6 (1 bit)
access : read-write
CP7 : Enables Non-secure access to coprocessor CP7
bits : 7 - 7 (1 bit)
access : read-write
CP10 : Enables Non-secure access to the Floating-point Extension
bits : 10 - 10 (1 bit)
access : read-write
CP11 : Enables Non-secure access to the Floating-point Extension
bits : 11 - 11 (1 bit)
access : read-write
The MPU Type Register indicates how many regions the MPU `FTSSS supports
address_offset : 0xED90 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SEPARATE : Indicates support for separate instructions and data address regions
bits : 0 - 0 (1 bit)
access : read-only
DREGION : Number of regions supported by the MPU
bits : 8 - 15 (8 bit)
access : read-only
Enables the MPU and, when the MPU is enabled, controls whether the default memory map is enabled as a background region for privileged accesses, and whether the MPU is enabled for HardFaults, NMIs, and exception handlers when FAULTMASK is set to 1
address_offset : 0xED94 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ENABLE : Enables the MPU
bits : 0 - 0 (1 bit)
access : read-write
HFNMIENA : Controls whether handlers executing with priority less than 0 access memory with the MPU enabled or disabled. This applies to HardFaults, NMIs, and exception handlers when FAULTMASK is set to 1
bits : 1 - 1 (1 bit)
access : read-write
PRIVDEFENA : Controls whether the default memory map is enabled for privileged software
bits : 2 - 2 (1 bit)
access : read-write
Selects the region currently accessed by MPU_RBAR and MPU_RLAR
address_offset : 0xED98 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
REGION : Indicates the memory region accessed by MPU_RBAR and MPU_RLAR
bits : 0 - 2 (3 bit)
access : read-write
Provides indirect read and write access to the base address of the currently selected MPU region `FTSSS
address_offset : 0xED9C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
XN : Defines whether code can be executed from this region
bits : 0 - 0 (1 bit)
access : read-write
AP : Defines the access permissions for this region
bits : 1 - 2 (2 bit)
access : read-write
SH : Defines the Shareability domain of this region for Normal memory
bits : 3 - 4 (2 bit)
access : read-write
BASE : Contains bits [31:5] of the lower inclusive limit of the selected MPU memory region. This value is zero extended to provide the base address to be checked against
bits : 5 - 31 (27 bit)
access : read-write
Provides indirect read and write access to the limit address of the currently selected MPU region `FTSSS
address_offset : 0xEDA0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : Region enable
bits : 0 - 0 (1 bit)
access : read-write
ATTRINDX : Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields
bits : 1 - 3 (3 bit)
access : read-write
LIMIT : Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region. This value is postfixed with 0x1F to provide the limit address to be checked against
bits : 5 - 31 (27 bit)
access : read-write
Provides indirect read and write access to the base address of the MPU region selected by MPU_RNR[7:2]:(1[1:0]) `FTSSS
address_offset : 0xEDA4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
XN : Defines whether code can be executed from this region
bits : 0 - 0 (1 bit)
access : read-write
AP : Defines the access permissions for this region
bits : 1 - 2 (2 bit)
access : read-write
SH : Defines the Shareability domain of this region for Normal memory
bits : 3 - 4 (2 bit)
access : read-write
BASE : Contains bits [31:5] of the lower inclusive limit of the selected MPU memory region. This value is zero extended to provide the base address to be checked against
bits : 5 - 31 (27 bit)
access : read-write
Provides indirect read and write access to the limit address of the currently selected MPU region selected by MPU_RNR[7:2]:(1[1:0]) `FTSSS
address_offset : 0xEDA8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : Region enable
bits : 0 - 0 (1 bit)
access : read-write
ATTRINDX : Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields
bits : 1 - 3 (3 bit)
access : read-write
LIMIT : Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region. This value is postfixed with 0x1F to provide the limit address to be checked against
bits : 5 - 31 (27 bit)
access : read-write
Provides indirect read and write access to the base address of the MPU region selected by MPU_RNR[7:2]:(2[1:0]) `FTSSS
address_offset : 0xEDAC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
XN : Defines whether code can be executed from this region
bits : 0 - 0 (1 bit)
access : read-write
AP : Defines the access permissions for this region
bits : 1 - 2 (2 bit)
access : read-write
SH : Defines the Shareability domain of this region for Normal memory
bits : 3 - 4 (2 bit)
access : read-write
BASE : Contains bits [31:5] of the lower inclusive limit of the selected MPU memory region. This value is zero extended to provide the base address to be checked against
bits : 5 - 31 (27 bit)
access : read-write
Provides indirect read and write access to the limit address of the currently selected MPU region selected by MPU_RNR[7:2]:(2[1:0]) `FTSSS
address_offset : 0xEDB0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : Region enable
bits : 0 - 0 (1 bit)
access : read-write
ATTRINDX : Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields
bits : 1 - 3 (3 bit)
access : read-write
LIMIT : Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region. This value is postfixed with 0x1F to provide the limit address to be checked against
bits : 5 - 31 (27 bit)
access : read-write
Provides indirect read and write access to the base address of the MPU region selected by MPU_RNR[7:2]:(3[1:0]) `FTSSS
address_offset : 0xEDB4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
XN : Defines whether code can be executed from this region
bits : 0 - 0 (1 bit)
access : read-write
AP : Defines the access permissions for this region
bits : 1 - 2 (2 bit)
access : read-write
SH : Defines the Shareability domain of this region for Normal memory
bits : 3 - 4 (2 bit)
access : read-write
BASE : Contains bits [31:5] of the lower inclusive limit of the selected MPU memory region. This value is zero extended to provide the base address to be checked against
bits : 5 - 31 (27 bit)
access : read-write
Provides indirect read and write access to the limit address of the currently selected MPU region selected by MPU_RNR[7:2]:(3[1:0]) `FTSSS
address_offset : 0xEDB8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : Region enable
bits : 0 - 0 (1 bit)
access : read-write
ATTRINDX : Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields
bits : 1 - 3 (3 bit)
access : read-write
LIMIT : Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region. This value is postfixed with 0x1F to provide the limit address to be checked against
bits : 5 - 31 (27 bit)
access : read-write
Along with MPU_MAIR1, provides the memory attribute encodings corresponding to the AttrIndex values
address_offset : 0xEDC0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ATTR0 : Memory attribute encoding for MPU regions with an AttrIndex of 0
bits : 0 - 7 (8 bit)
access : read-write
ATTR1 : Memory attribute encoding for MPU regions with an AttrIndex of 1
bits : 8 - 15 (8 bit)
access : read-write
ATTR2 : Memory attribute encoding for MPU regions with an AttrIndex of 2
bits : 16 - 23 (8 bit)
access : read-write
ATTR3 : Memory attribute encoding for MPU regions with an AttrIndex of 3
bits : 24 - 31 (8 bit)
access : read-write
Along with MPU_MAIR0, provides the memory attribute encodings corresponding to the AttrIndex values
address_offset : 0xEDC4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ATTR4 : Memory attribute encoding for MPU regions with an AttrIndex of 4
bits : 0 - 7 (8 bit)
access : read-write
ATTR5 : Memory attribute encoding for MPU regions with an AttrIndex of 5
bits : 8 - 15 (8 bit)
access : read-write
ATTR6 : Memory attribute encoding for MPU regions with an AttrIndex of 6
bits : 16 - 23 (8 bit)
access : read-write
ATTR7 : Memory attribute encoding for MPU regions with an AttrIndex of 7
bits : 24 - 31 (8 bit)
access : read-write
Allows enabling of the Security Attribution Unit
address_offset : 0xEDD0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ENABLE : Enables the SAU
bits : 0 - 0 (1 bit)
access : read-write
ALLNS : When SAU_CTRL.ENABLE is 0 this bit controls if the memory is marked as Non-secure or Secure
bits : 1 - 1 (1 bit)
access : read-write
Indicates the number of regions implemented by the Security Attribution Unit
address_offset : 0xEDD4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SREGION : The number of implemented SAU regions
bits : 0 - 7 (8 bit)
access : read-only
Selects the region currently accessed by SAU_RBAR and SAU_RLAR
address_offset : 0xEDD8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
REGION : Indicates the SAU region accessed by SAU_RBAR and SAU_RLAR
bits : 0 - 7 (8 bit)
access : read-write
Provides indirect read and write access to the base address of the currently selected SAU region
address_offset : 0xEDDC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BADDR : Holds bits [31:5] of the base address for the selected SAU region
bits : 5 - 31 (27 bit)
access : read-write
Provides indirect read and write access to the limit address of the currently selected SAU region
address_offset : 0xEDE0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ENABLE : SAU region enable
bits : 0 - 0 (1 bit)
access : read-write
NSC : Controls whether Non-secure state is permitted to execute an SG instruction from this region
bits : 1 - 1 (1 bit)
access : read-write
LADDR : Holds bits [31:5] of the limit address for the selected SAU region
bits : 5 - 31 (27 bit)
access : read-write
Provides information about any security related faults
address_offset : 0xEDE4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INVEP : This bit is set if a function call from the Non-secure state or exception targets a non-SG instruction in the Secure state. This bit is also set if the target address is a SG instruction, but there is no matching SAU/IDAU region with the NSC flag set
bits : 0 - 0 (1 bit)
access : read-write
INVIS : This bit is set if the integrity signature in an exception stack frame is found to be invalid during the unstacking operation
bits : 1 - 1 (1 bit)
access : read-write
INVER : This can be caused by EXC_RETURN.DCRS being set to 0 when returning from an exception in the Non-secure state, or by EXC_RETURN.ES being set to 1 when returning from an exception in the Non-secure state
bits : 2 - 2 (1 bit)
access : read-write
AUVIOL : Sticky flag indicating that an attempt was made to access parts of the address space that are marked as Secure with NS-Req for the transaction set to Non-secure. This bit is not set if the violation occurred during lazy state preservation. See LSPERR
bits : 3 - 3 (1 bit)
access : read-write
INVTRAN : Sticky flag indicating that an exception was raised due to a branch that was not flagged as being domain crossing causing a transition from Secure to Non-secure memory
bits : 4 - 4 (1 bit)
access : read-write
LSPERR : Stick flag indicating that an SAU or IDAU violation occurred during the lazy preservation of floating-point state
bits : 5 - 5 (1 bit)
access : read-write
SFARVALID : This bit is set when the SFAR register contains a valid value. As with similar fields, such as BFSR.BFARVALID and MMFSR.MMARVALID, this bit can be cleared by other exceptions, such as BusFault
bits : 6 - 6 (1 bit)
access : read-write
LSERR : Sticky flag indicating that an error occurred during lazy state activation or deactivation
bits : 7 - 7 (1 bit)
access : read-write
Shows the address of the memory location that caused a Security violation
address_offset : 0xEDE8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADDRESS : The address of an access that caused a attribution unit violation. This field is only valid when SFSR.SFARVALID is set. This allows the actual flip flops associated with this register to be shared with other fault address registers. If an implementation chooses to share the storage in this way, care must be taken to not leak Secure address information to the Non-secure state. One way of achieving this is to share the SFAR register with the MMFAR_S register, which is not accessible to the Non-secure state
bits : 0 - 31 (32 bit)
access : read-write
Controls halting debug
address_offset : 0xEDF0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
C_DEBUGEN : Enable Halting debug
bits : 0 - 0 (1 bit)
access : read-write
C_HALT : PE enter Debug state halt request
bits : 1 - 1 (1 bit)
access : read-write
C_STEP : Enable single instruction step
bits : 2 - 2 (1 bit)
access : read-write
C_MASKINTS : When debug is enabled, the debugger can write to this bit to mask PendSV, SysTick and external configurable interrupts
bits : 3 - 3 (1 bit)
access : read-write
C_SNAPSTALL : Allow imprecise entry to Debug state
bits : 5 - 5 (1 bit)
access : read-write
S_REGRDY : Handshake flag to transfers through the DCRDR
bits : 16 - 16 (1 bit)
access : read-only
S_HALT : Indicates whether the PE is in Debug state
bits : 17 - 17 (1 bit)
access : read-only
S_SLEEP : Indicates whether the PE is sleeping
bits : 18 - 18 (1 bit)
access : read-only
S_LOCKUP : Indicates whether the PE is in Lockup state
bits : 19 - 19 (1 bit)
access : read-only
S_SDE : Indicates whether Secure invasive debug is allowed
bits : 20 - 20 (1 bit)
access : read-only
S_RETIRE_ST : Set to 1 every time the PE retires one of more instructions
bits : 24 - 24 (1 bit)
access : read-only
S_RESET_ST : Indicates whether the PE has been reset since the last read of the DHCSR
bits : 25 - 25 (1 bit)
access : read-only
S_RESTART_ST : Indicates the PE has processed a request to clear DHCSR.C_HALT to 0. That is, either a write to DHCSR that clears DHCSR.C_HALT from 1 to 0, or an External Restart Request
bits : 26 - 26 (1 bit)
access : read-only
With the DCRDR, provides debug access to the general-purpose registers, special-purpose registers, and the FP extension registers. A write to the DCRSR specifies the register to transfer, whether the transfer is a read or write, and starts the transfer
address_offset : 0xEDF4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
REGSEL : Specifies the general-purpose register, special-purpose register, or FP register to transfer
bits : 0 - 6 (7 bit)
access : read-write
REGWNR : Specifies the access type for the transfer
bits : 16 - 16 (1 bit)
access : read-write
With the DCRSR, provides debug access to the general-purpose registers, special-purpose registers, and the FP Extension registers. If the Main Extension is implemented, it can also be used for message passing between an external debugger and a debug agent running on the PE
address_offset : 0xEDF8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DBGTMP : Provides debug access for reading and writing the general-purpose registers, special-purpose registers, and Floating-point Extension registers
bits : 0 - 31 (32 bit)
access : read-write
Manages vector catch behavior and DebugMonitor handling when debugging
address_offset : 0xEDFC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VC_CORERESET : Enable Reset Vector Catch. This causes a warm reset to halt a running system
bits : 0 - 0 (1 bit)
access : read-write
VC_MMERR : Enable halting debug trap on a MemManage exception
bits : 4 - 4 (1 bit)
access : read-write
VC_NOCPERR : Enable halting debug trap on a UsageFault caused by an access to a coprocessor
bits : 5 - 5 (1 bit)
access : read-write
VC_CHKERR : Enable halting debug trap on a UsageFault exception caused by a checking error, for example an alignment check error
bits : 6 - 6 (1 bit)
access : read-write
VC_STATERR : Enable halting debug trap on a UsageFault exception caused by a state information error, for example an Undefined Instruction exception
bits : 7 - 7 (1 bit)
access : read-write
VC_BUSERR : BusFault exception halting debug vector catch enable
bits : 8 - 8 (1 bit)
access : read-write
VC_INTERR : Enable halting debug vector catch for faults during exception entry and return
bits : 9 - 9 (1 bit)
access : read-write
VC_HARDERR : HardFault exception halting debug vector catch enable
bits : 10 - 10 (1 bit)
access : read-write
VC_SFERR : SecureFault exception halting debug vector catch enable
bits : 11 - 11 (1 bit)
access : read-write
MON_EN : Enable the DebugMonitor exception
bits : 16 - 16 (1 bit)
access : read-write
MON_PEND : Sets or clears the pending state of the DebugMonitor exception
bits : 17 - 17 (1 bit)
access : read-write
MON_STEP : Enable DebugMonitor stepping
bits : 18 - 18 (1 bit)
access : read-write
MON_REQ : DebugMonitor semaphore bit
bits : 19 - 19 (1 bit)
access : read-write
SDME : Indicates whether the DebugMonitor targets the Secure or the Non-secure state and whether debug events are allowed in Secure state
bits : 20 - 20 (1 bit)
access : read-only
TRCENA : Global enable for all DWT and ITM features
bits : 24 - 24 (1 bit)
access : read-write
Provides control and status information for Secure debug
address_offset : 0xEE08 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SBRSELEN : Controls whether the SBRSEL field or the current Security state of the processor selects which version of the memory-mapped Banked registers are accessed to the debugger
bits : 0 - 0 (1 bit)
access : read-write
SBRSEL : If SBRSELEN is 1 this bit selects whether the Non-secure or the Secure version of the memory-mapped Banked registers are accessible to the debugger
bits : 1 - 1 (1 bit)
access : read-write
CDS : This field indicates the current Security state of the processor
bits : 16 - 16 (1 bit)
access : read-write
CDSKEY : Writes to the CDS bit are ignored unless CDSKEY is concurrently written to zero
bits : 17 - 17 (1 bit)
access : read-write
Integration Mode: Read ATB Ready
address_offset : 0xEF0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ATREADY : A read of this bit returns the value of ATREADY
bits : 0 - 0 (1 bit)
access : read-only
AFVALID : A read of this bit returns the value of AFVALID
bits : 1 - 1 (1 bit)
access : read-only
Provides a mechanism for software to generate an interrupt
address_offset : 0xEF00 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INTID : Indicates the interrupt to be pended. The value written is (ExceptionNumber - 16)
bits : 0 - 8 (9 bit)
access : read-write
Holds control data for the Floating-point extension
address_offset : 0xEF34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LSPACT : Indicates whether lazy preservation of the floating-point state is active
bits : 0 - 0 (1 bit)
access : read-write
USER : Indicates the privilege level of the software executing when the PE allocated the floating-point stack frame
bits : 1 - 1 (1 bit)
access : read-write
S : Security status of the floating-point context. This bit is only present in the Secure version of the register, and behaves as RAZ/WI when accessed from the Non-secure state. This bit is updated whenever lazy state preservation is activated, or when a floating-point instruction is executed
bits : 2 - 2 (1 bit)
access : read-write
THREAD : Indicates the PE mode when it allocated the floating-point stack frame
bits : 3 - 3 (1 bit)
access : read-write
HFRDY : Indicates whether the software executing when the PE allocated the floating-point stack frame was able to set the HardFault exception to pending
bits : 4 - 4 (1 bit)
access : read-write
MMRDY : Indicates whether the software executing when the PE allocated the floating-point stack frame was able to set the MemManage exception to pending
bits : 5 - 5 (1 bit)
access : read-write
BFRDY : Indicates whether the software executing when the PE allocated the floating-point stack frame was able to set the BusFault exception to pending
bits : 6 - 6 (1 bit)
access : read-write
SFRDY : Indicates whether the software executing when the PE allocated the floating-point stack frame was able to set the SecureFault exception to pending. This bit is only present in the Secure version of the register, and behaves as RAZ/WI when accessed from the Non-secure state
bits : 7 - 7 (1 bit)
access : read-write
MONRDY : Indicates whether the software executing when the PE allocated the floating-point stack frame was able to set the DebugMonitor exception to pending
bits : 8 - 8 (1 bit)
access : read-write
SPLIMVIOL : This bit is banked between the Security states and indicates whether the floating-point context violates the stack pointer limit that was active when lazy state preservation was activated. SPLIMVIOL modifies the lazy floating-point state preservation behavior
bits : 9 - 9 (1 bit)
access : read-write
UFRDY : Indicates whether the software executing when the PE allocated the floating-point stack frame was able to set the UsageFault exception to pending
bits : 10 - 10 (1 bit)
access : read-write
TS : Treat floating-point registers as Secure enable
bits : 26 - 26 (1 bit)
access : read-write
CLRONRETS : This bit controls whether the CLRONRET bit is writeable from the Non-secure state
bits : 27 - 27 (1 bit)
access : read-write
CLRONRET : Clear floating-point caller saved registers on exception return
bits : 28 - 28 (1 bit)
access : read-write
LSPENS : This bit controls whether the LSPEN bit is writeable from the Non-secure state
bits : 29 - 29 (1 bit)
access : read-write
LSPEN : Enables lazy context save of floating-point state
bits : 30 - 30 (1 bit)
access : read-write
ASPEN : When this bit is set to 1, execution of a floating-point instruction sets the CONTROL.FPCA bit to 1
bits : 31 - 31 (1 bit)
access : read-write
Holds the location of the unpopulated floating-point register space allocated on an exception stack frame
address_offset : 0xEF38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADDRESS : The location of the unpopulated floating-point register space allocated on an exception stack frame
bits : 3 - 31 (29 bit)
access : read-write
Holds the default values for the floating-point status control data that the PE assigns to the FPSCR when it creates a new floating-point context
address_offset : 0xEF3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RMODE : Default value for FPSCR.RMode
bits : 22 - 23 (2 bit)
access : read-write
FZ : Default value for FPSCR.FZ
bits : 24 - 24 (1 bit)
access : read-write
DN : Default value for FPSCR.DN
bits : 25 - 25 (1 bit)
access : read-write
AHP : Default value for FPSCR.AHP
bits : 26 - 26 (1 bit)
access : read-write
Describes the features provided by the Floating-point Extension
address_offset : 0xEF40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SIMDREG : Indicates size of FP register file
bits : 0 - 3 (4 bit)
access : read-only
FPSP : Indicates support for FP single-precision operations
bits : 4 - 7 (4 bit)
access : read-only
FPDP : Indicates support for FP double-precision operations
bits : 8 - 11 (4 bit)
access : read-only
FPDIVIDE : Indicates the support for FP divide operations
bits : 16 - 19 (4 bit)
access : read-only
FPSQRT : Indicates the support for FP square root operations
bits : 20 - 23 (4 bit)
access : read-only
FPROUND : Indicates the rounding modes supported by the FP Extension
bits : 28 - 31 (4 bit)
access : read-only
Describes the features provided by the Floating-point Extension
address_offset : 0xEF44 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FPFTZ : Indicates whether subnormals are always flushed-to-zero
bits : 0 - 3 (4 bit)
access : read-only
FPDNAN : Indicates whether the FP hardware implementation supports NaN propagation
bits : 4 - 7 (4 bit)
access : read-only
FPHP : Indicates whether the FP Extension implements half-precision FP conversion instructions
bits : 24 - 27 (4 bit)
access : read-only
FMAC : Indicates whether the FP Extension implements the fused multiply accumulate instructions
bits : 28 - 31 (4 bit)
access : read-only
Describes the features provided by the Floating-point Extension
address_offset : 0xEF48 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FPMISC : Indicates support for miscellaneous FP features
bits : 4 - 7 (4 bit)
access : read-only
Integration Mode: Write ATB Valid
address_offset : 0xEF8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ATREADY : A write to this bit gives the value of ATVALID
bits : 0 - 0 (1 bit)
access : read-write
AFREADY : A write to this bit gives the value of AFREADY
bits : 1 - 1 (1 bit)
access : read-write
Provides CoreSight discovery information for the SCS
address_offset : 0xEFBC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ARCHPART : Defines the architecture of the component
bits : 0 - 11 (12 bit)
access : read-only
ARCHVER : Defines the architecture version of the component
bits : 12 - 15 (4 bit)
access : read-only
REVISION : Defines the architecture revision of the component
bits : 16 - 19 (4 bit)
access : read-only
PRESENT : Defines that the DEVARCH register is present
bits : 20 - 20 (1 bit)
access : read-only
ARCHITECT : Defines the architect of the component. Bits [31:28] are the JEP106 continuation code (JEP106 bank ID, minus 1) and bits [27:21] are the JEP106 ID code.
bits : 21 - 31 (11 bit)
access : read-only
Provides CoreSight discovery information for the SCS
address_offset : 0xEFCC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MAJOR : CoreSight major type
bits : 0 - 3 (4 bit)
access : read-only
SUB : Component sub-type
bits : 4 - 7 (4 bit)
access : read-only
Provides CoreSight discovery information for the SCS
address_offset : 0xEFD0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DES_2 : See CoreSight Architecture Specification
bits : 0 - 3 (4 bit)
access : read-only
SIZE : See CoreSight Architecture Specification
bits : 4 - 7 (4 bit)
access : read-only
Provides CoreSight discovery information for the SCS
address_offset : 0xEFD4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DPIDR5 :
bits : 0 - 31 (32 bit)
access : read-write
Provides CoreSight discovery information for the SCS
address_offset : 0xEFD8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DPIDR6 :
bits : 0 - 31 (32 bit)
access : read-write
Provides CoreSight discovery information for the SCS
address_offset : 0xEFDC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DPIDR7 :
bits : 0 - 31 (32 bit)
access : read-write
Provides CoreSight discovery information for the SCS
address_offset : 0xEFE0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PART_0 : See CoreSight Architecture Specification
bits : 0 - 7 (8 bit)
access : read-only
Provides CoreSight discovery information for the SCS
address_offset : 0xEFE4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PART_1 : See CoreSight Architecture Specification
bits : 0 - 3 (4 bit)
access : read-only
DES_0 : See CoreSight Architecture Specification
bits : 4 - 7 (4 bit)
access : read-only
Provides CoreSight discovery information for the SCS
address_offset : 0xEFE8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DES_1 : See CoreSight Architecture Specification
bits : 0 - 2 (3 bit)
access : read-only
JEDEC : See CoreSight Architecture Specification
bits : 3 - 3 (1 bit)
access : read-only
REVISION : See CoreSight Architecture Specification
bits : 4 - 7 (4 bit)
access : read-only
Provides CoreSight discovery information for the SCS
address_offset : 0xEFEC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CMOD : See CoreSight Architecture Specification
bits : 0 - 3 (4 bit)
access : read-only
REVAND : See CoreSight Architecture Specification
bits : 4 - 7 (4 bit)
access : read-only
Provides CoreSight discovery information for the SCS
address_offset : 0xEFF0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRMBL_0 : See CoreSight Architecture Specification
bits : 0 - 7 (8 bit)
access : read-only
Provides CoreSight discovery information for the SCS
address_offset : 0xEFF4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRMBL_1 : See CoreSight Architecture Specification
bits : 0 - 3 (4 bit)
access : read-only
CLASS : See CoreSight Architecture Specification
bits : 4 - 7 (4 bit)
access : read-only
Provides CoreSight discovery information for the SCS
address_offset : 0xEFF8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRMBL_2 : See CoreSight Architecture Specification
bits : 0 - 7 (8 bit)
access : read-only
Provides CoreSight discovery information for the SCS
address_offset : 0xEFFC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRMBL_3 : See CoreSight Architecture Specification
bits : 0 - 7 (8 bit)
access : read-only
Integration Mode Control Register
address_offset : 0xF00 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IME : Integration mode enable bit - The possible values are: 0 - The trace unit is not in integration mode. 1 - The trace unit is in integration mode. This mode enables: A debug agent to perform topology detection. SoC test software to perform integration testing.
bits : 0 - 0 (1 bit)
access : read-write
Provides CoreSight discovery information for the ITM
address_offset : 0xFBC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ARCHPART : Defines the architecture of the component
bits : 0 - 11 (12 bit)
access : read-only
ARCHVER : Defines the architecture version of the component
bits : 12 - 15 (4 bit)
access : read-only
REVISION : Defines the architecture revision of the component
bits : 16 - 19 (4 bit)
access : read-only
PRESENT : Defines that the DEVARCH register is present
bits : 20 - 20 (1 bit)
access : read-only
ARCHITECT : Defines the architect of the component. Bits [31:28] are the JEP106 continuation code (JEP106 bank ID, minus 1) and bits [27:21] are the JEP106 ID code.
bits : 21 - 31 (11 bit)
access : read-only
Provides CoreSight discovery information for the ITM
address_offset : 0xFCC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MAJOR : Component major type
bits : 0 - 3 (4 bit)
access : read-only
SUB : Component sub-type
bits : 4 - 7 (4 bit)
access : read-only
Provides CoreSight discovery information for the ITM
address_offset : 0xFD0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DES_2 : See CoreSight Architecture Specification
bits : 0 - 3 (4 bit)
access : read-only
SIZE : See CoreSight Architecture Specification
bits : 4 - 7 (4 bit)
access : read-only
Provides CoreSight discovery information for the ITM
address_offset : 0xFD4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ITM_PIDR5 :
bits : 0 - 31 (32 bit)
access : read-write
Provides CoreSight discovery information for the ITM
address_offset : 0xFD8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ITM_PIDR6 :
bits : 0 - 31 (32 bit)
access : read-write
Provides CoreSight discovery information for the ITM
address_offset : 0xFDC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ITM_PIDR7 :
bits : 0 - 31 (32 bit)
access : read-write
Provides CoreSight discovery information for the ITM
address_offset : 0xFE0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PART_0 : See CoreSight Architecture Specification
bits : 0 - 7 (8 bit)
access : read-only
Provides CoreSight discovery information for the ITM
address_offset : 0xFE4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PART_1 : See CoreSight Architecture Specification
bits : 0 - 3 (4 bit)
access : read-only
DES_0 : See CoreSight Architecture Specification
bits : 4 - 7 (4 bit)
access : read-only
Provides CoreSight discovery information for the ITM
address_offset : 0xFE8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DES_1 : See CoreSight Architecture Specification
bits : 0 - 2 (3 bit)
access : read-only
JEDEC : See CoreSight Architecture Specification
bits : 3 - 3 (1 bit)
access : read-only
REVISION : See CoreSight Architecture Specification
bits : 4 - 7 (4 bit)
access : read-only
Provides CoreSight discovery information for the ITM
address_offset : 0xFEC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CMOD : See CoreSight Architecture Specification
bits : 0 - 3 (4 bit)
access : read-only
REVAND : See CoreSight Architecture Specification
bits : 4 - 7 (4 bit)
access : read-only
Provides CoreSight discovery information for the ITM
address_offset : 0xFF0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRMBL_0 : See CoreSight Architecture Specification
bits : 0 - 7 (8 bit)
access : read-only
Provides CoreSight discovery information for the ITM
address_offset : 0xFF4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRMBL_1 : See CoreSight Architecture Specification
bits : 0 - 3 (4 bit)
access : read-only
CLASS : See CoreSight Architecture Specification
bits : 4 - 7 (4 bit)
access : read-only
Provides CoreSight discovery information for the ITM
address_offset : 0xFF8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRMBL_2 : See CoreSight Architecture Specification
bits : 0 - 7 (8 bit)
access : read-only
Provides CoreSight discovery information for the ITM
address_offset : 0xFFC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRMBL_3 : See CoreSight Architecture Specification
bits : 0 - 7 (8 bit)
access : read-only
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