Embeetle, an IDE designed from scratch for embedded software developers.address_offset : 0x0 Bytes (0x0)
size : 0x54 byte (0x0)
mem_usage : registers
protection :
Control and status for direct serial mode
Direct serial mode allows the processor to send and receive raw serial frames, for programming, configuration and control of the external memory devices. Only SPI mode 0 (CPOL=0 CPHA=0) is supported.
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : Enable direct mode.
In direct mode, software controls the chip select lines, and can perform direct SPI transfers by pushing data to the DIRECT_TX FIFO, and popping the same amount of data from the DIRECT_RX FIFO.
Memory-mapped accesses will generate bus errors when direct serial mode is enabled.
bits : 0 - 0 (1 bit)
access : read-write
BUSY : Direct mode busy flag. If 1, data is currently being shifted in/out (or would be if the interface were not stalled on the RX FIFO), and the chip select must not yet be deasserted.
The busy flag will also be set to 1 if a memory-mapped transfer is still in progress when direct mode is enabled. Direct mode blocks new memory-mapped transfers, but can't halt a transfer that is already in progress. If there is a chance that memory-mapped transfers may be in progress, the busy flag should be polled for 0 before asserting the chip select.
(In practice you will usually discover this timing condition through other means, because any subsequent memory-mapped transfers when direct mode is enabled will return bus errors, which are difficult to ignore.)
bits : 1 - 1 (1 bit)
access : read-only
ASSERT_CS0N : When 1, assert (i.e. drive low) the CS0n chip select line.
Note that this applies even when DIRECT_CSR_EN is 0.
bits : 2 - 2 (1 bit)
access : read-write
ASSERT_CS1N : When 1, assert (i.e. drive low) the CS1n chip select line.
Note that this applies even when DIRECT_CSR_EN is 0.
bits : 3 - 3 (1 bit)
access : read-write
AUTO_CS0N : When 1, automatically assert the CS0n chip select line whenever the BUSY flag is set.
bits : 6 - 6 (1 bit)
access : read-write
AUTO_CS1N : When 1, automatically assert the CS1n chip select line whenever the BUSY flag is set.
bits : 7 - 7 (1 bit)
access : read-write
TXFULL : When 1, the DIRECT_TX FIFO is currently full. If the processor tries to write more data, that data will be ignored.
bits : 10 - 10 (1 bit)
access : read-only
TXEMPTY : When 1, the DIRECT_TX FIFO is currently empty. Unless the processor pushes more data, transmission will stop and BUSY will go low once the current 8-bit serial frame completes.
bits : 11 - 11 (1 bit)
access : read-only
TXLEVEL : Current level of DIRECT_TX FIFO
bits : 12 - 14 (3 bit)
access : read-only
RXEMPTY : When 1, the DIRECT_RX FIFO is currently empty. If the processor attempts to read more data, the FIFO state is not affected, but the value returned to the processor is undefined.
bits : 16 - 16 (1 bit)
access : read-only
RXFULL : When 1, the DIRECT_RX FIFO is currently full. The serial interface will be stalled until data is popped the interface will not begin a new serial frame when the DIRECT_TX FIFO is empty or the DIRECT_RX FIFO is full.
bits : 17 - 17 (1 bit)
access : read-only
RXLEVEL : Current level of DIRECT_RX FIFO
bits : 18 - 20 (3 bit)
access : read-only
CLKDIV : Clock divisor for direct serial mode. Divisors of 1..255 are encoded directly, and the maximum divisor of 256 is encoded by a value of CLKDIV=0.
The clock divisor can be changed on-the-fly by software, without halting or otherwise coordinating with the serial interface. The serial interface will sample the latest clock divisor each time it begins the transmission of a new byte.
bits : 22 - 29 (8 bit)
access : read-write
RXDELAY : Delay the read data sample timing, in units of one half of a system clock cycle. (Not necessarily half of an SCK cycle.)
bits : 30 - 31 (2 bit)
access : read-write
Read transfer format configuration for memory address window 0.
Configure the bus width of each transfer phase individually, and configure the length or presence of the command prefix, command suffix and dummy/turnaround transfer phases. Only 24-bit addresses are supported.
The reset value of the M0_RFMT register is configured to support a basic 03h serial read transfer with no additional configuration.
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PREFIX_WIDTH : The transfer width used for the command prefix, if any
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
0 : S
Single width
1 : D
Dual width
2 : Q
Quad width
End of enumeration elements list.
ADDR_WIDTH : The transfer width used for the address. The address phase always transfers 24 bits in total.
bits : 2 - 3 (2 bit)
access : read-write
Enumeration:
0 : S
Single width
1 : D
Dual width
2 : Q
Quad width
End of enumeration elements list.
SUFFIX_WIDTH : The width used for the post-address command suffix, if any
bits : 4 - 5 (2 bit)
access : read-write
Enumeration:
0 : S
Single width
1 : D
Dual width
2 : Q
Quad width
End of enumeration elements list.
DUMMY_WIDTH : The width used for the dummy phase, if any.
If width is single, SD0/MOSI is held asserted low during the dummy phase, and SD1...SD3 are tristated. If width is dual/quad, all IOs are tristated during the dummy phase.
bits : 6 - 7 (2 bit)
access : read-write
Enumeration:
0 : S
Single width
1 : D
Dual width
2 : Q
Quad width
End of enumeration elements list.
DATA_WIDTH : The width used for the data transfer
bits : 8 - 9 (2 bit)
access : read-write
Enumeration:
0 : S
Single width
1 : D
Dual width
2 : Q
Quad width
End of enumeration elements list.
PREFIX_LEN : Length of command prefix, in units of 8 bits. (i.e. 2 cycles for quad width, 4 for dual, 8 for single)
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
0 : NONE
No prefix
1 : 8
8-bit prefix
End of enumeration elements list.
SUFFIX_LEN : Length of post-address command suffix, in units of 4 bits. (i.e. 1 cycle for quad width, 2 for dual, 4 for single)
Only values of 0 and 8 bits are supported.
bits : 14 - 15 (2 bit)
access : read-write
Enumeration:
0 : NONE
No suffix
2 : 8
8-bit suffix
End of enumeration elements list.
DUMMY_LEN : Length of dummy phase between command suffix and data phase, in units of 4 bits. (i.e. 1 cycle for quad width, 2 for dual, 4 for single)
bits : 16 - 18 (3 bit)
access : read-write
Enumeration:
0 : NONE
No dummy phase
1 : 4
4 dummy bits
2 : 8
8 dummy bits
3 : 12
12 dummy bits
4 : 16
16 dummy bits
5 : 20
20 dummy bits
6 : 24
24 dummy bits
7 : 28
28 dummy bits
End of enumeration elements list.
DTR : Enable double transfer rate (DTR) for read commands: address, suffix and read data phases are active on both edges of SCK. SDO data is launched centre-aligned on each SCK edge, and SDI data is captured on the SCK edge that follows its launch.
DTR is implemented by halving the clock rate SCK has a period of 2 x CLK_DIV throughout the transfer. The prefix and dummy phases are still single transfer rate.
If the suffix is quad-width, it must be 0 or 8 bits in length, to ensure an even number of SCK edges.
bits : 28 - 28 (1 bit)
access : read-write
Command constants used for reads from memory address window 0.
The reset value of the M0_RCMD register is configured to support a basic 03h serial read transfer with no additional configuration.
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PREFIX : The command prefix bits to prepend on each new transfer, if Mx_RFMT_PREFIX_LEN is nonzero.
bits : 0 - 7 (8 bit)
access : read-write
SUFFIX : The command suffix bits following the address, if Mx_RFMT_SUFFIX_LEN is nonzero.
bits : 8 - 15 (8 bit)
access : read-write
Write transfer format configuration for memory address window 0.
Configure the bus width of each transfer phase individually, and configure the length or presence of the command prefix, command suffix and dummy/turnaround transfer phases. Only 24-bit addresses are supported.
The reset value of the M0_WFMT register is configured to support a basic 02h serial write transfer. However, writes to this window must first be enabled via the XIP_CTRL_WRITABLE_M0 bit, as XIP memory is read-only by default.
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PREFIX_WIDTH : The transfer width used for the command prefix, if any
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
0 : S
Single width
1 : D
Dual width
2 : Q
Quad width
End of enumeration elements list.
ADDR_WIDTH : The transfer width used for the address. The address phase always transfers 24 bits in total.
bits : 2 - 3 (2 bit)
access : read-write
Enumeration:
0 : S
Single width
1 : D
Dual width
2 : Q
Quad width
End of enumeration elements list.
SUFFIX_WIDTH : The width used for the post-address command suffix, if any
bits : 4 - 5 (2 bit)
access : read-write
Enumeration:
0 : S
Single width
1 : D
Dual width
2 : Q
Quad width
End of enumeration elements list.
DUMMY_WIDTH : The width used for the dummy phase, if any.
If width is single, SD0/MOSI is held asserted low during the dummy phase, and SD1...SD3 are tristated. If width is dual/quad, all IOs are tristated during the dummy phase.
bits : 6 - 7 (2 bit)
access : read-write
Enumeration:
0 : S
Single width
1 : D
Dual width
2 : Q
Quad width
End of enumeration elements list.
DATA_WIDTH : The width used for the data transfer
bits : 8 - 9 (2 bit)
access : read-write
Enumeration:
0 : S
Single width
1 : D
Dual width
2 : Q
Quad width
End of enumeration elements list.
PREFIX_LEN : Length of command prefix, in units of 8 bits. (i.e. 2 cycles for quad width, 4 for dual, 8 for single)
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
0 : NONE
No prefix
1 : 8
8-bit prefix
End of enumeration elements list.
SUFFIX_LEN : Length of post-address command suffix, in units of 4 bits. (i.e. 1 cycle for quad width, 2 for dual, 4 for single)
Only values of 0 and 8 bits are supported.
bits : 14 - 15 (2 bit)
access : read-write
Enumeration:
0 : NONE
No suffix
2 : 8
8-bit suffix
End of enumeration elements list.
DUMMY_LEN : Length of dummy phase between command suffix and data phase, in units of 4 bits. (i.e. 1 cycle for quad width, 2 for dual, 4 for single)
bits : 16 - 18 (3 bit)
access : read-write
Enumeration:
0 : NONE
No dummy phase
1 : 4
4 dummy bits
2 : 8
8 dummy bits
3 : 12
12 dummy bits
4 : 16
16 dummy bits
5 : 20
20 dummy bits
6 : 24
24 dummy bits
7 : 28
28 dummy bits
End of enumeration elements list.
DTR : Enable double transfer rate (DTR) for write commands: address, suffix and write data phases are active on both edges of SCK. SDO data is launched centre-aligned on each SCK edge, and SDI data is captured on the SCK edge that follows its launch.
DTR is implemented by halving the clock rate SCK has a period of 2 x CLK_DIV throughout the transfer. The prefix and dummy phases are still single transfer rate.
If the suffix is quad-width, it must be 0 or 8 bits in length, to ensure an even number of SCK edges.
bits : 28 - 28 (1 bit)
access : read-write
Command constants used for writes to memory address window 0.
The reset value of the M0_WCMD register is configured to support a basic 02h serial write transfer with no additional configuration.
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PREFIX : The command prefix bits to prepend on each new transfer, if Mx_WFMT_PREFIX_LEN is nonzero.
bits : 0 - 7 (8 bit)
access : read-write
SUFFIX : The command suffix bits following the address, if Mx_WFMT_SUFFIX_LEN is nonzero.
bits : 8 - 15 (8 bit)
access : read-write
Timing configuration register for memory address window 1.
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CLKDIV : Clock divisor. Odd and even divisors are supported. Defines the SCK clock period in units of 1 system clock cycle. Divisors 1..255 are encoded directly, and a divisor of 256 is encoded with a value of CLKDIV=0.
The clock divisor can be changed on-the-fly, even when the QMI is currently accessing memory in this address window. All other parameters must only be changed when the QMI is idle.
If software is increasing CLKDIV in anticipation of an increase in the system clock frequency, a dummy access to either memory window (and appropriate processor barriers/fences) must be inserted after the Mx_TIMING write to ensure the SCK divisor change is in effect _before_ the system clock is changed.
bits : 0 - 7 (8 bit)
access : read-write
RXDELAY : Delay the read data sample timing, in units of one half of a system clock cycle. (Not necessarily half of an SCK cycle.) An RXDELAY of 0 means the sample is captured at the SDI input registers simultaneously with the rising edge of SCK launched from the SCK output register.
At higher SCK frequencies, RXDELAY may need to be increased to account for the round trip delay of the pads, and the clock-to-Q delay of the QSPI memory device.
bits : 8 - 10 (3 bit)
access : read-write
MIN_DESELECT : After this window's chip select is deasserted, it remains deasserted for half an SCK cycle (rounded up to an integer number of system clock cycles), plus MIN_DESELECT additional system clock cycles, before the QMI reasserts either chip select pin.
Nonzero values may be required for PSRAM devices which enforce a longer minimum CS deselect time, so that they can perform internal DRAM refresh cycles whilst deselected.
bits : 12 - 16 (5 bit)
access : read-write
MAX_SELECT : Enforce a maximum assertion duration for this window's chip select, in units of 64 system clock cycles. If 0, the QMI is permitted to keep the chip select asserted indefinitely when servicing sequential memory accesses (see COOLDOWN).
This feature is required to meet timing constraints of PSRAM devices, which specify a maximum chip select assertion so they can perform DRAM refresh cycles. See also MIN_DESELECT, which can enforce a minimum deselect time.
If a memory access is in progress at the time MAX_SELECT is reached, the QMI will wait for the access to complete before deasserting the chip select. This additional time must be accounted for to calculate a safe MAX_SELECT value. In the worst case, this may be a fully-formed serial transfer, including command prefix and address, with a data payload as large as one cache line.
bits : 17 - 22 (6 bit)
access : read-write
SELECT_HOLD : Add up to three additional system clock cycles of active hold between the last falling edge of SCK and the deassertion of this window's chip select.
The default hold time is one system clock cycle. Note that flash datasheets usually give chip select active hold time from the last *rising* edge of SCK, and so even zero hold from the last falling edge would be safe.
Note that this is a minimum hold time guaranteed by the QMI: the actual chip select active hold may be slightly longer for read transfers with low clock divisors and/or high sample delays. Specifically, if the point two cycles after the last RX data sample is later than the last SCK falling edge, then the hold time is measured from *this* point.
Note also that, in case the final SCK pulse is masked to save energy (true for non-DTR reads when COOLDOWN is disabled or PAGE_BREAK is reached), all of QMI's timing logic behaves as though the clock pulse were still present. The SELECT_HOLD time is applied from the point where the last SCK falling edge would be if the clock pulse were not masked.
bits : 23 - 24 (2 bit)
access : read-write
SELECT_SETUP : Add up to one additional system clock cycle of setup between chip select assertion and the first rising edge of SCK.
The default setup time is one half SCK period, which is usually sufficient except for very high SCK frequencies with some flash devices.
bits : 25 - 25 (1 bit)
access : read-write
PAGEBREAK : When page break is enabled, chip select will automatically deassert when crossing certain power-of-2-aligned address boundaries. The next access will always begin a new read/write SPI burst, even if the address of the next access follows in sequence with the last access before the page boundary.
Some flash and PSRAM devices forbid crossing page boundaries with a single read/write transfer, or restrict the operating frequency for transfers that do cross page a boundary. This option allows the QMI to safely support those devices.
This field has no effect when COOLDOWN is disabled.
bits : 28 - 29 (2 bit)
access : read-write
Enumeration:
0 : NONE
No page boundary is enforced
1 : 256
Break bursts crossing a 256-byte page boundary
2 : 1024
Break bursts crossing a 1024-byte quad-page boundary
3 : 4096
Break bursts crossing a 4096-byte sector boundary
End of enumeration elements list.
COOLDOWN : Chip select cooldown period. When a memory transfer finishes, the chip select remains asserted for 64 x COOLDOWN system clock cycles, plus half an SCK clock period (rounded up for odd SCK divisors). After this cooldown expires, the chip select is always deasserted to save power.
If the next memory access arrives within the cooldown period, the QMI may be able to append more SCK cycles to the currently ongoing SPI transfer, rather than starting a new transfer. This reduces access latency and increases bus throughput.
Specifically, the next access must be in the same direction (read/write), access the same memory window (chip select 0/1), and follow sequentially the address of the last transfer. If any of these are false, the new access will first deassert the chip select, then begin a new transfer.
If COOLDOWN is 0, the address alignment configured by PAGEBREAK has been reached, or the total chip select assertion limit MAX_SELECT has been reached, the cooldown period is skipped, and the chip select will always be deasserted one half SCK period after the transfer finishes.
bits : 30 - 31 (2 bit)
access : read-write
Read transfer format configuration for memory address window 1.
Configure the bus width of each transfer phase individually, and configure the length or presence of the command prefix, command suffix and dummy/turnaround transfer phases. Only 24-bit addresses are supported.
The reset value of the M1_RFMT register is configured to support a basic 03h serial read transfer with no additional configuration.
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PREFIX_WIDTH : The transfer width used for the command prefix, if any
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
0 : S
Single width
1 : D
Dual width
2 : Q
Quad width
End of enumeration elements list.
ADDR_WIDTH : The transfer width used for the address. The address phase always transfers 24 bits in total.
bits : 2 - 3 (2 bit)
access : read-write
Enumeration:
0 : S
Single width
1 : D
Dual width
2 : Q
Quad width
End of enumeration elements list.
SUFFIX_WIDTH : The width used for the post-address command suffix, if any
bits : 4 - 5 (2 bit)
access : read-write
Enumeration:
0 : S
Single width
1 : D
Dual width
2 : Q
Quad width
End of enumeration elements list.
DUMMY_WIDTH : The width used for the dummy phase, if any.
If width is single, SD0/MOSI is held asserted low during the dummy phase, and SD1...SD3 are tristated. If width is dual/quad, all IOs are tristated during the dummy phase.
bits : 6 - 7 (2 bit)
access : read-write
Enumeration:
0 : S
Single width
1 : D
Dual width
2 : Q
Quad width
End of enumeration elements list.
DATA_WIDTH : The width used for the data transfer
bits : 8 - 9 (2 bit)
access : read-write
Enumeration:
0 : S
Single width
1 : D
Dual width
2 : Q
Quad width
End of enumeration elements list.
PREFIX_LEN : Length of command prefix, in units of 8 bits. (i.e. 2 cycles for quad width, 4 for dual, 8 for single)
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
0 : NONE
No prefix
1 : 8
8-bit prefix
End of enumeration elements list.
SUFFIX_LEN : Length of post-address command suffix, in units of 4 bits. (i.e. 1 cycle for quad width, 2 for dual, 4 for single)
Only values of 0 and 8 bits are supported.
bits : 14 - 15 (2 bit)
access : read-write
Enumeration:
0 : NONE
No suffix
2 : 8
8-bit suffix
End of enumeration elements list.
DUMMY_LEN : Length of dummy phase between command suffix and data phase, in units of 4 bits. (i.e. 1 cycle for quad width, 2 for dual, 4 for single)
bits : 16 - 18 (3 bit)
access : read-write
Enumeration:
0 : NONE
No dummy phase
1 : 4
4 dummy bits
2 : 8
8 dummy bits
3 : 12
12 dummy bits
4 : 16
16 dummy bits
5 : 20
20 dummy bits
6 : 24
24 dummy bits
7 : 28
28 dummy bits
End of enumeration elements list.
DTR : Enable double transfer rate (DTR) for read commands: address, suffix and read data phases are active on both edges of SCK. SDO data is launched centre-aligned on each SCK edge, and SDI data is captured on the SCK edge that follows its launch.
DTR is implemented by halving the clock rate SCK has a period of 2 x CLK_DIV throughout the transfer. The prefix and dummy phases are still single transfer rate.
If the suffix is quad-width, it must be 0 or 8 bits in length, to ensure an even number of SCK edges.
bits : 28 - 28 (1 bit)
access : read-write
Command constants used for reads from memory address window 1.
The reset value of the M1_RCMD register is configured to support a basic 03h serial read transfer with no additional configuration.
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PREFIX : The command prefix bits to prepend on each new transfer, if Mx_RFMT_PREFIX_LEN is nonzero.
bits : 0 - 7 (8 bit)
access : read-write
SUFFIX : The command suffix bits following the address, if Mx_RFMT_SUFFIX_LEN is nonzero.
bits : 8 - 15 (8 bit)
access : read-write
Write transfer format configuration for memory address window 1.
Configure the bus width of each transfer phase individually, and configure the length or presence of the command prefix, command suffix and dummy/turnaround transfer phases. Only 24-bit addresses are supported.
The reset value of the M1_WFMT register is configured to support a basic 02h serial write transfer. However, writes to this window must first be enabled via the XIP_CTRL_WRITABLE_M1 bit, as XIP memory is read-only by default.
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PREFIX_WIDTH : The transfer width used for the command prefix, if any
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
0 : S
Single width
1 : D
Dual width
2 : Q
Quad width
End of enumeration elements list.
ADDR_WIDTH : The transfer width used for the address. The address phase always transfers 24 bits in total.
bits : 2 - 3 (2 bit)
access : read-write
Enumeration:
0 : S
Single width
1 : D
Dual width
2 : Q
Quad width
End of enumeration elements list.
SUFFIX_WIDTH : The width used for the post-address command suffix, if any
bits : 4 - 5 (2 bit)
access : read-write
Enumeration:
0 : S
Single width
1 : D
Dual width
2 : Q
Quad width
End of enumeration elements list.
DUMMY_WIDTH : The width used for the dummy phase, if any.
If width is single, SD0/MOSI is held asserted low during the dummy phase, and SD1...SD3 are tristated. If width is dual/quad, all IOs are tristated during the dummy phase.
bits : 6 - 7 (2 bit)
access : read-write
Enumeration:
0 : S
Single width
1 : D
Dual width
2 : Q
Quad width
End of enumeration elements list.
DATA_WIDTH : The width used for the data transfer
bits : 8 - 9 (2 bit)
access : read-write
Enumeration:
0 : S
Single width
1 : D
Dual width
2 : Q
Quad width
End of enumeration elements list.
PREFIX_LEN : Length of command prefix, in units of 8 bits. (i.e. 2 cycles for quad width, 4 for dual, 8 for single)
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
0 : NONE
No prefix
1 : 8
8-bit prefix
End of enumeration elements list.
SUFFIX_LEN : Length of post-address command suffix, in units of 4 bits. (i.e. 1 cycle for quad width, 2 for dual, 4 for single)
Only values of 0 and 8 bits are supported.
bits : 14 - 15 (2 bit)
access : read-write
Enumeration:
0 : NONE
No suffix
2 : 8
8-bit suffix
End of enumeration elements list.
DUMMY_LEN : Length of dummy phase between command suffix and data phase, in units of 4 bits. (i.e. 1 cycle for quad width, 2 for dual, 4 for single)
bits : 16 - 18 (3 bit)
access : read-write
Enumeration:
0 : NONE
No dummy phase
1 : 4
4 dummy bits
2 : 8
8 dummy bits
3 : 12
12 dummy bits
4 : 16
16 dummy bits
5 : 20
20 dummy bits
6 : 24
24 dummy bits
7 : 28
28 dummy bits
End of enumeration elements list.
DTR : Enable double transfer rate (DTR) for write commands: address, suffix and write data phases are active on both edges of SCK. SDO data is launched centre-aligned on each SCK edge, and SDI data is captured on the SCK edge that follows its launch.
DTR is implemented by halving the clock rate SCK has a period of 2 x CLK_DIV throughout the transfer. The prefix and dummy phases are still single transfer rate.
If the suffix is quad-width, it must be 0 or 8 bits in length, to ensure an even number of SCK edges.
bits : 28 - 28 (1 bit)
access : read-write
Command constants used for writes to memory address window 1.
The reset value of the M1_WCMD register is configured to support a basic 02h serial write transfer with no additional configuration.
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PREFIX : The command prefix bits to prepend on each new transfer, if Mx_WFMT_PREFIX_LEN is nonzero.
bits : 0 - 7 (8 bit)
access : read-write
SUFFIX : The command suffix bits following the address, if Mx_WFMT_SUFFIX_LEN is nonzero.
bits : 8 - 15 (8 bit)
access : read-write
Configure address translation for XIP virtual addresses 0x000000 through 0x3fffff (a 4 MiB window starting at +0 MiB).
Address translation allows a program image to be executed in place at multiple physical flash addresses (for example, a double-buffered flash image for over-the-air updates), without the overhead of position-independent code.
At reset, the address translation registers are initialised to an identity mapping, so that they can be ignored if address translation is not required.
Note that the XIP cache is fully virtually addressed, so a cache flush is required after changing the address translation.
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BASE : Physical address base for this virtual address range, in units of 4 kiB (one flash sector).
Taking a 24-bit virtual address, firstly bits 23:22 (the two MSBs) are masked to zero, and then BASE is added to bits 23:12 (the upper 12 bits) to form the physical address. Translation wraps on a 16 MiB boundary.
bits : 0 - 11 (12 bit)
access : read-write
SIZE : Translation aperture size for this virtual address range, in units of 4 kiB (one flash sector).
Bits 21:12 of the virtual address are compared to SIZE. Offsets greater than SIZE return a bus error, and do not cause a QSPI access.
bits : 16 - 26 (11 bit)
access : read-write
Configure address translation for XIP virtual addresses 0x400000 through 0x7fffff (a 4 MiB window starting at +4 MiB).
Address translation allows a program image to be executed in place at multiple physical flash addresses (for example, a double-buffered flash image for over-the-air updates), without the overhead of position-independent code.
At reset, the address translation registers are initialised to an identity mapping, so that they can be ignored if address translation is not required.
Note that the XIP cache is fully virtually addressed, so a cache flush is required after changing the address translation.
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BASE : Physical address base for this virtual address range, in units of 4 kiB (one flash sector).
Taking a 24-bit virtual address, firstly bits 23:22 (the two MSBs) are masked to zero, and then BASE is added to bits 23:12 (the upper 12 bits) to form the physical address. Translation wraps on a 16 MiB boundary.
bits : 0 - 11 (12 bit)
access : read-write
SIZE : Translation aperture size for this virtual address range, in units of 4 kiB (one flash sector).
Bits 21:12 of the virtual address are compared to SIZE. Offsets greater than SIZE return a bus error, and do not cause a QSPI access.
bits : 16 - 26 (11 bit)
access : read-write
Configure address translation for XIP virtual addresses 0x800000 through 0xbfffff (a 4 MiB window starting at +8 MiB).
Address translation allows a program image to be executed in place at multiple physical flash addresses (for example, a double-buffered flash image for over-the-air updates), without the overhead of position-independent code.
At reset, the address translation registers are initialised to an identity mapping, so that they can be ignored if address translation is not required.
Note that the XIP cache is fully virtually addressed, so a cache flush is required after changing the address translation.
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BASE : Physical address base for this virtual address range, in units of 4 kiB (one flash sector).
Taking a 24-bit virtual address, firstly bits 23:22 (the two MSBs) are masked to zero, and then BASE is added to bits 23:12 (the upper 12 bits) to form the physical address. Translation wraps on a 16 MiB boundary.
bits : 0 - 11 (12 bit)
access : read-write
SIZE : Translation aperture size for this virtual address range, in units of 4 kiB (one flash sector).
Bits 21:12 of the virtual address are compared to SIZE. Offsets greater than SIZE return a bus error, and do not cause a QSPI access.
bits : 16 - 26 (11 bit)
access : read-write
Transmit FIFO for direct mode
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : Data pushed here will be clocked out falling edges of SCK (or before the very first rising edge of SCK, if this is the first pulse). For each byte clocked out, the interface will simultaneously sample one byte, on rising edges of SCK, and push this to the DIRECT_RX FIFO.
For 16-bit data, the least-significant byte is transmitted first.
bits : 0 - 15 (16 bit)
access : write-only
IWIDTH : Configure whether this FIFO record is transferred with single/dual/quad interface width (0/1/2). Different widths can be mixed freely.
bits : 16 - 17 (2 bit)
access : write-only
Enumeration:
0 : S
Single width
1 : D
Dual width
2 : Q
Quad width
End of enumeration elements list.
DWIDTH : Data width. If 0, hardware will transmit the 8 LSBs of the DIRECT_TX DATA field, and return an 8-bit value in the 8 LSBs of DIRECT_RX. If 1, the full 16-bit width is used. 8-bit and 16-bit transfers can be mixed freely.
bits : 18 - 18 (1 bit)
access : write-only
OE : Output enable (active-high). For single width (SPI), this field is ignored, and SD0 is always set to output, with SD1 always set to input.
For dual and quad width (DSPI/QSPI), this sets whether the relevant SDx pads are set to output whilst transferring this FIFO record. In this case the command/address should have OE set, and the data transfer should have OE set or clear depending on the direction of the transfer.
bits : 19 - 19 (1 bit)
access : write-only
NOPUSH : Inhibit the RX FIFO push that would correspond to this TX FIFO entry.
Useful to avoid garbage appearing in the RX FIFO when pushing the command at the beginning of a SPI transfer.
bits : 20 - 20 (1 bit)
access : write-only
Configure address translation for XIP virtual addresses 0xc00000 through 0xffffff (a 4 MiB window starting at +12 MiB).
Address translation allows a program image to be executed in place at multiple physical flash addresses (for example, a double-buffered flash image for over-the-air updates), without the overhead of position-independent code.
At reset, the address translation registers are initialised to an identity mapping, so that they can be ignored if address translation is not required.
Note that the XIP cache is fully virtually addressed, so a cache flush is required after changing the address translation.
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BASE : Physical address base for this virtual address range, in units of 4 kiB (one flash sector).
Taking a 24-bit virtual address, firstly bits 23:22 (the two MSBs) are masked to zero, and then BASE is added to bits 23:12 (the upper 12 bits) to form the physical address. Translation wraps on a 16 MiB boundary.
bits : 0 - 11 (12 bit)
access : read-write
SIZE : Translation aperture size for this virtual address range, in units of 4 kiB (one flash sector).
Bits 21:12 of the virtual address are compared to SIZE. Offsets greater than SIZE return a bus error, and do not cause a QSPI access.
bits : 16 - 26 (11 bit)
access : read-write
Configure address translation for XIP virtual addresses 0x1000000 through 0x13fffff (a 4 MiB window starting at +16 MiB).
Address translation allows a program image to be executed in place at multiple physical flash addresses (for example, a double-buffered flash image for over-the-air updates), without the overhead of position-independent code.
At reset, the address translation registers are initialised to an identity mapping, so that they can be ignored if address translation is not required.
Note that the XIP cache is fully virtually addressed, so a cache flush is required after changing the address translation.
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BASE : Physical address base for this virtual address range, in units of 4 kiB (one flash sector).
Taking a 24-bit virtual address, firstly bits 23:22 (the two MSBs) are masked to zero, and then BASE is added to bits 23:12 (the upper 12 bits) to form the physical address. Translation wraps on a 16 MiB boundary.
bits : 0 - 11 (12 bit)
access : read-write
SIZE : Translation aperture size for this virtual address range, in units of 4 kiB (one flash sector).
Bits 21:12 of the virtual address are compared to SIZE. Offsets greater than SIZE return a bus error, and do not cause a QSPI access.
bits : 16 - 26 (11 bit)
access : read-write
Configure address translation for XIP virtual addresses 0x1400000 through 0x17fffff (a 4 MiB window starting at +20 MiB).
Address translation allows a program image to be executed in place at multiple physical flash addresses (for example, a double-buffered flash image for over-the-air updates), without the overhead of position-independent code.
At reset, the address translation registers are initialised to an identity mapping, so that they can be ignored if address translation is not required.
Note that the XIP cache is fully virtually addressed, so a cache flush is required after changing the address translation.
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BASE : Physical address base for this virtual address range, in units of 4 kiB (one flash sector).
Taking a 24-bit virtual address, firstly bits 23:22 (the two MSBs) are masked to zero, and then BASE is added to bits 23:12 (the upper 12 bits) to form the physical address. Translation wraps on a 16 MiB boundary.
bits : 0 - 11 (12 bit)
access : read-write
SIZE : Translation aperture size for this virtual address range, in units of 4 kiB (one flash sector).
Bits 21:12 of the virtual address are compared to SIZE. Offsets greater than SIZE return a bus error, and do not cause a QSPI access.
bits : 16 - 26 (11 bit)
access : read-write
Configure address translation for XIP virtual addresses 0x1800000 through 0x1bfffff (a 4 MiB window starting at +24 MiB).
Address translation allows a program image to be executed in place at multiple physical flash addresses (for example, a double-buffered flash image for over-the-air updates), without the overhead of position-independent code.
At reset, the address translation registers are initialised to an identity mapping, so that they can be ignored if address translation is not required.
Note that the XIP cache is fully virtually addressed, so a cache flush is required after changing the address translation.
address_offset : 0x4C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BASE : Physical address base for this virtual address range, in units of 4 kiB (one flash sector).
Taking a 24-bit virtual address, firstly bits 23:22 (the two MSBs) are masked to zero, and then BASE is added to bits 23:12 (the upper 12 bits) to form the physical address. Translation wraps on a 16 MiB boundary.
bits : 0 - 11 (12 bit)
access : read-write
SIZE : Translation aperture size for this virtual address range, in units of 4 kiB (one flash sector).
Bits 21:12 of the virtual address are compared to SIZE. Offsets greater than SIZE return a bus error, and do not cause a QSPI access.
bits : 16 - 26 (11 bit)
access : read-write
Configure address translation for XIP virtual addresses 0x1c00000 through 0x1ffffff (a 4 MiB window starting at +28 MiB).
Address translation allows a program image to be executed in place at multiple physical flash addresses (for example, a double-buffered flash image for over-the-air updates), without the overhead of position-independent code.
At reset, the address translation registers are initialised to an identity mapping, so that they can be ignored if address translation is not required.
Note that the XIP cache is fully virtually addressed, so a cache flush is required after changing the address translation.
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BASE : Physical address base for this virtual address range, in units of 4 kiB (one flash sector).
Taking a 24-bit virtual address, firstly bits 23:22 (the two MSBs) are masked to zero, and then BASE is added to bits 23:12 (the upper 12 bits) to form the physical address. Translation wraps on a 16 MiB boundary.
bits : 0 - 11 (12 bit)
access : read-write
SIZE : Translation aperture size for this virtual address range, in units of 4 kiB (one flash sector).
Bits 21:12 of the virtual address are compared to SIZE. Offsets greater than SIZE return a bus error, and do not cause a QSPI access.
bits : 16 - 26 (11 bit)
access : read-write
Receive FIFO for direct mode
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DIRECT_RX : With each byte clocked out on the serial interface, one byte will simultaneously be clocked in, and will appear in this FIFO. The serial interface will stall when this FIFO is full, to avoid dropping data.
When 16-bit data is pushed into the TX FIFO, the corresponding RX FIFO push will also contain 16 bits of data. The least-significant byte is the first one received.
bits : 0 - 15 (16 bit)
access : read-only
Timing configuration register for memory address window 0.
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CLKDIV : Clock divisor. Odd and even divisors are supported. Defines the SCK clock period in units of 1 system clock cycle. Divisors 1..255 are encoded directly, and a divisor of 256 is encoded with a value of CLKDIV=0.
The clock divisor can be changed on-the-fly, even when the QMI is currently accessing memory in this address window. All other parameters must only be changed when the QMI is idle.
If software is increasing CLKDIV in anticipation of an increase in the system clock frequency, a dummy access to either memory window (and appropriate processor barriers/fences) must be inserted after the Mx_TIMING write to ensure the SCK divisor change is in effect _before_ the system clock is changed.
bits : 0 - 7 (8 bit)
access : read-write
RXDELAY : Delay the read data sample timing, in units of one half of a system clock cycle. (Not necessarily half of an SCK cycle.) An RXDELAY of 0 means the sample is captured at the SDI input registers simultaneously with the rising edge of SCK launched from the SCK output register.
At higher SCK frequencies, RXDELAY may need to be increased to account for the round trip delay of the pads, and the clock-to-Q delay of the QSPI memory device.
bits : 8 - 10 (3 bit)
access : read-write
MIN_DESELECT : After this window's chip select is deasserted, it remains deasserted for half an SCK cycle (rounded up to an integer number of system clock cycles), plus MIN_DESELECT additional system clock cycles, before the QMI reasserts either chip select pin.
Nonzero values may be required for PSRAM devices which enforce a longer minimum CS deselect time, so that they can perform internal DRAM refresh cycles whilst deselected.
bits : 12 - 16 (5 bit)
access : read-write
MAX_SELECT : Enforce a maximum assertion duration for this window's chip select, in units of 64 system clock cycles. If 0, the QMI is permitted to keep the chip select asserted indefinitely when servicing sequential memory accesses (see COOLDOWN).
This feature is required to meet timing constraints of PSRAM devices, which specify a maximum chip select assertion so they can perform DRAM refresh cycles. See also MIN_DESELECT, which can enforce a minimum deselect time.
If a memory access is in progress at the time MAX_SELECT is reached, the QMI will wait for the access to complete before deasserting the chip select. This additional time must be accounted for to calculate a safe MAX_SELECT value. In the worst case, this may be a fully-formed serial transfer, including command prefix and address, with a data payload as large as one cache line.
bits : 17 - 22 (6 bit)
access : read-write
SELECT_HOLD : Add up to three additional system clock cycles of active hold between the last falling edge of SCK and the deassertion of this window's chip select.
The default hold time is one system clock cycle. Note that flash datasheets usually give chip select active hold time from the last *rising* edge of SCK, and so even zero hold from the last falling edge would be safe.
Note that this is a minimum hold time guaranteed by the QMI: the actual chip select active hold may be slightly longer for read transfers with low clock divisors and/or high sample delays. Specifically, if the point two cycles after the last RX data sample is later than the last SCK falling edge, then the hold time is measured from *this* point.
Note also that, in case the final SCK pulse is masked to save energy (true for non-DTR reads when COOLDOWN is disabled or PAGE_BREAK is reached), all of QMI's timing logic behaves as though the clock pulse were still present. The SELECT_HOLD time is applied from the point where the last SCK falling edge would be if the clock pulse were not masked.
bits : 23 - 24 (2 bit)
access : read-write
SELECT_SETUP : Add up to one additional system clock cycle of setup between chip select assertion and the first rising edge of SCK.
The default setup time is one half SCK period, which is usually sufficient except for very high SCK frequencies with some flash devices.
bits : 25 - 25 (1 bit)
access : read-write
PAGEBREAK : When page break is enabled, chip select will automatically deassert when crossing certain power-of-2-aligned address boundaries. The next access will always begin a new read/write SPI burst, even if the address of the next access follows in sequence with the last access before the page boundary.
Some flash and PSRAM devices forbid crossing page boundaries with a single read/write transfer, or restrict the operating frequency for transfers that do cross page a boundary. This option allows the QMI to safely support those devices.
This field has no effect when COOLDOWN is disabled.
bits : 28 - 29 (2 bit)
access : read-write
Enumeration:
0 : NONE
No page boundary is enforced
1 : 256
Break bursts crossing a 256-byte page boundary
2 : 1024
Break bursts crossing a 1024-byte quad-page boundary
3 : 4096
Break bursts crossing a 4096-byte sector boundary
End of enumeration elements list.
COOLDOWN : Chip select cooldown period. When a memory transfer finishes, the chip select remains asserted for 64 x COOLDOWN system clock cycles, plus half an SCK clock period (rounded up for odd SCK divisors). After this cooldown expires, the chip select is always deasserted to save power.
If the next memory access arrives within the cooldown period, the QMI may be able to append more SCK cycles to the currently ongoing SPI transfer, rather than starting a new transfer. This reduces access latency and increases bus throughput.
Specifically, the next access must be in the same direction (read/write), access the same memory window (chip select 0/1), and follow sequentially the address of the last transfer. If any of these are false, the new access will first deassert the chip select, then begin a new transfer.
If COOLDOWN is 0, the address alignment configured by PAGEBREAK has been reached, or the total chip select assertion limit MAX_SELECT has been reached, the cooldown period is skipped, and the chip select will always be deasserted one half SCK period after the transfer finishes.
bits : 30 - 31 (2 bit)
access : read-write
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