SYSCFG

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x18 byte (0x0)
mem_usage : registers
protection :

Registers

PROC_CONFIG

MEMPOWERDOWN

AUXCTRL

PROC_IN_SYNC_BYPASS

PROC_IN_SYNC_BYPASS_HI

DBGFORCE


PROC_CONFIG

Configuration for processors
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PROC_CONFIG PROC_CONFIG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PROC0_HALTED PROC1_HALTED

PROC0_HALTED : Indication that proc0 has halted
bits : 0 - 0 (1 bit)
access : read-only

PROC1_HALTED : Indication that proc1 has halted
bits : 1 - 1 (1 bit)
access : read-only


MEMPOWERDOWN

Control PD pins to memories. Set high to put memories to a low power state. In this state the memories will retain contents but not be accessible Use with caution
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MEMPOWERDOWN MEMPOWERDOWN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SRAM0 SRAM1 SRAM2 SRAM3 SRAM4 SRAM5 SRAM6 SRAM7 SRAM8 SRAM9 USB ROM BOOTRAM

SRAM0 :
bits : 0 - 0 (1 bit)
access : read-write

SRAM1 :
bits : 1 - 1 (1 bit)
access : read-write

SRAM2 :
bits : 2 - 2 (1 bit)
access : read-write

SRAM3 :
bits : 3 - 3 (1 bit)
access : read-write

SRAM4 :
bits : 4 - 4 (1 bit)
access : read-write

SRAM5 :
bits : 5 - 5 (1 bit)
access : read-write

SRAM6 :
bits : 6 - 6 (1 bit)
access : read-write

SRAM7 :
bits : 7 - 7 (1 bit)
access : read-write

SRAM8 :
bits : 8 - 8 (1 bit)
access : read-write

SRAM9 :
bits : 9 - 9 (1 bit)
access : read-write

USB :
bits : 10 - 10 (1 bit)
access : read-write

ROM :
bits : 11 - 11 (1 bit)
access : read-write

BOOTRAM :
bits : 12 - 12 (1 bit)
access : read-write


AUXCTRL

Auxiliary system control register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AUXCTRL AUXCTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AUXCTRL

AUXCTRL : * Bits 7:2: Reserved * Bit 1: When clear, the LPOSC output is XORed into the TRNG ROSC output as an additional, uncorrelated entropy source. When set, this behaviour is disabled. * Bit 0: Force POWMAN clock to switch to LPOSC, by asserting its WDRESET input. This must be set before initiating a watchdog reset of the RSM from a stage that includes CLOCKS, if POWMAN is running from clk_ref at the point that the watchdog reset takes place. Otherwise, the short pulse generated on clk_ref by the reset of the CLOCKS block may affect POWMAN register state.
bits : 0 - 7 (8 bit)
access : read-write


PROC_IN_SYNC_BYPASS

For each bit, if 1, bypass the input synchronizer between that GPIO and the GPIO input register in the SIO. The input synchronizers should generally be unbypassed, to avoid injecting metastabilities into processors. If you're feeling brave, you can bypass to save two cycles of input latency. This register applies to GPIO 0...31.
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PROC_IN_SYNC_BYPASS PROC_IN_SYNC_BYPASS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 GPIO

GPIO :
bits : 0 - 31 (32 bit)
access : read-write


PROC_IN_SYNC_BYPASS_HI

For each bit, if 1, bypass the input synchronizer between that GPIO and the GPIO input register in the SIO. The input synchronizers should generally be unbypassed, to avoid injecting metastabilities into processors. If you're feeling brave, you can bypass to save two cycles of input latency. This register applies to GPIO 32...47. USB GPIO 56..57 QSPI GPIO 58..63
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PROC_IN_SYNC_BYPASS_HI PROC_IN_SYNC_BYPASS_HI read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 GPIO USB_DP USB_DM QSPI_SCK QSPI_CSN QSPI_SD

GPIO :
bits : 0 - 15 (16 bit)
access : read-write

USB_DP :
bits : 24 - 24 (1 bit)
access : read-write

USB_DM :
bits : 25 - 25 (1 bit)
access : read-write

QSPI_SCK :
bits : 26 - 26 (1 bit)
access : read-write

QSPI_CSN :
bits : 27 - 27 (1 bit)
access : read-write

QSPI_SD :
bits : 28 - 31 (4 bit)
access : read-write


DBGFORCE

Directly control the chip SWD debug port
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DBGFORCE DBGFORCE read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SWDO SWDI SWCLK ATTACH

SWDO : Observe the value of SWDIO output.
bits : 0 - 0 (1 bit)
access : read-only

SWDI : Directly drive SWDIO input, if ATTACH is set
bits : 1 - 1 (1 bit)
access : read-write

SWCLK : Directly drive SWCLK, if ATTACH is set
bits : 2 - 2 (1 bit)
access : read-write

ATTACH : Attach chip debug port to syscfg controls, and disconnect it from external SWD pads.
bits : 3 - 3 (1 bit)
access : read-write



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