Embeetle, an IDE designed from scratch for embedded software developers.address_offset : 0x0 Bytes (0x0)
size : 0x14 byte (0x0)
mem_usage : registers
protection :
Crystal Oscillator Control
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FREQ_RANGE : The 12-bit code is intended to give some protection against accidental writes. An invalid setting will retain the previous value. The actual value being used can be read from STATUS_FREQ_RANGE
bits : 0 - 11 (12 bit)
access : read-write
Enumeration:
2720 : 1_15MHZ
2721 : 10_30MHZ
2722 : 25_60MHZ
2723 : 40_100MHZ
End of enumeration elements list.
ENABLE : On power-up this field is initialised to DISABLE and the chip runs from the ROSC.
If the chip has subsequently been programmed to run from the XOSC then setting this field to DISABLE may lock-up the chip. If this is a concern then run the clk_ref from the ROSC and enable the clk_sys RESUS feature.
The 12-bit code is intended to give some protection against accidental writes. An invalid setting will retain the previous value. The actual value being used can be read from STATUS_ENABLED
bits : 12 - 23 (12 bit)
access : read-write
Enumeration:
3358 : DISABLE
4011 : ENABLE
End of enumeration elements list.
A down counter running at the xosc frequency which counts to zero and stops.
Can be used for short software pauses when setting up time sensitive hardware.
To start the counter, write a non-zero value. Reads will return 1 while the count is running and 0 when it has finished.
Minimum count value is 4. Count values <4 will be treated as count value =4.
Note that synchronisation to the register clock domain costs 2 register clock cycles and the counter cannot compensate for that.
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
COUNT :
bits : 0 - 15 (16 bit)
access : read-write
Crystal Oscillator Status
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FREQ_RANGE : The current frequency range setting
bits : 0 - 1 (2 bit)
access : read-only
Enumeration:
0 : 1_15MHZ
1 : 10_30MHZ
2 : 25_60MHZ
3 : 40_100MHZ
End of enumeration elements list.
ENABLED : Oscillator is enabled but not necessarily running and stable, resets to 0
bits : 12 - 12 (1 bit)
access : read-only
BADWRITE : An invalid value has been written to CTRL_ENABLE or CTRL_FREQ_RANGE or DORMANT
bits : 24 - 24 (1 bit)
access : read-write
STABLE : Oscillator is running and stable
bits : 31 - 31 (1 bit)
access : read-only
Crystal Oscillator pause control
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DORMANT : This is used to save power by pausing the XOSC
On power-up this field is initialised to WAKE
An invalid write will also select WAKE
Warning: stop the PLLs before selecting dormant mode
Warning: setup the irq before selecting dormant mode
bits : 0 - 31 (32 bit)
access : read-write
Enumeration:
1668246881 : dormant
2002873189 : WAKE
End of enumeration elements list.
Controls the startup delay
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DELAY : in multiples of 256*xtal_period. The reset value of 0xc4 corresponds to approx 50 000 cycles.
bits : 0 - 13 (14 bit)
access : read-write
X4 : Multiplies the startup_delay by 4, just in case. The reset value is controlled by a mask-programmable tiecell and is provided in case we are booting from XOSC and the default startup delay is insufficient. The reset value is 0x0.
bits : 20 - 20 (1 bit)
access : read-write
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