PLL_SYS

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x20 byte (0x0)
mem_usage : registers
protection :

Registers

CS

INTR

INTE

INTF

INTS

PWR

FBDIV_INT

PRIM


CS

Control and Status GENERAL CONSTRAINTS: Reference clock frequency min=5MHz, max=800MHz Feedback divider min=16, max=320 VCO frequency min=750MHz, max=1600MHz
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CS CS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 REFDIV BYPASS LOCK_N LOCK

REFDIV : Divides the PLL input reference clock. Behaviour is undefined for div=0. PLL output will be unpredictable during refdiv changes, wait for lock=1 before using it.
bits : 0 - 5 (6 bit)
access : read-write

BYPASS : Passes the reference clock to the output instead of the divided VCO. The VCO continues to run so the user can switch between the reference clock and the divided VCO but the output will glitch when doing so.
bits : 8 - 8 (1 bit)
access : read-write

LOCK_N : PLL is not locked Ideally this is cleared when PLL lock is seen and this should never normally be set
bits : 30 - 30 (1 bit)
access : read-write

LOCK : PLL is locked
bits : 31 - 31 (1 bit)
access : read-only


INTR

Raw Interrupts
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

INTR INTR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LOCK_N_STICKY

LOCK_N_STICKY :
bits : 0 - 0 (1 bit)
access : read-write


INTE

Interrupt Enable
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

INTE INTE read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LOCK_N_STICKY

LOCK_N_STICKY :
bits : 0 - 0 (1 bit)
access : read-write


INTF

Interrupt Force
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

INTF INTF read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LOCK_N_STICKY

LOCK_N_STICKY :
bits : 0 - 0 (1 bit)
access : read-write


INTS

Interrupt status after masking & forcing
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

INTS INTS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LOCK_N_STICKY

LOCK_N_STICKY :
bits : 0 - 0 (1 bit)
access : read-only


PWR

Controls the PLL power modes.
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PWR PWR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PD DSMPD POSTDIVPD VCOPD

PD : PLL powerdown To save power set high when PLL output not required.
bits : 0 - 0 (1 bit)
access : read-write

DSMPD : PLL DSM powerdown Nothing is achieved by setting this low.
bits : 2 - 2 (1 bit)
access : read-write

POSTDIVPD : PLL post divider powerdown To save power set high when PLL output not required or bypass=1.
bits : 3 - 3 (1 bit)
access : read-write

VCOPD : PLL VCO powerdown To save power set high when PLL output not required or bypass=1.
bits : 5 - 5 (1 bit)
access : read-write


FBDIV_INT

Feedback divisor (note: this PLL does not support fractional division)
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FBDIV_INT FBDIV_INT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FBDIV_INT

FBDIV_INT : see ctrl reg description for constraints
bits : 0 - 11 (12 bit)
access : read-write


PRIM

Controls the PLL post dividers for the primary output (note: this PLL does not have a secondary output) the primary output is driven from VCO divided by postdiv1*postdiv2
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRIM PRIM read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 POSTDIV2 POSTDIV1

POSTDIV2 : divide by 1-7
bits : 12 - 14 (3 bit)
access : read-write

POSTDIV1 : divide by 1-7
bits : 16 - 18 (3 bit)
access : read-write



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