ACCESSCTRL

Once a LOCK bit is written to 1, ACCESSCTRL silently ignores writes from that master. LOCK is writable only by a Secure, Privileged processor or debugger. LOCK bits are only writable when their value is zero. Once set, they can never be cleared, except by a full reset of ACCESSCTRL Setting the LOCK bit does not affect whether an access raises a bus error. Unprivileged writes, or writes from the DMA, will continue to raise bus errors. All other accesses will continue not to.
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CORE0 :
bits : 0 - 0 (1 bit)
access : read-write

CORE1 :
bits : 1 - 1 (1 bit)
access : read-write

DMA :
bits : 2 - 2 (1 bit)
access : read-only

DEBUG :
bits : 3 - 3 (1 bit)
access : read-write

GPIO_NSMASK1

Control whether GPIO32..47 are accessible to Non-secure code, and whether QSPI and USB bitbang are accessible through the Non-secure SIO. Writable only by a Secure, Privileged processor or debugger.
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GPIO :
bits : 0 - 15 (16 bit)
access : read-write

USB_DP :
bits : 24 - 24 (1 bit)
access : read-write

USB_DM :
bits : 25 - 25 (1 bit)
access : read-write

QSPI_SCK :
bits : 26 - 26 (1 bit)
access : read-write

QSPI_CSN :
bits : 27 - 27 (1 bit)
access : read-write

QSPI_SD :
bits : 28 - 31 (4 bit)
access : read-write

ROM

Control whether debugger, DMA, core 0 and core 1 can access ROM, and at what security/privilege levels they can do so. Defaults to fully open access. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set.
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NSU : If 1, and NSP is also set, ROM can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set.
bits : 0 - 0 (1 bit)
access : read-write

NSP : If 1, ROM can be accessed from a Non-secure, Privileged context.
bits : 1 - 1 (1 bit)
access : read-write

SU : If 1, and SP is also set, ROM can be accessed from a Secure, Unprivileged context.
bits : 2 - 2 (1 bit)
access : read-write

SP : If 1, ROM can be accessed from a Secure, Privileged context.
bits : 3 - 3 (1 bit)
access : read-write

CORE0 : If 1, ROM can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register.
bits : 4 - 4 (1 bit)
access : read-write

CORE1 : If 1, ROM can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register.
bits : 5 - 5 (1 bit)
access : read-write

DMA : If 1, ROM can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register.
bits : 6 - 6 (1 bit)
access : read-write

DBG : If 1, ROM can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register.
bits : 7 - 7 (1 bit)
access : read-write

XIP_MAIN

Control whether debugger, DMA, core 0 and core 1 can access XIP_MAIN, and at what security/privilege levels they can do so. Defaults to fully open access. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set.
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NSU : If 1, and NSP is also set, XIP_MAIN can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set.
bits : 0 - 0 (1 bit)
access : read-write

NSP : If 1, XIP_MAIN can be accessed from a Non-secure, Privileged context.
bits : 1 - 1 (1 bit)
access : read-write

SU : If 1, and SP is also set, XIP_MAIN can be accessed from a Secure, Unprivileged context.
bits : 2 - 2 (1 bit)
access : read-write

SP : If 1, XIP_MAIN can be accessed from a Secure, Privileged context.
bits : 3 - 3 (1 bit)
access : read-write

CORE0 : If 1, XIP_MAIN can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register.
bits : 4 - 4 (1 bit)
access : read-write

CORE1 : If 1, XIP_MAIN can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register.
bits : 5 - 5 (1 bit)
access : read-write

DMA : If 1, XIP_MAIN can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register.
bits : 6 - 6 (1 bit)
access : read-write

DBG : If 1, XIP_MAIN can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register.
bits : 7 - 7 (1 bit)
access : read-write

SRAM0

Control whether debugger, DMA, core 0 and core 1 can access SRAM0, and at what security/privilege levels they can do so. Defaults to fully open access. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set.
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NSU : If 1, and NSP is also set, SRAM0 can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set.
bits : 0 - 0 (1 bit)
access : read-write

NSP : If 1, SRAM0 can be accessed from a Non-secure, Privileged context.
bits : 1 - 1 (1 bit)
access : read-write

SU : If 1, and SP is also set, SRAM0 can be accessed from a Secure, Unprivileged context.
bits : 2 - 2 (1 bit)
access : read-write

SP : If 1, SRAM0 can be accessed from a Secure, Privileged context.
bits : 3 - 3 (1 bit)
access : read-write

CORE0 : If 1, SRAM0 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register.
bits : 4 - 4 (1 bit)
access : read-write

CORE1 : If 1, SRAM0 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register.
bits : 5 - 5 (1 bit)
access : read-write

DMA : If 1, SRAM0 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register.
bits : 6 - 6 (1 bit)
access : read-write

DBG : If 1, SRAM0 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register.
bits : 7 - 7 (1 bit)
access : read-write

SRAM1

Control whether debugger, DMA, core 0 and core 1 can access SRAM1, and at what security/privilege levels they can do so. Defaults to fully open access. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set.
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NSU : If 1, and NSP is also set, SRAM1 can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set.
bits : 0 - 0 (1 bit)
access : read-write

NSP : If 1, SRAM1 can be accessed from a Non-secure, Privileged context.
bits : 1 - 1 (1 bit)
access : read-write

SU : If 1, and SP is also set, SRAM1 can be accessed from a Secure, Unprivileged context.
bits : 2 - 2 (1 bit)
access : read-write

SP : If 1, SRAM1 can be accessed from a Secure, Privileged context.
bits : 3 - 3 (1 bit)
access : read-write

CORE0 : If 1, SRAM1 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register.
bits : 4 - 4 (1 bit)
access : read-write

CORE1 : If 1, SRAM1 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register.
bits : 5 - 5 (1 bit)
access : read-write

DMA : If 1, SRAM1 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register.
bits : 6 - 6 (1 bit)
access : read-write

DBG : If 1, SRAM1 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register.
bits : 7 - 7 (1 bit)
access : read-write

SRAM2

Control whether debugger, DMA, core 0 and core 1 can access SRAM2, and at what security/privilege levels they can do so. Defaults to fully open access. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set.
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NSU : If 1, and NSP is also set, SRAM2 can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set.
bits : 0 - 0 (1 bit)
access : read-write

NSP : If 1, SRAM2 can be accessed from a Non-secure, Privileged context.
bits : 1 - 1 (1 bit)
access : read-write

SU : If 1, and SP is also set, SRAM2 can be accessed from a Secure, Unprivileged context.
bits : 2 - 2 (1 bit)
access : read-write

SP : If 1, SRAM2 can be accessed from a Secure, Privileged context.
bits : 3 - 3 (1 bit)
access : read-write

CORE0 : If 1, SRAM2 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register.
bits : 4 - 4 (1 bit)
access : read-write

CORE1 : If 1, SRAM2 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register.
bits : 5 - 5 (1 bit)
access : read-write

DMA : If 1, SRAM2 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register.
bits : 6 - 6 (1 bit)
access : read-write

DBG : If 1, SRAM2 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register.
bits : 7 - 7 (1 bit)
access : read-write

SRAM3

Control whether debugger, DMA, core 0 and core 1 can access SRAM3, and at what security/privilege levels they can do so. Defaults to fully open access. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set.
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NSU : If 1, and NSP is also set, SRAM3 can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set.
bits : 0 - 0 (1 bit)
access : read-write

NSP : If 1, SRAM3 can be accessed from a Non-secure, Privileged context.
bits : 1 - 1 (1 bit)
access : read-write

SU : If 1, and SP is also set, SRAM3 can be accessed from a Secure, Unprivileged context.
bits : 2 - 2 (1 bit)
access : read-write

SP : If 1, SRAM3 can be accessed from a Secure, Privileged context.
bits : 3 - 3 (1 bit)
access : read-write

CORE0 : If 1, SRAM3 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register.
bits : 4 - 4 (1 bit)
access : read-write

CORE1 : If 1, SRAM3 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register.
bits : 5 - 5 (1 bit)
access : read-write

DMA : If 1, SRAM3 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register.
bits : 6 - 6 (1 bit)
access : read-write

DBG : If 1, SRAM3 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register.
bits : 7 - 7 (1 bit)
access : read-write

SRAM4

Control whether debugger, DMA, core 0 and core 1 can access SRAM4, and at what security/privilege levels they can do so. Defaults to fully open access. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set.
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NSU : If 1, and NSP is also set, SRAM4 can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set.
bits : 0 - 0 (1 bit)
access : read-write

NSP : If 1, SRAM4 can be accessed from a Non-secure, Privileged context.
bits : 1 - 1 (1 bit)
access : read-write

SU : If 1, and SP is also set, SRAM4 can be accessed from a Secure, Unprivileged context.
bits : 2 - 2 (1 bit)
access : read-write

SP : If 1, SRAM4 can be accessed from a Secure, Privileged context.
bits : 3 - 3 (1 bit)
access : read-write

CORE0 : If 1, SRAM4 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register.
bits : 4 - 4 (1 bit)
access : read-write

CORE1 : If 1, SRAM4 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register.
bits : 5 - 5 (1 bit)
access : read-write

DMA : If 1, SRAM4 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register.
bits : 6 - 6 (1 bit)
access : read-write

DBG : If 1, SRAM4 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register.
bits : 7 - 7 (1 bit)
access : read-write

SRAM5

Control whether debugger, DMA, core 0 and core 1 can access SRAM5, and at what security/privilege levels they can do so. Defaults to fully open access. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set.
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NSU : If 1, and NSP is also set, SRAM5 can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set.
bits : 0 - 0 (1 bit)
access : read-write

NSP : If 1, SRAM5 can be accessed from a Non-secure, Privileged context.
bits : 1 - 1 (1 bit)
access : read-write

SU : If 1, and SP is also set, SRAM5 can be accessed from a Secure, Unprivileged context.
bits : 2 - 2 (1 bit)
access : read-write

SP : If 1, SRAM5 can be accessed from a Secure, Privileged context.
bits : 3 - 3 (1 bit)
access : read-write

CORE0 : If 1, SRAM5 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register.
bits : 4 - 4 (1 bit)
access : read-write

CORE1 : If 1, SRAM5 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register.
bits : 5 - 5 (1 bit)
access : read-write

DMA : If 1, SRAM5 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register.
bits : 6 - 6 (1 bit)
access : read-write

DBG : If 1, SRAM5 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register.
bits : 7 - 7 (1 bit)
access : read-write

SRAM6

Control whether debugger, DMA, core 0 and core 1 can access SRAM6, and at what security/privilege levels they can do so. Defaults to fully open access. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set.
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NSU : If 1, and NSP is also set, SRAM6 can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set.
bits : 0 - 0 (1 bit)
access : read-write

NSP : If 1, SRAM6 can be accessed from a Non-secure, Privileged context.
bits : 1 - 1 (1 bit)
access : read-write

SU : If 1, and SP is also set, SRAM6 can be accessed from a Secure, Unprivileged context.
bits : 2 - 2 (1 bit)
access : read-write

SP : If 1, SRAM6 can be accessed from a Secure, Privileged context.
bits : 3 - 3 (1 bit)
access : read-write

CORE0 : If 1, SRAM6 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register.
bits : 4 - 4 (1 bit)
access : read-write

CORE1 : If 1, SRAM6 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register.
bits : 5 - 5 (1 bit)
access : read-write

DMA : If 1, SRAM6 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register.
bits : 6 - 6 (1 bit)
access : read-write

DBG : If 1, SRAM6 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register.
bits : 7 - 7 (1 bit)
access : read-write

SRAM7

Control whether debugger, DMA, core 0 and core 1 can access SRAM7, and at what security/privilege levels they can do so. Defaults to fully open access. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set.
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NSU : If 1, and NSP is also set, SRAM7 can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set.
bits : 0 - 0 (1 bit)
access : read-write

NSP : If 1, SRAM7 can be accessed from a Non-secure, Privileged context.
bits : 1 - 1 (1 bit)
access : read-write

SU : If 1, and SP is also set, SRAM7 can be accessed from a Secure, Unprivileged context.
bits : 2 - 2 (1 bit)
access : read-write

SP : If 1, SRAM7 can be accessed from a Secure, Privileged context.
bits : 3 - 3 (1 bit)
access : read-write

CORE0 : If 1, SRAM7 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register.
bits : 4 - 4 (1 bit)
access : read-write

CORE1 : If 1, SRAM7 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register.
bits : 5 - 5 (1 bit)
access : read-write

DMA : If 1, SRAM7 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register.
bits : 6 - 6 (1 bit)
access : read-write

DBG : If 1, SRAM7 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register.
bits : 7 - 7 (1 bit)
access : read-write

SRAM8

Control whether debugger, DMA, core 0 and core 1 can access SRAM8, and at what security/privilege levels they can do so. Defaults to fully open access. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set.
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NSU : If 1, and NSP is also set, SRAM8 can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set.
bits : 0 - 0 (1 bit)
access : read-write

NSP : If 1, SRAM8 can be accessed from a Non-secure, Privileged context.
bits : 1 - 1 (1 bit)
access : read-write

SU : If 1, and SP is also set, SRAM8 can be accessed from a Secure, Unprivileged context.
bits : 2 - 2 (1 bit)
access : read-write

SP : If 1, SRAM8 can be accessed from a Secure, Privileged context.
bits : 3 - 3 (1 bit)
access : read-write

CORE0 : If 1, SRAM8 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register.
bits : 4 - 4 (1 bit)
access : read-write

CORE1 : If 1, SRAM8 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register.
bits : 5 - 5 (1 bit)
access : read-write

DMA : If 1, SRAM8 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register.
bits : 6 - 6 (1 bit)
access : read-write

DBG : If 1, SRAM8 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register.
bits : 7 - 7 (1 bit)
access : read-write

FORCE_CORE_NS

Force core 1's bus accesses to always be Non-secure, no matter the core's internal state. Useful for schemes where one core is designated as the Non-secure core, since some peripherals may filter individual registers internally based on security state but not on master ID.
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CORE1 :
bits : 1 - 1 (1 bit)
access : read-write

SRAM9

Control whether debugger, DMA, core 0 and core 1 can access SRAM9, and at what security/privilege levels they can do so. Defaults to fully open access. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set.
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NSU : If 1, and NSP is also set, SRAM9 can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set.
bits : 0 - 0 (1 bit)
access : read-write

NSP : If 1, SRAM9 can be accessed from a Non-secure, Privileged context.
bits : 1 - 1 (1 bit)
access : read-write

SU : If 1, and SP is also set, SRAM9 can be accessed from a Secure, Unprivileged context.
bits : 2 - 2 (1 bit)
access : read-write

SP : If 1, SRAM9 can be accessed from a Secure, Privileged context.
bits : 3 - 3 (1 bit)
access : read-write

CORE0 : If 1, SRAM9 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register.
bits : 4 - 4 (1 bit)
access : read-write

CORE1 : If 1, SRAM9 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register.
bits : 5 - 5 (1 bit)
access : read-write

DMA : If 1, SRAM9 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register.
bits : 6 - 6 (1 bit)
access : read-write

DBG : If 1, SRAM9 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register.
bits : 7 - 7 (1 bit)
access : read-write

DMA

Control whether debugger, DMA, core 0 and core 1 can access DMA, and at what security/privilege levels they can do so. Defaults to Secure access from any master. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set.
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NSU : If 1, and NSP is also set, DMA can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set.
bits : 0 - 0 (1 bit)
access : read-write

NSP : If 1, DMA can be accessed from a Non-secure, Privileged context.
bits : 1 - 1 (1 bit)
access : read-write

SU : If 1, and SP is also set, DMA can be accessed from a Secure, Unprivileged context.
bits : 2 - 2 (1 bit)
access : read-write

SP : If 1, DMA can be accessed from a Secure, Privileged context.
bits : 3 - 3 (1 bit)
access : read-write

CORE0 : If 1, DMA can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register.
bits : 4 - 4 (1 bit)
access : read-write

CORE1 : If 1, DMA can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register.
bits : 5 - 5 (1 bit)
access : read-write

DMA : If 1, DMA can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register.
bits : 6 - 6 (1 bit)
access : read-write

DBG : If 1, DMA can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register.
bits : 7 - 7 (1 bit)
access : read-write

USBCTRL

Control whether debugger, DMA, core 0 and core 1 can access USBCTRL, and at what security/privilege levels they can do so. Defaults to Secure access from any master. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set.
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NSU : If 1, and NSP is also set, USBCTRL can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set.
bits : 0 - 0 (1 bit)
access : read-write

NSP : If 1, USBCTRL can be accessed from a Non-secure, Privileged context.
bits : 1 - 1 (1 bit)
access : read-write

SU : If 1, and SP is also set, USBCTRL can be accessed from a Secure, Unprivileged context.
bits : 2 - 2 (1 bit)
access : read-write

SP : If 1, USBCTRL can be accessed from a Secure, Privileged context.
bits : 3 - 3 (1 bit)
access : read-write

CORE0 : If 1, USBCTRL can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register.
bits : 4 - 4 (1 bit)
access : read-write

CORE1 : If 1, USBCTRL can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register.
bits : 5 - 5 (1 bit)
access : read-write

DMA : If 1, USBCTRL can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register.
bits : 6 - 6 (1 bit)
access : read-write

DBG : If 1, USBCTRL can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register.
bits : 7 - 7 (1 bit)
access : read-write

PIO0

Control whether debugger, DMA, core 0 and core 1 can access PIO0, and at what security/privilege levels they can do so. Defaults to Secure access from any master. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set.
address_offset : 0x4C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NSU : If 1, and NSP is also set, PIO0 can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set.
bits : 0 - 0 (1 bit)
access : read-write

NSP : If 1, PIO0 can be accessed from a Non-secure, Privileged context.
bits : 1 - 1 (1 bit)
access : read-write

SU : If 1, and SP is also set, PIO0 can be accessed from a Secure, Unprivileged context.
bits : 2 - 2 (1 bit)
access : read-write

SP : If 1, PIO0 can be accessed from a Secure, Privileged context.
bits : 3 - 3 (1 bit)
access : read-write

CORE0 : If 1, PIO0 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register.
bits : 4 - 4 (1 bit)
access : read-write

CORE1 : If 1, PIO0 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register.
bits : 5 - 5 (1 bit)
access : read-write

DMA : If 1, PIO0 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register.
bits : 6 - 6 (1 bit)
access : read-write

DBG : If 1, PIO0 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register.
bits : 7 - 7 (1 bit)
access : read-write

PIO1

Control whether debugger, DMA, core 0 and core 1 can access PIO1, and at what security/privilege levels they can do so. Defaults to Secure access from any master. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set.
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NSU : If 1, and NSP is also set, PIO1 can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set.
bits : 0 - 0 (1 bit)
access : read-write

NSP : If 1, PIO1 can be accessed from a Non-secure, Privileged context.
bits : 1 - 1 (1 bit)
access : read-write

SU : If 1, and SP is also set, PIO1 can be accessed from a Secure, Unprivileged context.
bits : 2 - 2 (1 bit)
access : read-write

SP : If 1, PIO1 can be accessed from a Secure, Privileged context.
bits : 3 - 3 (1 bit)
access : read-write

CORE0 : If 1, PIO1 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register.
bits : 4 - 4 (1 bit)
access : read-write

CORE1 : If 1, PIO1 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register.
bits : 5 - 5 (1 bit)
access : read-write

DMA : If 1, PIO1 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register.
bits : 6 - 6 (1 bit)
access : read-write

DBG : If 1, PIO1 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register.
bits : 7 - 7 (1 bit)
access : read-write

PIO2

Control whether debugger, DMA, core 0 and core 1 can access PIO2, and at what security/privilege levels they can do so. Defaults to Secure access from any master. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set.
address_offset : 0x54 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NSU : If 1, and NSP is also set, PIO2 can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set.
bits : 0 - 0 (1 bit)
access : read-write

NSP : If 1, PIO2 can be accessed from a Non-secure, Privileged context.
bits : 1 - 1 (1 bit)
access : read-write

SU : If 1, and SP is also set, PIO2 can be accessed from a Secure, Unprivileged context.
bits : 2 - 2 (1 bit)
access : read-write

SP : If 1, PIO2 can be accessed from a Secure, Privileged context.
bits : 3 - 3 (1 bit)
access : read-write

CORE0 : If 1, PIO2 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register.
bits : 4 - 4 (1 bit)
access : read-write

CORE1 : If 1, PIO2 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register.
bits : 5 - 5 (1 bit)
access : read-write

DMA : If 1, PIO2 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register.
bits : 6 - 6 (1 bit)
access : read-write

DBG : If 1, PIO2 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register.
bits : 7 - 7 (1 bit)
access : read-write

CORESIGHT_TRACE

Control whether debugger, DMA, core 0 and core 1 can access CORESIGHT_TRACE, and at what security/privilege levels they can do so. Defaults to Secure, Privileged processor or debug access only. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set.
address_offset : 0x58 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NSU : If 1, and NSP is also set, CORESIGHT_TRACE can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set.
bits : 0 - 0 (1 bit)
access : read-write

NSP : If 1, CORESIGHT_TRACE can be accessed from a Non-secure, Privileged context.
bits : 1 - 1 (1 bit)
access : read-write

SU : If 1, and SP is also set, CORESIGHT_TRACE can be accessed from a Secure, Unprivileged context.
bits : 2 - 2 (1 bit)
access : read-write

SP : If 1, CORESIGHT_TRACE can be accessed from a Secure, Privileged context.
bits : 3 - 3 (1 bit)
access : read-write

CORE0 : If 1, CORESIGHT_TRACE can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register.
bits : 4 - 4 (1 bit)
access : read-write

CORE1 : If 1, CORESIGHT_TRACE can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register.
bits : 5 - 5 (1 bit)
access : read-write

DMA : If 1, CORESIGHT_TRACE can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register.
bits : 6 - 6 (1 bit)
access : read-write

DBG : If 1, CORESIGHT_TRACE can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register.
bits : 7 - 7 (1 bit)
access : read-write

CORESIGHT_PERIPH

Control whether debugger, DMA, core 0 and core 1 can access CORESIGHT_PERIPH, and at what security/privilege levels they can do so. Defaults to Secure, Privileged processor or debug access only. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set.
address_offset : 0x5C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NSU : If 1, and NSP is also set, CORESIGHT_PERIPH can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set.
bits : 0 - 0 (1 bit)
access : read-write

NSP : If 1, CORESIGHT_PERIPH can be accessed from a Non-secure, Privileged context.
bits : 1 - 1 (1 bit)
access : read-write

SU : If 1, and SP is also set, CORESIGHT_PERIPH can be accessed from a Secure, Unprivileged context.
bits : 2 - 2 (1 bit)
access : read-write

SP : If 1, CORESIGHT_PERIPH can be accessed from a Secure, Privileged context.
bits : 3 - 3 (1 bit)
access : read-write

CORE0 : If 1, CORESIGHT_PERIPH can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register.
bits : 4 - 4 (1 bit)
access : read-write

CORE1 : If 1, CORESIGHT_PERIPH can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register.
bits : 5 - 5 (1 bit)
access : read-write

DMA : If 1, CORESIGHT_PERIPH can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register.
bits : 6 - 6 (1 bit)
access : read-write

DBG : If 1, CORESIGHT_PERIPH can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register.
bits : 7 - 7 (1 bit)
access : read-write

SYSINFO

Control whether debugger, DMA, core 0 and core 1 can access SYSINFO, and at what security/privilege levels they can do so. Defaults to fully open access. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set.
address_offset : 0x60 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NSU : If 1, and NSP is also set, SYSINFO can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set.
bits : 0 - 0 (1 bit)
access : read-write

NSP : If 1, SYSINFO can be accessed from a Non-secure, Privileged context.
bits : 1 - 1 (1 bit)
access : read-write

SU : If 1, and SP is also set, SYSINFO can be accessed from a Secure, Unprivileged context.
bits : 2 - 2 (1 bit)
access : read-write

SP : If 1, SYSINFO can be accessed from a Secure, Privileged context.
bits : 3 - 3 (1 bit)
access : read-write

CORE0 : If 1, SYSINFO can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register.
bits : 4 - 4 (1 bit)
access : read-write

CORE1 : If 1, SYSINFO can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register.
bits : 5 - 5 (1 bit)
access : read-write

DMA : If 1, SYSINFO can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register.
bits : 6 - 6 (1 bit)
access : read-write

DBG : If 1, SYSINFO can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register.
bits : 7 - 7 (1 bit)
access : read-write

RESETS

Control whether debugger, DMA, core 0 and core 1 can access RESETS, and at what security/privilege levels they can do so. Defaults to Secure access from any master. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set.
address_offset : 0x64 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NSU : If 1, and NSP is also set, RESETS can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set.
bits : 0 - 0 (1 bit)
access : read-write

NSP : If 1, RESETS can be accessed from a Non-secure, Privileged context.
bits : 1 - 1 (1 bit)
access : read-write

SU : If 1, and SP is also set, RESETS can be accessed from a Secure, Unprivileged context.
bits : 2 - 2 (1 bit)
access : read-write

SP : If 1, RESETS can be accessed from a Secure, Privileged context.
bits : 3 - 3 (1 bit)
access : read-write

CORE0 : If 1, RESETS can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register.
bits : 4 - 4 (1 bit)
access : read-write

CORE1 : If 1, RESETS can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register.
bits : 5 - 5 (1 bit)
access : read-write

DMA : If 1, RESETS can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register.
bits : 6 - 6 (1 bit)
access : read-write

DBG : If 1, RESETS can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register.
bits : 7 - 7 (1 bit)
access : read-write

IO_BANK0

Control whether debugger, DMA, core 0 and core 1 can access IO_BANK0, and at what security/privilege levels they can do so. Defaults to Secure access from any master. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set.
address_offset : 0x68 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NSU : If 1, and NSP is also set, IO_BANK0 can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set.
bits : 0 - 0 (1 bit)
access : read-write

NSP : If 1, IO_BANK0 can be accessed from a Non-secure, Privileged context.
bits : 1 - 1 (1 bit)
access : read-write

SU : If 1, and SP is also set, IO_BANK0 can be accessed from a Secure, Unprivileged context.
bits : 2 - 2 (1 bit)
access : read-write

SP : If 1, IO_BANK0 can be accessed from a Secure, Privileged context.
bits : 3 - 3 (1 bit)
access : read-write

CORE0 : If 1, IO_BANK0 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register.
bits : 4 - 4 (1 bit)
access : read-write

CORE1 : If 1, IO_BANK0 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register.
bits : 5 - 5 (1 bit)
access : read-write

DMA : If 1, IO_BANK0 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register.
bits : 6 - 6 (1 bit)
access : read-write

DBG : If 1, IO_BANK0 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register.
bits : 7 - 7 (1 bit)
access : read-write

IO_BANK1

Control whether debugger, DMA, core 0 and core 1 can access IO_BANK1, and at what security/privilege levels they can do so. Defaults to Secure access from any master. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set.
address_offset : 0x6C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NSU : If 1, and NSP is also set, IO_BANK1 can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set.
bits : 0 - 0 (1 bit)
access : read-write

NSP : If 1, IO_BANK1 can be accessed from a Non-secure, Privileged context.
bits : 1 - 1 (1 bit)
access : read-write

SU : If 1, and SP is also set, IO_BANK1 can be accessed from a Secure, Unprivileged context.
bits : 2 - 2 (1 bit)
access : read-write

SP : If 1, IO_BANK1 can be accessed from a Secure, Privileged context.
bits : 3 - 3 (1 bit)
access : read-write

CORE0 : If 1, IO_BANK1 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register.
bits : 4 - 4 (1 bit)
access : read-write

CORE1 : If 1, IO_BANK1 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register.
bits : 5 - 5 (1 bit)
access : read-write

DMA : If 1, IO_BANK1 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register.
bits : 6 - 6 (1 bit)
access : read-write

DBG : If 1, IO_BANK1 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register.
bits : 7 - 7 (1 bit)
access : read-write

PADS_BANK0

Control whether debugger, DMA, core 0 and core 1 can access PADS_BANK0, and at what security/privilege levels they can do so. Defaults to Secure access from any master. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set.
address_offset : 0x70 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NSU : If 1, and NSP is also set, PADS_BANK0 can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set.
bits : 0 - 0 (1 bit)
access : read-write

NSP : If 1, PADS_BANK0 can be accessed from a Non-secure, Privileged context.
bits : 1 - 1 (1 bit)
access : read-write

SU : If 1, and SP is also set, PADS_BANK0 can be accessed from a Secure, Unprivileged context.
bits : 2 - 2 (1 bit)
access : read-write

SP : If 1, PADS_BANK0 can be accessed from a Secure, Privileged context.
bits : 3 - 3 (1 bit)
access : read-write

CORE0 : If 1, PADS_BANK0 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register.
bits : 4 - 4 (1 bit)
access : read-write

CORE1 : If 1, PADS_BANK0 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register.
bits : 5 - 5 (1 bit)
access : read-write

DMA : If 1, PADS_BANK0 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register.
bits : 6 - 6 (1 bit)
access : read-write

DBG : If 1, PADS_BANK0 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register.
bits : 7 - 7 (1 bit)
access : read-write

PADS_QSPI

Control whether debugger, DMA, core 0 and core 1 can access PADS_QSPI, and at what security/privilege levels they can do so. Defaults to Secure access from any master. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set.
address_offset : 0x74 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NSU : If 1, and NSP is also set, PADS_QSPI can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set.
bits : 0 - 0 (1 bit)
access : read-write

NSP : If 1, PADS_QSPI can be accessed from a Non-secure, Privileged context.
bits : 1 - 1 (1 bit)
access : read-write

SU : If 1, and SP is also set, PADS_QSPI can be accessed from a Secure, Unprivileged context.
bits : 2 - 2 (1 bit)
access : read-write

SP : If 1, PADS_QSPI can be accessed from a Secure, Privileged context.
bits : 3 - 3 (1 bit)
access : read-write

CORE0 : If 1, PADS_QSPI can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register.
bits : 4 - 4 (1 bit)
access : read-write

CORE1 : If 1, PADS_QSPI can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register.
bits : 5 - 5 (1 bit)
access : read-write

DMA : If 1, PADS_QSPI can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register.
bits : 6 - 6 (1 bit)
access : read-write

DBG : If 1, PADS_QSPI can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register.
bits : 7 - 7 (1 bit)
access : read-write

BUSCTRL

Control whether debugger, DMA, core 0 and core 1 can access BUSCTRL, and at what security/privilege levels they can do so. Defaults to Secure access from any master. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set.
address_offset : 0x78 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NSU : If 1, and NSP is also set, BUSCTRL can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set.
bits : 0 - 0 (1 bit)
access : read-write

NSP : If 1, BUSCTRL can be accessed from a Non-secure, Privileged context.
bits : 1 - 1 (1 bit)
access : read-write

SU : If 1, and SP is also set, BUSCTRL can be accessed from a Secure, Unprivileged context.
bits : 2 - 2 (1 bit)
access : read-write

SP : If 1, BUSCTRL can be accessed from a Secure, Privileged context.
bits : 3 - 3 (1 bit)
access : read-write

CORE0 : If 1, BUSCTRL can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register.
bits : 4 - 4 (1 bit)
access : read-write

CORE1 : If 1, BUSCTRL can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register.
bits : 5 - 5 (1 bit)
access : read-write

DMA : If 1, BUSCTRL can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register.
bits : 6 - 6 (1 bit)
access : read-write

DBG : If 1, BUSCTRL can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register.
bits : 7 - 7 (1 bit)
access : read-write

ADC0

Control whether debugger, DMA, core 0 and core 1 can access ADC0, and at what security/privilege levels they can do so. Defaults to Secure access from any master. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set.
address_offset : 0x7C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NSU : If 1, and NSP is also set, ADC0 can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set.
bits : 0 - 0 (1 bit)
access : read-write

NSP : If 1, ADC0 can be accessed from a Non-secure, Privileged context.
bits : 1 - 1 (1 bit)
access : read-write

SU : If 1, and SP is also set, ADC0 can be accessed from a Secure, Unprivileged context.
bits : 2 - 2 (1 bit)
access : read-write

SP : If 1, ADC0 can be accessed from a Secure, Privileged context.
bits : 3 - 3 (1 bit)
access : read-write

CORE0 : If 1, ADC0 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register.
bits : 4 - 4 (1 bit)
access : read-write

CORE1 : If 1, ADC0 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register.
bits : 5 - 5 (1 bit)
access : read-write

DMA : If 1, ADC0 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register.
bits : 6 - 6 (1 bit)
access : read-write

DBG : If 1, ADC0 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register.
bits : 7 - 7 (1 bit)
access : read-write

CFGRESET

Write 1 to reset all ACCESSCTRL configuration, except for the LOCK and FORCE_CORE_NS registers. This bit is used in the RP2350 bootrom to quickly restore ACCESSCTRL to a known state during the boot path. Note that, like all registers in ACCESSCTRL, this register is not writable when the writer's corresponding LOCK bit is set, therefore a master which has been locked out of ACCESSCTRL can not use the CFGRESET register to disturb its contents.
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CFGRESET :
bits : 0 - 0 (1 bit)
access : write-only

HSTX

Control whether debugger, DMA, core 0 and core 1 can access HSTX, and at what security/privilege levels they can do so. Defaults to Secure access from any master. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set.
address_offset : 0x80 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NSU : If 1, and NSP is also set, HSTX can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set.
bits : 0 - 0 (1 bit)
access : read-write

NSP : If 1, HSTX can be accessed from a Non-secure, Privileged context.
bits : 1 - 1 (1 bit)
access : read-write

SU : If 1, and SP is also set, HSTX can be accessed from a Secure, Unprivileged context.
bits : 2 - 2 (1 bit)
access : read-write

SP : If 1, HSTX can be accessed from a Secure, Privileged context.
bits : 3 - 3 (1 bit)
access : read-write

CORE0 : If 1, HSTX can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register.
bits : 4 - 4 (1 bit)
access : read-write

CORE1 : If 1, HSTX can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register.
bits : 5 - 5 (1 bit)
access : read-write

DMA : If 1, HSTX can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register.
bits : 6 - 6 (1 bit)
access : read-write

DBG : If 1, HSTX can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register.
bits : 7 - 7 (1 bit)
access : read-write

I2C0

Control whether debugger, DMA, core 0 and core 1 can access I2C0, and at what security/privilege levels they can do so. Defaults to Secure access from any master. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set.
address_offset : 0x84 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NSU : If 1, and NSP is also set, I2C0 can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set.
bits : 0 - 0 (1 bit)
access : read-write

NSP : If 1, I2C0 can be accessed from a Non-secure, Privileged context.
bits : 1 - 1 (1 bit)
access : read-write

SU : If 1, and SP is also set, I2C0 can be accessed from a Secure, Unprivileged context.
bits : 2 - 2 (1 bit)
access : read-write

SP : If 1, I2C0 can be accessed from a Secure, Privileged context.
bits : 3 - 3 (1 bit)
access : read-write

CORE0 : If 1, I2C0 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register.
bits : 4 - 4 (1 bit)
access : read-write

CORE1 : If 1, I2C0 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register.
bits : 5 - 5 (1 bit)
access : read-write

DMA : If 1, I2C0 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register.
bits : 6 - 6 (1 bit)
access : read-write

DBG : If 1, I2C0 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register.
bits : 7 - 7 (1 bit)
access : read-write

I2C1

Control whether debugger, DMA, core 0 and core 1 can access I2C1, and at what security/privilege levels they can do so. Defaults to Secure access from any master. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set.
address_offset : 0x88 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NSU : If 1, and NSP is also set, I2C1 can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set.
bits : 0 - 0 (1 bit)
access : read-write

NSP : If 1, I2C1 can be accessed from a Non-secure, Privileged context.
bits : 1 - 1 (1 bit)
access : read-write

SU : If 1, and SP is also set, I2C1 can be accessed from a Secure, Unprivileged context.
bits : 2 - 2 (1 bit)
access : read-write

SP : If 1, I2C1 can be accessed from a Secure, Privileged context.
bits : 3 - 3 (1 bit)
access : read-write

CORE0 : If 1, I2C1 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register.
bits : 4 - 4 (1 bit)
access : read-write

CORE1 : If 1, I2C1 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register.
bits : 5 - 5 (1 bit)
access : read-write

DMA : If 1, I2C1 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register.
bits : 6 - 6 (1 bit)
access : read-write

DBG : If 1, I2C1 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register.
bits : 7 - 7 (1 bit)
access : read-write

PWM

Control whether debugger, DMA, core 0 and core 1 can access PWM, and at what security/privilege levels they can do so. Defaults to Secure access from any master. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set.
address_offset : 0x8C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NSU : If 1, and NSP is also set, PWM can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set.
bits : 0 - 0 (1 bit)
access : read-write

NSP : If 1, PWM can be accessed from a Non-secure, Privileged context.
bits : 1 - 1 (1 bit)
access : read-write

SU : If 1, and SP is also set, PWM can be accessed from a Secure, Unprivileged context.
bits : 2 - 2 (1 bit)
access : read-write

SP : If 1, PWM can be accessed from a Secure, Privileged context.
bits : 3 - 3 (1 bit)
access : read-write

CORE0 : If 1, PWM can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register.
bits : 4 - 4 (1 bit)
access : read-write

CORE1 : If 1, PWM can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register.
bits : 5 - 5 (1 bit)
access : read-write

DMA : If 1, PWM can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register.
bits : 6 - 6 (1 bit)
access : read-write

DBG : If 1, PWM can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register.
bits : 7 - 7 (1 bit)
access : read-write

SPI0

Control whether debugger, DMA, core 0 and core 1 can access SPI0, and at what security/privilege levels they can do so. Defaults to Secure access from any master. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set.
address_offset : 0x90 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NSU : If 1, and NSP is also set, SPI0 can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set.
bits : 0 - 0 (1 bit)
access : read-write

NSP : If 1, SPI0 can be accessed from a Non-secure, Privileged context.
bits : 1 - 1 (1 bit)
access : read-write

SU : If 1, and SP is also set, SPI0 can be accessed from a Secure, Unprivileged context.
bits : 2 - 2 (1 bit)
access : read-write

SP : If 1, SPI0 can be accessed from a Secure, Privileged context.
bits : 3 - 3 (1 bit)
access : read-write

CORE0 : If 1, SPI0 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register.
bits : 4 - 4 (1 bit)
access : read-write

CORE1 : If 1, SPI0 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register.
bits : 5 - 5 (1 bit)
access : read-write

DMA : If 1, SPI0 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register.
bits : 6 - 6 (1 bit)
access : read-write

DBG : If 1, SPI0 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register.
bits : 7 - 7 (1 bit)
access : read-write

SPI1

Control whether debugger, DMA, core 0 and core 1 can access SPI1, and at what security/privilege levels they can do so. Defaults to Secure access from any master. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set.
address_offset : 0x94 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NSU : If 1, and NSP is also set, SPI1 can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set.
bits : 0 - 0 (1 bit)
access : read-write

NSP : If 1, SPI1 can be accessed from a Non-secure, Privileged context.
bits : 1 - 1 (1 bit)
access : read-write

SU : If 1, and SP is also set, SPI1 can be accessed from a Secure, Unprivileged context.
bits : 2 - 2 (1 bit)
access : read-write

SP : If 1, SPI1 can be accessed from a Secure, Privileged context.
bits : 3 - 3 (1 bit)
access : read-write

CORE0 : If 1, SPI1 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register.
bits : 4 - 4 (1 bit)
access : read-write

CORE1 : If 1, SPI1 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register.
bits : 5 - 5 (1 bit)
access : read-write

DMA : If 1, SPI1 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register.
bits : 6 - 6 (1 bit)
access : read-write

DBG : If 1, SPI1 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register.
bits : 7 - 7 (1 bit)
access : read-write

TIMER0

Control whether debugger, DMA, core 0 and core 1 can access TIMER0, and at what security/privilege levels they can do so. Defaults to Secure access from any master. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set.
address_offset : 0x98 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NSU : If 1, and NSP is also set, TIMER0 can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set.
bits : 0 - 0 (1 bit)
access : read-write

NSP : If 1, TIMER0 can be accessed from a Non-secure, Privileged context.
bits : 1 - 1 (1 bit)
access : read-write

SU : If 1, and SP is also set, TIMER0 can be accessed from a Secure, Unprivileged context.
bits : 2 - 2 (1 bit)
access : read-write

SP : If 1, TIMER0 can be accessed from a Secure, Privileged context.
bits : 3 - 3 (1 bit)
access : read-write

CORE0 : If 1, TIMER0 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register.
bits : 4 - 4 (1 bit)
access : read-write

CORE1 : If 1, TIMER0 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register.
bits : 5 - 5 (1 bit)
access : read-write

DMA : If 1, TIMER0 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register.
bits : 6 - 6 (1 bit)
access : read-write

DBG : If 1, TIMER0 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register.
bits : 7 - 7 (1 bit)
access : read-write

TIMER1

Control whether debugger, DMA, core 0 and core 1 can access TIMER1, and at what security/privilege levels they can do so. Defaults to Secure access from any master. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set.
address_offset : 0x9C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NSU : If 1, and NSP is also set, TIMER1 can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set.
bits : 0 - 0 (1 bit)
access : read-write

NSP : If 1, TIMER1 can be accessed from a Non-secure, Privileged context.
bits : 1 - 1 (1 bit)
access : read-write

SU : If 1, and SP is also set, TIMER1 can be accessed from a Secure, Unprivileged context.
bits : 2 - 2 (1 bit)
access : read-write

SP : If 1, TIMER1 can be accessed from a Secure, Privileged context.
bits : 3 - 3 (1 bit)
access : read-write

CORE0 : If 1, TIMER1 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register.
bits : 4 - 4 (1 bit)
access : read-write

CORE1 : If 1, TIMER1 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register.
bits : 5 - 5 (1 bit)
access : read-write

DMA : If 1, TIMER1 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register.
bits : 6 - 6 (1 bit)
access : read-write

DBG : If 1, TIMER1 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register.
bits : 7 - 7 (1 bit)
access : read-write

UART0

Control whether debugger, DMA, core 0 and core 1 can access UART0, and at what security/privilege levels they can do so. Defaults to Secure access from any master. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set.
address_offset : 0xA0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NSU : If 1, and NSP is also set, UART0 can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set.
bits : 0 - 0 (1 bit)
access : read-write

NSP : If 1, UART0 can be accessed from a Non-secure, Privileged context.
bits : 1 - 1 (1 bit)
access : read-write

SU : If 1, and SP is also set, UART0 can be accessed from a Secure, Unprivileged context.
bits : 2 - 2 (1 bit)
access : read-write

SP : If 1, UART0 can be accessed from a Secure, Privileged context.
bits : 3 - 3 (1 bit)
access : read-write

CORE0 : If 1, UART0 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register.
bits : 4 - 4 (1 bit)
access : read-write

CORE1 : If 1, UART0 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register.
bits : 5 - 5 (1 bit)
access : read-write

DMA : If 1, UART0 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register.
bits : 6 - 6 (1 bit)
access : read-write

DBG : If 1, UART0 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register.
bits : 7 - 7 (1 bit)
access : read-write

UART1

Control whether debugger, DMA, core 0 and core 1 can access UART1, and at what security/privilege levels they can do so. Defaults to Secure access from any master. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set.
address_offset : 0xA4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NSU : If 1, and NSP is also set, UART1 can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set.
bits : 0 - 0 (1 bit)
access : read-write

NSP : If 1, UART1 can be accessed from a Non-secure, Privileged context.
bits : 1 - 1 (1 bit)
access : read-write

SU : If 1, and SP is also set, UART1 can be accessed from a Secure, Unprivileged context.
bits : 2 - 2 (1 bit)
access : read-write

SP : If 1, UART1 can be accessed from a Secure, Privileged context.
bits : 3 - 3 (1 bit)
access : read-write

CORE0 : If 1, UART1 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register.
bits : 4 - 4 (1 bit)
access : read-write

CORE1 : If 1, UART1 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register.
bits : 5 - 5 (1 bit)
access : read-write

DMA : If 1, UART1 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register.
bits : 6 - 6 (1 bit)
access : read-write

DBG : If 1, UART1 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register.
bits : 7 - 7 (1 bit)
access : read-write

OTP

Control whether debugger, DMA, core 0 and core 1 can access OTP, and at what security/privilege levels they can do so. Defaults to Secure access from any master. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set.
address_offset : 0xA8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NSU : If 1, and NSP is also set, OTP can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set.
bits : 0 - 0 (1 bit)
access : read-write

NSP : If 1, OTP can be accessed from a Non-secure, Privileged context.
bits : 1 - 1 (1 bit)
access : read-write

SU : If 1, and SP is also set, OTP can be accessed from a Secure, Unprivileged context.
bits : 2 - 2 (1 bit)
access : read-write

SP : If 1, OTP can be accessed from a Secure, Privileged context.
bits : 3 - 3 (1 bit)
access : read-write

CORE0 : If 1, OTP can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register.
bits : 4 - 4 (1 bit)
access : read-write

CORE1 : If 1, OTP can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register.
bits : 5 - 5 (1 bit)
access : read-write

DMA : If 1, OTP can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register.
bits : 6 - 6 (1 bit)
access : read-write

DBG : If 1, OTP can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register.
bits : 7 - 7 (1 bit)
access : read-write

TBMAN

Control whether debugger, DMA, core 0 and core 1 can access TBMAN, and at what security/privilege levels they can do so. Defaults to Secure access from any master. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set.
address_offset : 0xAC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NSU : If 1, and NSP is also set, TBMAN can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set.
bits : 0 - 0 (1 bit)
access : read-write

NSP : If 1, TBMAN can be accessed from a Non-secure, Privileged context.
bits : 1 - 1 (1 bit)
access : read-write

SU : If 1, and SP is also set, TBMAN can be accessed from a Secure, Unprivileged context.
bits : 2 - 2 (1 bit)
access : read-write

SP : If 1, TBMAN can be accessed from a Secure, Privileged context.
bits : 3 - 3 (1 bit)
access : read-write

CORE0 : If 1, TBMAN can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register.
bits : 4 - 4 (1 bit)
access : read-write

CORE1 : If 1, TBMAN can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register.
bits : 5 - 5 (1 bit)
access : read-write

DMA : If 1, TBMAN can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register.
bits : 6 - 6 (1 bit)
access : read-write

DBG : If 1, TBMAN can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register.
bits : 7 - 7 (1 bit)
access : read-write

POWMAN

Control whether debugger, DMA, core 0 and core 1 can access POWMAN, and at what security/privilege levels they can do so. Defaults to Secure, Privileged processor or debug access only. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set.
address_offset : 0xB0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NSU : If 1, and NSP is also set, POWMAN can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set.
bits : 0 - 0 (1 bit)
access : read-write

NSP : If 1, POWMAN can be accessed from a Non-secure, Privileged context.
bits : 1 - 1 (1 bit)
access : read-write

SU : If 1, and SP is also set, POWMAN can be accessed from a Secure, Unprivileged context.
bits : 2 - 2 (1 bit)
access : read-write

SP : If 1, POWMAN can be accessed from a Secure, Privileged context.
bits : 3 - 3 (1 bit)
access : read-write

CORE0 : If 1, POWMAN can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register.
bits : 4 - 4 (1 bit)
access : read-write

CORE1 : If 1, POWMAN can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register.
bits : 5 - 5 (1 bit)
access : read-write

DMA : If 1, POWMAN can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register.
bits : 6 - 6 (1 bit)
access : read-write

DBG : If 1, POWMAN can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register.
bits : 7 - 7 (1 bit)
access : read-write

TRNG

Control whether debugger, DMA, core 0 and core 1 can access TRNG, and at what security/privilege levels they can do so. Defaults to Secure, Privileged processor or debug access only. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set.
address_offset : 0xB4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NSU : If 1, and NSP is also set, TRNG can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set.
bits : 0 - 0 (1 bit)
access : read-write

NSP : If 1, TRNG can be accessed from a Non-secure, Privileged context.
bits : 1 - 1 (1 bit)
access : read-write

SU : If 1, and SP is also set, TRNG can be accessed from a Secure, Unprivileged context.
bits : 2 - 2 (1 bit)
access : read-write

SP : If 1, TRNG can be accessed from a Secure, Privileged context.
bits : 3 - 3 (1 bit)
access : read-write

CORE0 : If 1, TRNG can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register.
bits : 4 - 4 (1 bit)
access : read-write

CORE1 : If 1, TRNG can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register.
bits : 5 - 5 (1 bit)
access : read-write

DMA : If 1, TRNG can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register.
bits : 6 - 6 (1 bit)
access : read-write

DBG : If 1, TRNG can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register.
bits : 7 - 7 (1 bit)
access : read-write

SHA256

Control whether debugger, DMA, core 0 and core 1 can access SHA256, and at what security/privilege levels they can do so. Defaults to Secure, Privileged access only. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set.
address_offset : 0xB8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NSU : If 1, and NSP is also set, SHA256 can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set.
bits : 0 - 0 (1 bit)
access : read-write

NSP : If 1, SHA256 can be accessed from a Non-secure, Privileged context.
bits : 1 - 1 (1 bit)
access : read-write

SU : If 1, and SP is also set, SHA256 can be accessed from a Secure, Unprivileged context.
bits : 2 - 2 (1 bit)
access : read-write

SP : If 1, SHA256 can be accessed from a Secure, Privileged context.
bits : 3 - 3 (1 bit)
access : read-write

CORE0 : If 1, SHA256 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register.
bits : 4 - 4 (1 bit)
access : read-write

CORE1 : If 1, SHA256 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register.
bits : 5 - 5 (1 bit)
access : read-write

DMA : If 1, SHA256 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register.
bits : 6 - 6 (1 bit)
access : read-write

DBG : If 1, SHA256 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register.
bits : 7 - 7 (1 bit)
access : read-write

SYSCFG

Control whether debugger, DMA, core 0 and core 1 can access SYSCFG, and at what security/privilege levels they can do so. Defaults to Secure, Privileged processor or debug access only. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set.
address_offset : 0xBC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NSU : If 1, and NSP is also set, SYSCFG can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set.
bits : 0 - 0 (1 bit)
access : read-write

NSP : If 1, SYSCFG can be accessed from a Non-secure, Privileged context.
bits : 1 - 1 (1 bit)
access : read-write

SU : If 1, and SP is also set, SYSCFG can be accessed from a Secure, Unprivileged context.
bits : 2 - 2 (1 bit)
access : read-write

SP : If 1, SYSCFG can be accessed from a Secure, Privileged context.
bits : 3 - 3 (1 bit)
access : read-write

CORE0 : If 1, SYSCFG can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register.
bits : 4 - 4 (1 bit)
access : read-write

CORE1 : If 1, SYSCFG can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register.
bits : 5 - 5 (1 bit)
access : read-write

DMA : If 1, SYSCFG can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register.
bits : 6 - 6 (1 bit)
access : read-write

DBG : If 1, SYSCFG can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register.
bits : 7 - 7 (1 bit)
access : read-write

GPIO_NSMASK0

Control whether GPIO0...31 are accessible to Non-secure code. Writable only by a Secure, Privileged processor or debugger. 0 -> Secure access only 1 -> Secure + Non-secure access
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GPIO_NSMASK0 :
bits : 0 - 31 (32 bit)
access : read-write

CLOCKS

Control whether debugger, DMA, core 0 and core 1 can access CLOCKS, and at what security/privilege levels they can do so. Defaults to Secure, Privileged processor or debug access only. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set.
address_offset : 0xC0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NSU : If 1, and NSP is also set, CLOCKS can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set.
bits : 0 - 0 (1 bit)
access : read-write

NSP : If 1, CLOCKS can be accessed from a Non-secure, Privileged context.
bits : 1 - 1 (1 bit)
access : read-write

SU : If 1, and SP is also set, CLOCKS can be accessed from a Secure, Unprivileged context.
bits : 2 - 2 (1 bit)
access : read-write

SP : If 1, CLOCKS can be accessed from a Secure, Privileged context.
bits : 3 - 3 (1 bit)
access : read-write

CORE0 : If 1, CLOCKS can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register.
bits : 4 - 4 (1 bit)
access : read-write

CORE1 : If 1, CLOCKS can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register.
bits : 5 - 5 (1 bit)
access : read-write

DMA : If 1, CLOCKS can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register.
bits : 6 - 6 (1 bit)
access : read-write

DBG : If 1, CLOCKS can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register.
bits : 7 - 7 (1 bit)
access : read-write

XOSC

Control whether debugger, DMA, core 0 and core 1 can access XOSC, and at what security/privilege levels they can do so. Defaults to Secure, Privileged processor or debug access only. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set.
address_offset : 0xC4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NSU : If 1, and NSP is also set, XOSC can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set.
bits : 0 - 0 (1 bit)
access : read-write

NSP : If 1, XOSC can be accessed from a Non-secure, Privileged context.
bits : 1 - 1 (1 bit)
access : read-write

SU : If 1, and SP is also set, XOSC can be accessed from a Secure, Unprivileged context.
bits : 2 - 2 (1 bit)
access : read-write

SP : If 1, XOSC can be accessed from a Secure, Privileged context.
bits : 3 - 3 (1 bit)
access : read-write

CORE0 : If 1, XOSC can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register.
bits : 4 - 4 (1 bit)
access : read-write

CORE1 : If 1, XOSC can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register.
bits : 5 - 5 (1 bit)
access : read-write

DMA : If 1, XOSC can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register.
bits : 6 - 6 (1 bit)
access : read-write

DBG : If 1, XOSC can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register.
bits : 7 - 7 (1 bit)
access : read-write

ROSC

Control whether debugger, DMA, core 0 and core 1 can access ROSC, and at what security/privilege levels they can do so. Defaults to Secure, Privileged processor or debug access only. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set.
address_offset : 0xC8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NSU : If 1, and NSP is also set, ROSC can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set.
bits : 0 - 0 (1 bit)
access : read-write

NSP : If 1, ROSC can be accessed from a Non-secure, Privileged context.
bits : 1 - 1 (1 bit)
access : read-write

SU : If 1, and SP is also set, ROSC can be accessed from a Secure, Unprivileged context.
bits : 2 - 2 (1 bit)
access : read-write

SP : If 1, ROSC can be accessed from a Secure, Privileged context.
bits : 3 - 3 (1 bit)
access : read-write

CORE0 : If 1, ROSC can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register.
bits : 4 - 4 (1 bit)
access : read-write

CORE1 : If 1, ROSC can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register.
bits : 5 - 5 (1 bit)
access : read-write

DMA : If 1, ROSC can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register.
bits : 6 - 6 (1 bit)
access : read-write

DBG : If 1, ROSC can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register.
bits : 7 - 7 (1 bit)
access : read-write

PLL_SYS

Control whether debugger, DMA, core 0 and core 1 can access PLL_SYS, and at what security/privilege levels they can do so. Defaults to Secure, Privileged processor or debug access only. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set.
address_offset : 0xCC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NSU : If 1, and NSP is also set, PLL_SYS can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set.
bits : 0 - 0 (1 bit)
access : read-write

NSP : If 1, PLL_SYS can be accessed from a Non-secure, Privileged context.
bits : 1 - 1 (1 bit)
access : read-write

SU : If 1, and SP is also set, PLL_SYS can be accessed from a Secure, Unprivileged context.
bits : 2 - 2 (1 bit)
access : read-write

SP : If 1, PLL_SYS can be accessed from a Secure, Privileged context.
bits : 3 - 3 (1 bit)
access : read-write

CORE0 : If 1, PLL_SYS can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register.
bits : 4 - 4 (1 bit)
access : read-write

CORE1 : If 1, PLL_SYS can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register.
bits : 5 - 5 (1 bit)
access : read-write

DMA : If 1, PLL_SYS can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register.
bits : 6 - 6 (1 bit)
access : read-write

DBG : If 1, PLL_SYS can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register.
bits : 7 - 7 (1 bit)
access : read-write

PLL_USB

Control whether debugger, DMA, core 0 and core 1 can access PLL_USB, and at what security/privilege levels they can do so. Defaults to Secure, Privileged processor or debug access only. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set.
address_offset : 0xD0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NSU : If 1, and NSP is also set, PLL_USB can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set.
bits : 0 - 0 (1 bit)
access : read-write

NSP : If 1, PLL_USB can be accessed from a Non-secure, Privileged context.
bits : 1 - 1 (1 bit)
access : read-write

SU : If 1, and SP is also set, PLL_USB can be accessed from a Secure, Unprivileged context.
bits : 2 - 2 (1 bit)
access : read-write

SP : If 1, PLL_USB can be accessed from a Secure, Privileged context.
bits : 3 - 3 (1 bit)
access : read-write

CORE0 : If 1, PLL_USB can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register.
bits : 4 - 4 (1 bit)
access : read-write

CORE1 : If 1, PLL_USB can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register.
bits : 5 - 5 (1 bit)
access : read-write

DMA : If 1, PLL_USB can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register.
bits : 6 - 6 (1 bit)
access : read-write

DBG : If 1, PLL_USB can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register.
bits : 7 - 7 (1 bit)
access : read-write

TICKS

Control whether debugger, DMA, core 0 and core 1 can access TICKS, and at what security/privilege levels they can do so. Defaults to Secure, Privileged processor or debug access only. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set.
address_offset : 0xD4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NSU : If 1, and NSP is also set, TICKS can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set.
bits : 0 - 0 (1 bit)
access : read-write

NSP : If 1, TICKS can be accessed from a Non-secure, Privileged context.
bits : 1 - 1 (1 bit)
access : read-write

SU : If 1, and SP is also set, TICKS can be accessed from a Secure, Unprivileged context.
bits : 2 - 2 (1 bit)
access : read-write

SP : If 1, TICKS can be accessed from a Secure, Privileged context.
bits : 3 - 3 (1 bit)
access : read-write

CORE0 : If 1, TICKS can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register.
bits : 4 - 4 (1 bit)
access : read-write

CORE1 : If 1, TICKS can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register.
bits : 5 - 5 (1 bit)
access : read-write

DMA : If 1, TICKS can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register.
bits : 6 - 6 (1 bit)
access : read-write

DBG : If 1, TICKS can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register.
bits : 7 - 7 (1 bit)
access : read-write

WATCHDOG

Control whether debugger, DMA, core 0 and core 1 can access WATCHDOG, and at what security/privilege levels they can do so. Defaults to Secure, Privileged processor or debug access only. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set.
address_offset : 0xD8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NSU : If 1, and NSP is also set, WATCHDOG can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set.
bits : 0 - 0 (1 bit)
access : read-write

NSP : If 1, WATCHDOG can be accessed from a Non-secure, Privileged context.
bits : 1 - 1 (1 bit)
access : read-write

SU : If 1, and SP is also set, WATCHDOG can be accessed from a Secure, Unprivileged context.
bits : 2 - 2 (1 bit)
access : read-write

SP : If 1, WATCHDOG can be accessed from a Secure, Privileged context.
bits : 3 - 3 (1 bit)
access : read-write

CORE0 : If 1, WATCHDOG can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register.
bits : 4 - 4 (1 bit)
access : read-write

CORE1 : If 1, WATCHDOG can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register.
bits : 5 - 5 (1 bit)
access : read-write

DMA : If 1, WATCHDOG can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register.
bits : 6 - 6 (1 bit)
access : read-write

DBG : If 1, WATCHDOG can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register.
bits : 7 - 7 (1 bit)
access : read-write

RSM

Control whether debugger, DMA, core 0 and core 1 can access RSM, and at what security/privilege levels they can do so. Defaults to Secure, Privileged processor or debug access only. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set.
address_offset : 0xDC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NSU : If 1, and NSP is also set, RSM can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set.
bits : 0 - 0 (1 bit)
access : read-write

NSP : If 1, RSM can be accessed from a Non-secure, Privileged context.
bits : 1 - 1 (1 bit)
access : read-write

SU : If 1, and SP is also set, RSM can be accessed from a Secure, Unprivileged context.
bits : 2 - 2 (1 bit)
access : read-write

SP : If 1, RSM can be accessed from a Secure, Privileged context.
bits : 3 - 3 (1 bit)
access : read-write

CORE0 : If 1, RSM can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register.
bits : 4 - 4 (1 bit)
access : read-write

CORE1 : If 1, RSM can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register.
bits : 5 - 5 (1 bit)
access : read-write

DMA : If 1, RSM can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register.
bits : 6 - 6 (1 bit)
access : read-write

DBG : If 1, RSM can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register.
bits : 7 - 7 (1 bit)
access : read-write

XIP_CTRL

Control whether debugger, DMA, core 0 and core 1 can access XIP_CTRL, and at what security/privilege levels they can do so. Defaults to Secure, Privileged processor or debug access only. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set.
address_offset : 0xE0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NSU : If 1, and NSP is also set, XIP_CTRL can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set.
bits : 0 - 0 (1 bit)
access : read-write

NSP : If 1, XIP_CTRL can be accessed from a Non-secure, Privileged context.
bits : 1 - 1 (1 bit)
access : read-write

SU : If 1, and SP is also set, XIP_CTRL can be accessed from a Secure, Unprivileged context.
bits : 2 - 2 (1 bit)
access : read-write

SP : If 1, XIP_CTRL can be accessed from a Secure, Privileged context.
bits : 3 - 3 (1 bit)
access : read-write

CORE0 : If 1, XIP_CTRL can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register.
bits : 4 - 4 (1 bit)
access : read-write

CORE1 : If 1, XIP_CTRL can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register.
bits : 5 - 5 (1 bit)
access : read-write

DMA : If 1, XIP_CTRL can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register.
bits : 6 - 6 (1 bit)
access : read-write

DBG : If 1, XIP_CTRL can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register.
bits : 7 - 7 (1 bit)
access : read-write

XIP_QMI

Control whether debugger, DMA, core 0 and core 1 can access XIP_QMI, and at what security/privilege levels they can do so. Defaults to Secure, Privileged processor or debug access only. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set.
address_offset : 0xE4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NSU : If 1, and NSP is also set, XIP_QMI can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set.
bits : 0 - 0 (1 bit)
access : read-write

NSP : If 1, XIP_QMI can be accessed from a Non-secure, Privileged context.
bits : 1 - 1 (1 bit)
access : read-write

SU : If 1, and SP is also set, XIP_QMI can be accessed from a Secure, Unprivileged context.
bits : 2 - 2 (1 bit)
access : read-write

SP : If 1, XIP_QMI can be accessed from a Secure, Privileged context.
bits : 3 - 3 (1 bit)
access : read-write

CORE0 : If 1, XIP_QMI can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register.
bits : 4 - 4 (1 bit)
access : read-write

CORE1 : If 1, XIP_QMI can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register.
bits : 5 - 5 (1 bit)
access : read-write

DMA : If 1, XIP_QMI can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register.
bits : 6 - 6 (1 bit)
access : read-write

DBG : If 1, XIP_QMI can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register.
bits : 7 - 7 (1 bit)
access : read-write

XIP_AUX

Control whether debugger, DMA, core 0 and core 1 can access XIP_AUX, and at what security/privilege levels they can do so. Defaults to Secure, Privileged access only. This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set.
address_offset : 0xE8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NSU : If 1, and NSP is also set, XIP_AUX can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set.
bits : 0 - 0 (1 bit)
access : read-write

NSP : If 1, XIP_AUX can be accessed from a Non-secure, Privileged context.
bits : 1 - 1 (1 bit)
access : read-write

SU : If 1, and SP is also set, XIP_AUX can be accessed from a Secure, Unprivileged context.
bits : 2 - 2 (1 bit)
access : read-write

SP : If 1, XIP_AUX can be accessed from a Secure, Privileged context.
bits : 3 - 3 (1 bit)
access : read-write

CORE0 : If 1, XIP_AUX can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register.
bits : 4 - 4 (1 bit)
access : read-write

CORE1 : If 1, XIP_AUX can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register.
bits : 5 - 5 (1 bit)
access : read-write

DMA : If 1, XIP_AUX can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register.
bits : 6 - 6 (1 bit)
access : read-write

DBG : If 1, XIP_AUX can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register.
bits : 7 - 7 (1 bit)
access : read-write

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