POWMAN

MODE : selects either normal (switching) mode or low power (linear) mode low power mode can only be selected for output voltages up to 1.3V 0 = normal mode (switching) 1 = low power mode (linear)
bits : 2 - 2 (1 bit)
access : read-write

VSEL : output voltage select the regulator output voltage is limited to 1.3V unless the voltage limit is disabled using the disable_voltage_limit field in the vreg_ctrl register 00000 - 0.55V 00001 - 0.60V 00010 - 0.65V 00011 - 0.70V 00100 - 0.75V 00101 - 0.80V 00110 - 0.85V 00111 - 0.90V 01000 - 0.95V 01001 - 1.00V 01010 - 1.05V 01011 - 1.10V (default) 01100 - 1.15V 01101 - 1.20V 01110 - 1.25V 01111 - 1.30V 10000 - 1.35V 10001 - 1.40V 10010 - 1.50V 10011 - 1.60V 10100 - 1.65V 10101 - 1.70V 10110 - 1.80V 10111 - 1.90V 11000 - 2.00V 11001 - 2.35V 11010 - 2.50V 11011 - 2.65V 11100 - 2.80V 11101 - 3.00V 11110 - 3.15V 11111 - 3.30V
bits : 4 - 8 (5 bit)
access : read-write

VREG_LP_EXIT

Voltage Regulator Low Power Exit Settings
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HIZ : high impedance mode select 0=not in high impedance mode, 1=in high impedance mode
bits : 1 - 1 (1 bit)
access : read-write

BOD_CTRL

Brown-out Detection Control
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ISOLATE : isolates the brown-out detection control interface 0 - not isolated (default) 1 - isolated
bits : 12 - 12 (1 bit)
access : read-write

BOD

Brown-out Detection Settings
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EN : enable brown-out detection 0=not enabled, 1=enabled
bits : 0 - 0 (1 bit)
access : read-write

VSEL : threshold select 00000 - 0.473V 00001 - 0.516V 00010 - 0.559V 00011 - 0.602V 00100 - 0.645VS 00101 - 0.688V 00110 - 0.731V 00111 - 0.774V 01000 - 0.817V 01001 - 0.860V (default) 01010 - 0.903V 01011 - 0.946V 01100 - 0.989V 01101 - 1.032V 01110 - 1.075V 01111 - 1.118V 10000 - 1.161 10001 - 1.204V
bits : 4 - 8 (5 bit)
access : read-write

BOD_LP_ENTRY

Brown-out Detection Low Power Entry Settings
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EN : enable brown-out detection 0=not enabled, 1=enabled
bits : 0 - 0 (1 bit)
access : read-write

BOD_LP_EXIT

Brown-out Detection Low Power Exit Settings
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EN : enable brown-out detection 0=not enabled, 1=enabled
bits : 0 - 0 (1 bit)
access : read-write

LPOSC

Low power oscillator control register.
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MODE : This feature has been removed
bits : 0 - 1 (2 bit)
access : read-write

TRIM : Frequency trim - the trim step is typically 1% of the reset frequency, but can be up to 3%
bits : 4 - 9 (6 bit)
access : read-write

CHIP_RESET

Chip reset control and status
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOUBLE_TAP : This flag is set by double-tapping RUN. It tells bootcode to go into the bootloader.
bits : 0 - 0 (1 bit)
access : read-write

RESCUE_FLAG : This is set by a rescue reset from the RP-AP. Its purpose is to halt before the bootrom before booting from flash in order to recover from a boot lock-up. The debugger can then attach once the bootrom has been halted and flash some working code that does not lock up.
bits : 4 - 4 (1 bit)
access : read-write

HAD_POR : Last reset was from the power-on reset This resets: double_tap flag yes DP yes RPAP yes rescue_flag yes timer yes powman yes swcore yes psm yes then starts the power sequencer
bits : 16 - 16 (1 bit)
access : read-only

HAD_BOR : Last reset was from the brown-out detection block This resets: double_tap flag yes DP yes RPAP yes rescue_flag yes timer yes powman yes swcore yes psm yes then starts the power sequencer
bits : 17 - 17 (1 bit)
access : read-only

HAD_RUN_LOW : Last reset was from the RUN pin This resets: double_tap flag no DP yes RPAP yes rescue_flag yes timer yes powman yes swcore yes psm yes then starts the power sequencer
bits : 18 - 18 (1 bit)
access : read-only

HAD_DP_RESET_REQ : Last reset was an reset request from the arm debugger This resets: double_tap flag no DP no RPAP no rescue_flag yes timer yes powman yes swcore yes psm yes then starts the power sequencer
bits : 19 - 19 (1 bit)
access : read-only

HAD_RESCUE : Last reset was a rescue reset from the debugger This resets: double_tap flag no DP no RPAP no rescue_flag no, it sets this flag timer yes powman yes swcore yes psm yes then starts the power sequencer
bits : 21 - 21 (1 bit)
access : read-only

HAD_WATCHDOG_RESET_POWMAN_ASYNC : Last reset was a watchdog timeout which was configured to reset the power manager asynchronously This resets: double_tap flag no DP no RPAP no rescue_flag no timer yes powman yes swcore yes psm yes then starts the power sequencer
bits : 22 - 22 (1 bit)
access : read-only

HAD_WATCHDOG_RESET_POWMAN : Last reset was a watchdog timeout which was configured to reset the power manager This resets: double_tap flag no DP no RPAP no rescue_flag no timer yes powman yes swcore yes psm yes then starts the power sequencer
bits : 23 - 23 (1 bit)
access : read-only

HAD_WATCHDOG_RESET_SWCORE : Last reset was a watchdog timeout which was configured to reset the switched-core This resets: double_tap flag no DP no RPAP no rescue_flag no timer no powman no swcore yes psm yes then starts the power sequencer
bits : 24 - 24 (1 bit)
access : read-only

HAD_SWCORE_PD : Last reset was a switched core powerdown This resets: double_tap flag no DP no RPAP no rescue_flag no timer no powman no swcore yes psm yes then starts the power sequencer
bits : 25 - 25 (1 bit)
access : read-only

HAD_GLITCH_DETECT : Last reset was due to a power supply glitch This resets: double_tap flag no DP no RPAP no rescue_flag no timer no powman no swcore no psm yes and does not change the power state
bits : 26 - 26 (1 bit)
access : read-only

HAD_HZD_SYS_RESET_REQ : Last reset was a system reset from the hazard debugger This resets: double_tap flag no DP no RPAP no rescue_flag no timer no powman no swcore no psm yes and does not change the power state
bits : 27 - 27 (1 bit)
access : read-only

HAD_WATCHDOG_RESET_RSM : Last reset was a watchdog timeout which was configured to reset the power-on state machine This resets: double_tap flag no DP no RPAP no rescue_flag no timer no powman no swcore no psm yes and does not change the power state
bits : 28 - 28 (1 bit)
access : read-only

WDSEL

Allows a watchdog reset to reset the internal state of powman in addition to the power-on state machine (PSM). Note that powman ignores watchdog resets that do not select at least the CLOCKS stage or earlier stages in the PSM. If using these bits, it's recommended to set PSM_WDSEL to all-ones in addition to the desired bits in this register. Failing to select CLOCKS or earlier will result in the POWMAN_WDSEL register having no effect.
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RESET_POWMAN_ASYNC : If set to 1, a watchdog reset will restore powman defaults, reset the timer, reset the switched core domain and run the full power-on state machine (PSM) sequence This does not rely on clk_ref running
bits : 0 - 0 (1 bit)
access : read-write

RESET_POWMAN : If set to 1, a watchdog reset will restore powman defaults, reset the timer, reset the switched core power domain and run the full power-on state machine (PSM) sequence This relies on clk_ref running. Use reset_powman_async if that may not be true
bits : 4 - 4 (1 bit)
access : read-write

RESET_SWCORE : If set to 1, a watchdog reset will reset the switched core power domain and run the full power-on state machine (PSM) sequence From a user perspective it is the same as setting RSM_WDSEL_PROC_COLD From a hardware debug perspective it has the same effect as a power-on reset for the switched core power domain
bits : 8 - 8 (1 bit)
access : read-write

RESET_RSM : If set to 1, a watchdog reset will run the full power-on state machine (PSM) sequence From a user perspective it is the same as setting RSM_WDSEL_PROC_COLD From a hardware debug perspective it has the same effect as a reset from a glitch detector
bits : 12 - 12 (1 bit)
access : read-write

SEQ_CFG

For configuration of the power sequencer Writes are ignored while POWMAN_STATE_CHANGING=1
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HW_PWRUP_SRAM1 : Specifies the power state of SRAM1 when powering up swcore from a low power state (P1.xxx) to a high power state (P0.0xx). 0=power-up 1=no change
bits : 0 - 0 (1 bit)
access : read-write

HW_PWRUP_SRAM0 : Specifies the power state of SRAM0 when powering up swcore from a low power state (P1.xxx) to a high power state (P0.0xx). 0=power-up 1=no change
bits : 1 - 1 (1 bit)
access : read-write

USE_VREG_LP : Set to 0 to prevent automatic switching to vreg low power mode when switched-core is powered down This setting takes effect when the swcore is next powered down
bits : 4 - 4 (1 bit)
access : read-write

USE_VREG_HP : Set to 0 to prevent automatic switching to vreg high power mode when switched-core is powered up This setting takes effect when the swcore is next powered up
bits : 5 - 5 (1 bit)
access : read-write

USE_BOD_LP : Set to 0 to prevent automatic switching to bod low power mode when switched-core is powered down This setting takes effect when the swcore is next powered down
bits : 6 - 6 (1 bit)
access : read-write

USE_BOD_HP : Set to 0 to prevent automatic switching to bod high power mode when switched-core is powered up This setting takes effect when the swcore is next powered up
bits : 7 - 7 (1 bit)
access : read-write

RUN_LPOSC_IN_LP : Set to 0 to stop the low power osc when the switched-core is powered down, which is unwise if using it to clock the timer This setting takes effect when the swcore is next powered down
bits : 8 - 8 (1 bit)
access : read-write

USE_FAST_POWCK : selects the reference clock (clk_ref) as the source of the POWMAN clock when switched-core is powered. The POWMAN clock always switches to the slow clock (lposc) when switched-core is powered down because the fast clock stops running. 0 always run the POWMAN clock from the slow clock (lposc) 1 run the POWMAN clock from the fast clock when available This setting takes effect when a power up sequence is next run
bits : 12 - 12 (1 bit)
access : read-write

USING_VREG_LP : Indicates the voltage regulator (VREG) mode 0 = VREG high power mode which is the default 1 = VREG low power mode
bits : 16 - 16 (1 bit)
access : read-only

USING_BOD_LP : Indicates the brown-out detector (BOD) mode 0 = BOD high power mode which is the default 1 = BOD low power mode
bits : 17 - 17 (1 bit)
access : read-only

USING_FAST_POWCK : 0 indicates the POWMAN clock is running from the low power oscillator (32kHz) 1 indicates the POWMAN clock is running from the reference clock (2-50MHz)
bits : 20 - 20 (1 bit)
access : read-only

STATE

This register controls the power state of the 4 power domains. The current power state is indicated in POWMAN_STATE_CURRENT which is read-only. To change the state, write to POWMAN_STATE_REQ. The coding of POWMAN_STATE_CURRENT & POWMAN_STATE_REQ corresponds to the power states defined in the datasheet: bit 3 = SWCORE bit 2 = XIP cache bit 1 = SRAM0 bit 0 = SRAM1 0 = powered up 1 = powered down When POWMAN_STATE_REQ is written, the POWMAN_STATE_WAITING flag is set while the Power Manager determines what is required. If an invalid transition is requested the Power Manager will still register the request in POWMAN_STATE_REQ but will also set the POWMAN_BAD_REQ flag. It will then implement the power-up requests and ignore the power down requests. To do nothing would risk entering an unrecoverable lock-up state. Invalid requests are: any combination of power up and power down requests any request that results in swcore boing powered and xip unpowered If the request is to power down the switched-core domain then POWMAN_STATE_WAITING stays active until the processors halt. During this time the POWMAN_STATE_REQ field can be re-written to change or cancel the request. When the power state transition begins the POWMAN_STATE_WAITING_flag is cleared, the POWMAN_STATE_CHANGING flag is set and POWMAN register writes are ignored until the transition completes.
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CURRENT :
bits : 0 - 3 (4 bit)
access : read-only

REQ :
bits : 4 - 7 (4 bit)
access : read-write

REQ_IGNORED :
bits : 8 - 8 (1 bit)
access : read-write

PWRUP_WHILE_WAITING : Request ignored because of a pending pwrup request. See current_pwrup_req. Note this blocks powering up AND powering down.
bits : 9 - 9 (1 bit)
access : read-write

BAD_SW_REQ : Bad software initiated state request. No action taken.
bits : 10 - 10 (1 bit)
access : read-only

BAD_HW_REQ : Bad hardware initiated state request. Went back to state 0 (i.e. everything powered up)
bits : 11 - 11 (1 bit)
access : read-only

WAITING :
bits : 12 - 12 (1 bit)
access : read-only

CHANGING :
bits : 13 - 13 (1 bit)
access : read-only

POW_FASTDIV

address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

POW_FASTDIV : divides the POWMAN clock to provide a tick for the delay module and state machines when clk_pow is running from the slow clock it is not divided when clk_pow is running from the fast clock it is divided by tick_div
bits : 0 - 10 (11 bit)
access : read-write

VREG_CTRL

Voltage Regulator Control
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HT_TH : high temperature protection threshold regulator power transistors are disabled when junction temperature exceeds threshold 000 - 100C 001 - 105C 010 - 110C 011 - 115C 100 - 120C 101 - 125C 110 - 135C 111 - 150C
bits : 4 - 6 (3 bit)
access : read-write

DISABLE_VOLTAGE_LIMIT : 0=not disabled, 1=enabled
bits : 8 - 8 (1 bit)
access : read-write

ISOLATE : isolates the VREG control interface 0 - not isolated (default) 1 - isolated
bits : 12 - 12 (1 bit)
access : read-write

UNLOCK : unlocks the VREG control interface after power up 0 - Locked (default) 1 - Unlocked It cannot be relocked when it is unlocked.
bits : 13 - 13 (1 bit)
access : read-write

RST_N : returns the regulator to its startup settings 0 - reset 1 - not reset (default)
bits : 15 - 15 (1 bit)
access : read-write

POW_DELAY

power state machine delays
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SWCORE_STEP : timing between the swcore power state machine steps measured in units of the lposc period, 0 gives a delay of 1 unit
bits : 0 - 3 (4 bit)
access : read-write

XIP_STEP : timing between the xip power state machine steps measured in units of the lposc period, 0 gives a delay of 1 unit
bits : 4 - 7 (4 bit)
access : read-write

SRAM_STEP : timing between the sram0 and sram1 power state machine steps measured in units of the powman tick period (>=1us), 0 gives a delay of 1 unit
bits : 8 - 15 (8 bit)
access : read-write

EXT_CTRL0

Configures a gpio as a power mode aware control output
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GPIO_SELECT : selects from gpio 0->30 set to 31 to disable this feature
bits : 0 - 5 (6 bit)
access : read-write

INIT :
bits : 8 - 8 (1 bit)
access : read-write

INIT_STATE :
bits : 12 - 12 (1 bit)
access : read-write

LP_ENTRY_STATE : output level when entering the low power state
bits : 13 - 13 (1 bit)
access : read-write

LP_EXIT_STATE : output level when exiting the low power state
bits : 14 - 14 (1 bit)
access : read-write

EXT_CTRL1

Configures a gpio as a power mode aware control output
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GPIO_SELECT : selects from gpio 0->30 set to 31 to disable this feature
bits : 0 - 5 (6 bit)
access : read-write

INIT :
bits : 8 - 8 (1 bit)
access : read-write

INIT_STATE :
bits : 12 - 12 (1 bit)
access : read-write

LP_ENTRY_STATE : output level when entering the low power state
bits : 13 - 13 (1 bit)
access : read-write

LP_EXIT_STATE : output level when exiting the low power state
bits : 14 - 14 (1 bit)
access : read-write

EXT_TIME_REF

Select a GPIO to use as a time reference, the source can be used to drive the low power clock at 32kHz, or to provide a 1ms tick to the timer, or provide a 1Hz tick to the timer. The tick selection is controlled by the POWMAN_TIMER register.
address_offset : 0x4C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SOURCE_SEL : 0 -> gpio12 1 -> gpio20 2 -> gpio14 3 -> gpio22
bits : 0 - 1 (2 bit)
access : read-write

DRIVE_LPCK : Use the selected GPIO to drive the 32kHz low power clock, in place of LPOSC. This field must only be written when POWMAN_TIMER_RUN=0
bits : 4 - 4 (1 bit)
access : read-write

LPOSC_FREQ_KHZ_INT

Informs the AON Timer of the integer component of the clock frequency when running off the LPOSC.
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

LPOSC_FREQ_KHZ_INT : Integer component of the LPOSC or GPIO clock source frequency in kHz. Default = 32 This field must only be written when POWMAN_TIMER_RUN=0 or POWMAN_TIMER_USING_XOSC=1
bits : 0 - 5 (6 bit)
access : read-write

LPOSC_FREQ_KHZ_FRAC

Informs the AON Timer of the fractional component of the clock frequency when running off the LPOSC.
address_offset : 0x54 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

LPOSC_FREQ_KHZ_FRAC : Fractional component of the LPOSC or GPIO clock source frequency in kHz. Default = 0.768 This field must only be written when POWMAN_TIMER_RUN=0 or POWMAN_TIMER_USING_XOSC=1
bits : 0 - 15 (16 bit)
access : read-write

XOSC_FREQ_KHZ_INT

Informs the AON Timer of the integer component of the clock frequency when running off the XOSC.
address_offset : 0x58 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

XOSC_FREQ_KHZ_INT : Integer component of the XOSC frequency in kHz. Default = 12000 Must be >1 This field must only be written when POWMAN_TIMER_RUN=0 or POWMAN_TIMER_USING_XOSC=0
bits : 0 - 15 (16 bit)
access : read-write

XOSC_FREQ_KHZ_FRAC

Informs the AON Timer of the fractional component of the clock frequency when running off the XOSC.
address_offset : 0x5C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

XOSC_FREQ_KHZ_FRAC : Fractional component of the XOSC frequency in kHz. This field must only be written when POWMAN_TIMER_RUN=0 or POWMAN_TIMER_USING_XOSC=0
bits : 0 - 15 (16 bit)
access : read-write

SET_TIME_63TO48

address_offset : 0x60 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SET_TIME_63TO48 : For setting the time, do not use for reading the time, use POWMAN_READ_TIME_UPPER and POWMAN_READ_TIME_LOWER. This field must only be written when POWMAN_TIMER_RUN=0
bits : 0 - 15 (16 bit)
access : read-write

SET_TIME_47TO32

address_offset : 0x64 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SET_TIME_47TO32 : For setting the time, do not use for reading the time, use POWMAN_READ_TIME_UPPER and POWMAN_READ_TIME_LOWER. This field must only be written when POWMAN_TIMER_RUN=0
bits : 0 - 15 (16 bit)
access : read-write

SET_TIME_31TO16

address_offset : 0x68 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SET_TIME_31TO16 : For setting the time, do not use for reading the time, use POWMAN_READ_TIME_UPPER and POWMAN_READ_TIME_LOWER. This field must only be written when POWMAN_TIMER_RUN=0
bits : 0 - 15 (16 bit)
access : read-write

SET_TIME_15TO0

address_offset : 0x6C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SET_TIME_15TO0 : For setting the time, do not use for reading the time, use POWMAN_READ_TIME_UPPER and POWMAN_READ_TIME_LOWER. This field must only be written when POWMAN_TIMER_RUN=0
bits : 0 - 15 (16 bit)
access : read-write

READ_TIME_UPPER

address_offset : 0x70 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

READ_TIME_UPPER : For reading bits 63:32 of the timer. When reading all 64 bits it is possible for the LOWER count to rollover during the read. It is recommended to read UPPER, then LOWER, then re-read UPPER and, if it has changed, re-read LOWER.
bits : 0 - 31 (32 bit)
access : read-only

READ_TIME_LOWER

address_offset : 0x74 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

READ_TIME_LOWER : For reading bits 31:0 of the timer.
bits : 0 - 31 (32 bit)
access : read-only

ALARM_TIME_63TO48

address_offset : 0x78 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ALARM_TIME_63TO48 : This field must only be written when POWMAN_ALARM_ENAB=0
bits : 0 - 15 (16 bit)
access : read-write

ALARM_TIME_47TO32

address_offset : 0x7C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ALARM_TIME_47TO32 : This field must only be written when POWMAN_ALARM_ENAB=0
bits : 0 - 15 (16 bit)
access : read-write

VREG_STS

Voltage Regulator Status
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

STARTUP : startup status 0=startup complete, 1=starting up
bits : 0 - 0 (1 bit)
access : read-only

VOUT_OK : output regulation status 0=not in regulation, 1=in regulation
bits : 4 - 4 (1 bit)
access : read-only

ALARM_TIME_31TO16

address_offset : 0x80 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ALARM_TIME_31TO16 : This field must only be written when POWMAN_ALARM_ENAB=0
bits : 0 - 15 (16 bit)
access : read-write

ALARM_TIME_15TO0

address_offset : 0x84 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ALARM_TIME_15TO0 : This field must only be written when POWMAN_ALARM_ENAB=0
bits : 0 - 15 (16 bit)
access : read-write

TIMER

address_offset : 0x88 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NONSEC_WRITE : Control whether Non-secure software can write to the timer registers. All other registers are hardwired to be inaccessible to Non-secure.
bits : 0 - 0 (1 bit)
access : read-write

RUN : Timer enable. Setting this bit causes the timer to begin counting up from its current value. Clearing this bit stops the timer from counting. Before enabling the timer, set the POWMAN_LPOSC_FREQ* and POWMAN_XOSC_FREQ* registers to configure the count rate, and initialise the current time by writing to SET_TIME_63TO48 through SET_TIME_15TO0. You must not write to the SET_TIME_x registers when the timer is running. Once configured, start the timer by setting POWMAN_TIMER_RUN=1. This will start the timer running from the LPOSC. When the XOSC is available switch the reference clock to XOSC then select it as the timer clock by setting POWMAN_TIMER_USE_XOSC=1
bits : 1 - 1 (1 bit)
access : read-write

CLEAR : Clears the timer, does not disable the timer and does not affect the alarm. This control can be written at any time.
bits : 2 - 2 (1 bit)
access : write-only

ALARM_ENAB : Enables the alarm. The alarm must be disabled while writing the alarm time.
bits : 4 - 4 (1 bit)
access : read-write

PWRUP_ON_ALARM : Alarm wakes the chip from low power mode
bits : 5 - 5 (1 bit)
access : read-write

ALARM : Alarm has fired. Write to 1 to clear the alarm.
bits : 6 - 6 (1 bit)
access : read-write

USE_LPOSC : Switch to lposc as the source of the 1kHz timer tick
bits : 8 - 8 (1 bit)
access : write-only

USE_XOSC : switch to xosc as the source of the 1kHz timer tick
bits : 9 - 9 (1 bit)
access : write-only

USE_GPIO_1KHZ : switch to gpio as the source of the 1kHz timer tick
bits : 10 - 10 (1 bit)
access : write-only

USE_GPIO_1HZ : Selects the gpio source as the reference for the sec counter. The msec counter will continue to use the lposc or xosc reference.
bits : 13 - 13 (1 bit)
access : read-write

USING_XOSC : Timer is running from xosc
bits : 16 - 16 (1 bit)
access : read-only

USING_LPOSC : Timer is running from lposc
bits : 17 - 17 (1 bit)
access : read-only

USING_GPIO_1KHZ : Timer is running from a 1khz gpio source
bits : 18 - 18 (1 bit)
access : read-only

USING_GPIO_1HZ : Timer is synchronised to a 1hz gpio source
bits : 19 - 19 (1 bit)
access : read-only

PWRUP0

4 GPIO powerup events can be configured to wake the chip up from a low power state. The pwrups are level/edge sensitive and can be set to trigger on a high/rising or low/falling event The number of gpios available depends on the package option. An invalid selection will be ignored source = 0 selects gpio0 . . source = 47 selects gpio47 source = 48 selects qspi_ss source = 49 selects qspi_sd0 source = 50 selects qspi_sd1 source = 51 selects qspi_sd2 source = 52 selects qspi_sd3 source = 53 selects qspi_sclk level = 0 triggers the pwrup when the source is low level = 1 triggers the pwrup when the source is high
address_offset : 0x8C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SOURCE :
bits : 0 - 5 (6 bit)
access : read-write

ENABLE : Set to 1 to enable the wakeup source. Set to 0 to disable the wakeup source and clear a pending wakeup event. If using edge detect a latched edge needs to be cleared by writing 1 to the status register also.
bits : 6 - 6 (1 bit)
access : read-write

DIRECTION :
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

0 : low_falling

1 : high_rising

End of enumeration elements list.

MODE : Edge or level detect. Edge will detect a 0 to 1 transition (or 1 to 0 transition). Level will detect a 1 or 0. Both types of event get latched into the current_pwrup_req register.
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

0 : level

1 : edge

End of enumeration elements list.

STATUS : Status of gpio wakeup. Write to 1 to clear a latched edge detect.
bits : 9 - 9 (1 bit)
access : read-write

RAW_STATUS : Value of selected gpio pin (only if enable == 1)
bits : 10 - 10 (1 bit)
access : read-only

PWRUP1

4 GPIO powerup events can be configured to wake the chip up from a low power state. The pwrups are level/edge sensitive and can be set to trigger on a high/rising or low/falling event The number of gpios available depends on the package option. An invalid selection will be ignored source = 0 selects gpio0 . . source = 47 selects gpio47 source = 48 selects qspi_ss source = 49 selects qspi_sd0 source = 50 selects qspi_sd1 source = 51 selects qspi_sd2 source = 52 selects qspi_sd3 source = 53 selects qspi_sclk level = 0 triggers the pwrup when the source is low level = 1 triggers the pwrup when the source is high
address_offset : 0x90 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SOURCE :
bits : 0 - 5 (6 bit)
access : read-write

DIRECTION :
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

0 : low_falling

1 : high_rising

End of enumeration elements list.

Enumeration:

0 : level

1 : edge

End of enumeration elements list.

STATUS : Status of gpio wakeup. Write to 1 to clear a latched edge detect.
bits : 9 - 9 (1 bit)
access : read-write

RAW_STATUS : Value of selected gpio pin (only if enable == 1)
bits : 10 - 10 (1 bit)
access : read-only

PWRUP2

4 GPIO powerup events can be configured to wake the chip up from a low power state. The pwrups are level/edge sensitive and can be set to trigger on a high/rising or low/falling event The number of gpios available depends on the package option. An invalid selection will be ignored source = 0 selects gpio0 . . source = 47 selects gpio47 source = 48 selects qspi_ss source = 49 selects qspi_sd0 source = 50 selects qspi_sd1 source = 51 selects qspi_sd2 source = 52 selects qspi_sd3 source = 53 selects qspi_sclk level = 0 triggers the pwrup when the source is low level = 1 triggers the pwrup when the source is high
address_offset : 0x94 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SOURCE :
bits : 0 - 5 (6 bit)
access : read-write

DIRECTION :
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

0 : low_falling

1 : high_rising

End of enumeration elements list.

Enumeration:

0 : level

1 : edge

End of enumeration elements list.

STATUS : Status of gpio wakeup. Write to 1 to clear a latched edge detect.
bits : 9 - 9 (1 bit)
access : read-write

RAW_STATUS : Value of selected gpio pin (only if enable == 1)
bits : 10 - 10 (1 bit)
access : read-only

PWRUP3

4 GPIO powerup events can be configured to wake the chip up from a low power state. The pwrups are level/edge sensitive and can be set to trigger on a high/rising or low/falling event The number of gpios available depends on the package option. An invalid selection will be ignored source = 0 selects gpio0 . . source = 47 selects gpio47 source = 48 selects qspi_ss source = 49 selects qspi_sd0 source = 50 selects qspi_sd1 source = 51 selects qspi_sd2 source = 52 selects qspi_sd3 source = 53 selects qspi_sclk level = 0 triggers the pwrup when the source is low level = 1 triggers the pwrup when the source is high
address_offset : 0x98 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SOURCE :
bits : 0 - 5 (6 bit)
access : read-write

DIRECTION :
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

0 : low_falling

1 : high_rising

End of enumeration elements list.

Enumeration:

0 : level

1 : edge

End of enumeration elements list.

STATUS : Status of gpio wakeup. Write to 1 to clear a latched edge detect.
bits : 9 - 9 (1 bit)
access : read-write

RAW_STATUS : Value of selected gpio pin (only if enable == 1)
bits : 10 - 10 (1 bit)
access : read-only

CURRENT_PWRUP_REQ

Indicates current powerup request state pwrup events can be cleared by removing the enable from the pwrup register. The alarm pwrup req can be cleared by clearing timer.alarm_enab 0 = chip reset, for the source of the last reset see POWMAN_CHIP_RESET 1 = pwrup0 2 = pwrup1 3 = pwrup2 4 = pwrup3 5 = coresight_pwrup 6 = alarm_pwrup
address_offset : 0x9C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CURRENT_PWRUP_REQ :
bits : 0 - 6 (7 bit)
access : read-only

LAST_SWCORE_PWRUP

Indicates which pwrup source triggered the last switched-core power up 0 = chip reset, for the source of the last reset see POWMAN_CHIP_RESET 1 = pwrup0 2 = pwrup1 3 = pwrup2 4 = pwrup3 5 = coresight_pwrup 6 = alarm_pwrup
address_offset : 0xA0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

LAST_SWCORE_PWRUP :
bits : 0 - 6 (7 bit)
access : read-only

DBG_PWRCFG

address_offset : 0xA4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IGNORE : Ignore pwrup req from debugger. If pwrup req is asserted then this will prevent power down and set powerdown blocked. Set ignore to stop paying attention to pwrup_req
bits : 0 - 0 (1 bit)
access : read-write

BOOTDIS

Tell the bootrom to ignore the BOOT0..3 registers following the next RSM reset (e.g. the next core power down/up). If an early boot stage has soft-locked some OTP pages in order to protect their contents from later stages, there is a risk that Secure code running at a later stage can unlock the pages by powering the core up and down. This register can be used to ensure that the bootloader runs as normal on the next power up, preventing Secure code at a later stage from accessing OTP in its unlocked state. Should be used in conjunction with the OTP BOOTDIS register.
address_offset : 0xA8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NOW : When powman resets the RSM, the current value of BOOTDIS_NEXT is OR'd into BOOTDIS_NOW, and BOOTDIS_NEXT is cleared. The bootrom checks this flag before reading the BOOT0..3 registers. If it is set, the bootrom clears it, and ignores the BOOT registers. This prevents Secure software from diverting the boot path before a bootloader has had the chance to soft lock OTP pages containing sensitive data.
bits : 0 - 0 (1 bit)
access : read-write

NEXT : This flag always ORs writes into its current contents. It can be set but not cleared by software. The BOOTDIS_NEXT bit is OR'd into the BOOTDIS_NOW bit when the core is powered down. Simultaneously, the BOOTDIS_NEXT bit is cleared. Setting this bit means that the BOOT0..3 registers will be ignored following the next reset of the RSM by powman. This flag should be set by an early boot stage that has soft-locked OTP pages, to prevent later stages from unlocking it by power cycling.
bits : 1 - 1 (1 bit)
access : read-write

DBGCONFIG

address_offset : 0xAC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DP_INSTID : Configure DP instance ID for SWD multidrop selection. Recommend that this is NOT changed until you require debug access in multi-chip environment
bits : 0 - 3 (4 bit)
access : read-write

SCRATCH0

Scratch register. Information persists in low power mode
address_offset : 0xB0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SCRATCH0 :
bits : 0 - 31 (32 bit)
access : read-write

SCRATCH1

Scratch register. Information persists in low power mode
address_offset : 0xB4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SCRATCH1 :
bits : 0 - 31 (32 bit)
access : read-write

SCRATCH2

Scratch register. Information persists in low power mode
address_offset : 0xB8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SCRATCH2 :
bits : 0 - 31 (32 bit)
access : read-write

SCRATCH3

Scratch register. Information persists in low power mode
address_offset : 0xBC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SCRATCH3 :
bits : 0 - 31 (32 bit)
access : read-write

VREG

Voltage Regulator Settings
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HIZ : high impedance mode select 0=not in high impedance mode, 1=in high impedance mode
bits : 1 - 1 (1 bit)
access : read-write

UPDATE_IN_PROGRESS : regulator state is being updated writes to the vreg register will be ignored when this field is set
bits : 15 - 15 (1 bit)
access : read-only

SCRATCH4

Scratch register. Information persists in low power mode
address_offset : 0xC0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SCRATCH4 :
bits : 0 - 31 (32 bit)
access : read-write

SCRATCH5

Scratch register. Information persists in low power mode
address_offset : 0xC4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SCRATCH5 :
bits : 0 - 31 (32 bit)
access : read-write

SCRATCH6

Scratch register. Information persists in low power mode
address_offset : 0xC8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SCRATCH6 :
bits : 0 - 31 (32 bit)
access : read-write

SCRATCH7

Scratch register. Information persists in low power mode
address_offset : 0xCC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SCRATCH7 :
bits : 0 - 31 (32 bit)
access : read-write

BOOT0

Scratch register. Information persists in low power mode
address_offset : 0xD0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BOOT0 :
bits : 0 - 31 (32 bit)
access : read-write

BOOT1

Scratch register. Information persists in low power mode
address_offset : 0xD4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BOOT1 :
bits : 0 - 31 (32 bit)
access : read-write

BOOT2

Scratch register. Information persists in low power mode
address_offset : 0xD8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BOOT2 :
bits : 0 - 31 (32 bit)
access : read-write

BOOT3

Scratch register. Information persists in low power mode
address_offset : 0xDC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BOOT3 :
bits : 0 - 31 (32 bit)
access : read-write

INTR

Raw Interrupts
address_offset : 0xE0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VREG_OUTPUT_LOW :
bits : 0 - 0 (1 bit)
access : read-write

TIMER :
bits : 1 - 1 (1 bit)
access : read-only

STATE_REQ_IGNORED : Source is state.req_ignored
bits : 2 - 2 (1 bit)
access : read-only

PWRUP_WHILE_WAITING : Source is state.pwrup_while_waiting
bits : 3 - 3 (1 bit)
access : read-only

INTE

Interrupt Enable
address_offset : 0xE4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VREG_OUTPUT_LOW :
bits : 0 - 0 (1 bit)
access : read-write

TIMER :
bits : 1 - 1 (1 bit)
access : read-write

STATE_REQ_IGNORED : Source is state.req_ignored
bits : 2 - 2 (1 bit)
access : read-write

PWRUP_WHILE_WAITING : Source is state.pwrup_while_waiting
bits : 3 - 3 (1 bit)
access : read-write

INTF

Interrupt Force
address_offset : 0xE8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VREG_OUTPUT_LOW :
bits : 0 - 0 (1 bit)
access : read-write

TIMER :
bits : 1 - 1 (1 bit)
access : read-write

STATE_REQ_IGNORED : Source is state.req_ignored
bits : 2 - 2 (1 bit)
access : read-write

PWRUP_WHILE_WAITING : Source is state.pwrup_while_waiting
bits : 3 - 3 (1 bit)
access : read-write

INTS

Interrupt status after masking & forcing
address_offset : 0xEC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VREG_OUTPUT_LOW :
bits : 0 - 0 (1 bit)
access : read-only

TIMER :
bits : 1 - 1 (1 bit)
access : read-only

STATE_REQ_IGNORED : Source is state.req_ignored
bits : 2 - 2 (1 bit)
access : read-only

PWRUP_WHILE_WAITING : Source is state.pwrup_while_waiting
bits : 3 - 3 (1 bit)
access : read-only

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ChipSelect

POWMAN

Peripheral Memory Blocks

Registers

BADPASSWD

VREG_LP_ENTRY

VREG_LP_EXIT

BOD_CTRL

BOD

BOD_LP_ENTRY

BOD_LP_EXIT

LPOSC

CHIP_RESET

WDSEL

SEQ_CFG

STATE

POW_FASTDIV

VREG_CTRL

POW_DELAY

EXT_CTRL0

EXT_CTRL1

EXT_TIME_REF

LPOSC_FREQ_KHZ_INT

LPOSC_FREQ_KHZ_FRAC

XOSC_FREQ_KHZ_INT

XOSC_FREQ_KHZ_FRAC

SET_TIME_63TO48

SET_TIME_47TO32

SET_TIME_31TO16

SET_TIME_15TO0

READ_TIME_UPPER

READ_TIME_LOWER

ALARM_TIME_63TO48

ALARM_TIME_47TO32

VREG_STS

ALARM_TIME_31TO16

ALARM_TIME_15TO0

TIMER

PWRUP0

PWRUP1

PWRUP2

PWRUP3

CURRENT_PWRUP_REQ

LAST_SWCORE_PWRUP

DBG_PWRCFG

BOOTDIS

DBGCONFIG

SCRATCH0

SCRATCH1

SCRATCH2

SCRATCH3

VREG

SCRATCH4

SCRATCH5

SCRATCH6

SCRATCH7

BOOT0

BOOT1

BOOT2

BOOT3

INTR

INTE

INTF

INTS