Embeetle, an IDE designed from scratch for embedded software developers.address_offset : 0x0 Bytes (0x0)
size : 0xBC8 byte (0x0)
mem_usage : registers
protection :
DMA Channel 0 Read Address pointer
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH0_READ_ADDR : This register updates automatically each time a read completes. The current value is the next address to be read by this channel.
bits : 0 - 31 (32 bit)
access : read-write
Alias for channel 0 CTRL register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH0_AL1_CTRL :
bits : 0 - 31 (32 bit)
access : read-write
DMA Channel 4 Read Address pointer
address_offset : 0x100 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH4_READ_ADDR : This register updates automatically each time a read completes. The current value is the next address to be read by this channel.
bits : 0 - 31 (32 bit)
access : read-write
DMA Channel 4 Write Address pointer
address_offset : 0x104 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH4_WRITE_ADDR : This register updates automatically each time a write completes. The current value is the next address to be written by this channel.
bits : 0 - 31 (32 bit)
access : read-write
DMA Channel 4 Transfer Count
address_offset : 0x108 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
COUNT : 28-bit transfer count (256 million transfers maximum).
Program the number of bus transfers a channel will perform before halting. Note that, if transfers are larger than one byte in size, this is not equal to the number of bytes transferred (see CTRL_DATA_SIZE).
When the channel is active, reading this register shows the number of transfers remaining, updating automatically each time a write transfer completes.
Writing this register sets the RELOAD value for the transfer counter. Each time this channel is triggered, the RELOAD value is copied into the live transfer counter. The channel can be started multiple times, and will perform the same number of transfers each time, as programmed by most recent write.
The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a trigger, the written value is used immediately as the length of the new transfer sequence, as well as being written to RELOAD.
bits : 0 - 27 (28 bit)
access : read-write
MODE : When MODE is 0x0, the transfer count decrements with each transfer until 0, and then the channel triggers the next channel indicated by CTRL_CHAIN_TO.
When MODE is 0x1, the transfer count decrements with each transfer until 0, and then the channel re-triggers itself, in addition to the trigger indicated by CTRL_CHAIN_TO. This is useful for e.g. an endless ring-buffer DMA with periodic interrupts.
When MODE is 0xf, the transfer count does not decrement. The DMA channel performs an endless sequence of transfers, never triggering other channels or raising interrupts, until an ABORT is raised.
All other values are reserved.
bits : 28 - 31 (4 bit)
access : read-write
Enumeration:
0 : NORMAL
1 : TRIGGER_SELF
15 : ENDLESS
End of enumeration elements list.
DMA Channel 4 Control and Status
address_offset : 0x10C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : DMA Channel Enable.
When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high)
bits : 0 - 0 (1 bit)
access : read-write
HIGH_PRIORITY : HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels.
This only affects the order in which the DMA schedules channels. The DMA's bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput.
bits : 1 - 1 (1 bit)
access : read-write
DATA_SIZE : Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer.
bits : 2 - 3 (2 bit)
access : read-write
Enumeration:
0 : SIZE_BYTE
1 : SIZE_HALFWORD
2 : SIZE_WORD
End of enumeration elements list.
INCR_READ : If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address.
Generally this should be disabled for peripheral-to-memory transfers.
bits : 4 - 4 (1 bit)
access : read-write
INCR_READ_REV : If 1, and INCR_READ is 1, the read address is decremented rather than incremented with each transfer.
If 1, and INCR_READ is 0, this otherwise-unused combination causes the read address to be incremented by twice the transfer size, i.e. skipping over alternate addresses.
bits : 5 - 5 (1 bit)
access : read-write
INCR_WRITE : If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address.
Generally this should be disabled for memory-to-peripheral transfers.
bits : 6 - 6 (1 bit)
access : read-write
INCR_WRITE_REV : If 1, and INCR_WRITE is 1, the write address is decremented rather than incremented with each transfer.
If 1, and INCR_WRITE is 0, this otherwise-unused combination causes the write address to be incremented by twice the transfer size, i.e. skipping over alternate addresses.
bits : 7 - 7 (1 bit)
access : read-write
RING_SIZE : Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned ring buffers.
Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL.
bits : 8 - 11 (4 bit)
access : read-write
Enumeration:
0 : RING_NONE
End of enumeration elements list.
RING_SEL : Select whether RING_SIZE applies to read or write addresses.
If 0, read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, write addresses are wrapped.
bits : 12 - 12 (1 bit)
access : read-write
CHAIN_TO : When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_.
Note this field resets to 0, so channels 1 and above will chain to channel 0 by default. Set this field to avoid this behaviour.
bits : 13 - 16 (4 bit)
access : read-write
TREQ_SEL : Select a Transfer Request signal.
The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system).
0x0 to 0x3a -> select DREQ n as TREQ
bits : 17 - 22 (6 bit)
access : read-write
Enumeration:
0 : PIO0_TX0
Select PIO0's TX FIFO 0 as TREQ
1 : PIO0_TX1
Select PIO0's TX FIFO 1 as TREQ
2 : PIO0_TX2
Select PIO0's TX FIFO 2 as TREQ
3 : PIO0_TX3
Select PIO0's TX FIFO 3 as TREQ
4 : PIO0_RX0
Select PIO0's RX FIFO 0 as TREQ
5 : PIO0_RX1
Select PIO0's RX FIFO 1 as TREQ
6 : PIO0_RX2
Select PIO0's RX FIFO 2 as TREQ
7 : PIO0_RX3
Select PIO0's RX FIFO 3 as TREQ
8 : PIO1_TX0
Select PIO1's TX FIFO 0 as TREQ
9 : PIO1_TX1
Select PIO1's TX FIFO 1 as TREQ
10 : PIO1_TX2
Select PIO1's TX FIFO 2 as TREQ
11 : PIO1_TX3
Select PIO1's TX FIFO 3 as TREQ
12 : PIO1_RX0
Select PIO1's RX FIFO 0 as TREQ
13 : PIO1_RX1
Select PIO1's RX FIFO 1 as TREQ
14 : PIO1_RX2
Select PIO1's RX FIFO 2 as TREQ
15 : PIO1_RX3
Select PIO1's RX FIFO 3 as TREQ
16 : PIO2_TX0
Select PIO2's TX FIFO 0 as TREQ
17 : PIO2_TX1
Select PIO2's TX FIFO 1 as TREQ
18 : PIO2_TX2
Select PIO2's TX FIFO 2 as TREQ
19 : PIO2_TX3
Select PIO2's TX FIFO 3 as TREQ
20 : PIO2_RX0
Select PIO2's RX FIFO 0 as TREQ
21 : PIO2_RX1
Select PIO2's RX FIFO 1 as TREQ
22 : PIO2_RX2
Select PIO2's RX FIFO 2 as TREQ
23 : PIO2_RX3
Select PIO2's RX FIFO 3 as TREQ
24 : SPI0_TX
Select SPI0's TX FIFO as TREQ
25 : SPI0_RX
Select SPI0's RX FIFO as TREQ
26 : SPI1_TX
Select SPI1's TX FIFO as TREQ
27 : SPI1_RX
Select SPI1's RX FIFO as TREQ
28 : UART0_TX
Select UART0's TX FIFO as TREQ
29 : UART0_RX
Select UART0's RX FIFO as TREQ
30 : UART1_TX
Select UART1's TX FIFO as TREQ
31 : UART1_RX
Select UART1's RX FIFO as TREQ
32 : PWM_WRAP0
Select PWM Counter 0's Wrap Value as TREQ
33 : PWM_WRAP1
Select PWM Counter 1's Wrap Value as TREQ
34 : PWM_WRAP2
Select PWM Counter 2's Wrap Value as TREQ
35 : PWM_WRAP3
Select PWM Counter 3's Wrap Value as TREQ
36 : PWM_WRAP4
Select PWM Counter 4's Wrap Value as TREQ
37 : PWM_WRAP5
Select PWM Counter 5's Wrap Value as TREQ
38 : PWM_WRAP6
Select PWM Counter 6's Wrap Value as TREQ
39 : PWM_WRAP7
Select PWM Counter 7's Wrap Value as TREQ
40 : PWM_WRAP8
Select PWM Counter 8's Wrap Value as TREQ
41 : PWM_WRAP9
Select PWM Counter 9's Wrap Value as TREQ
42 : PWM_WRAP10
Select PWM Counter 0's Wrap Value as TREQ
43 : PWM_WRAP11
Select PWM Counter 1's Wrap Value as TREQ
44 : I2C0_TX
Select I2C0's TX FIFO as TREQ
45 : I2C0_RX
Select I2C0's RX FIFO as TREQ
46 : I2C1_TX
Select I2C1's TX FIFO as TREQ
47 : I2C1_RX
Select I2C1's RX FIFO as TREQ
48 : ADC
Select the ADC as TREQ
49 : XIP_STREAM
Select the XIP Streaming FIFO as TREQ
50 : XIP_QMITX
Select XIP_QMITX as TREQ
51 : XIP_QMIRX
Select XIP_QMIRX as TREQ
52 : HSTX
Select HSTX as TREQ
53 : CORESIGHT
Select CORESIGHT as TREQ
54 : SHA256
Select SHA256 as TREQ
59 : TIMER0
Select Timer 0 as TREQ
60 : TIMER1
Select Timer 1 as TREQ
61 : TIMER2
Select Timer 2 as TREQ (Optional)
62 : TIMER3
Select Timer 3 as TREQ (Optional)
63 : PERMANENT
Permanent request, for unpaced transfers.
End of enumeration elements list.
IRQ_QUIET : In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain.
This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks.
bits : 23 - 23 (1 bit)
access : read-write
BSWAP : Apply byte-swap transformation to DMA data.
For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order.
bits : 24 - 24 (1 bit)
access : read-write
SNIFF_EN : If 1, this channel's data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected.
This allows checksum to be enabled or disabled on a per-control- block basis.
bits : 25 - 25 (1 bit)
access : read-write
BUSY : This flag goes high when the channel starts a new transfer sequence, and low when the last transfer of that sequence completes. Clearing EN while BUSY is high pauses the channel, and BUSY will stay high while paused.
To terminate a sequence early (and clear the BUSY flag), see CHAN_ABORT.
bits : 26 - 26 (1 bit)
access : read-only
WRITE_ERROR : If 1, the channel received a write bus error. Write one to clear.
WRITE_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 5 transfers later)
bits : 29 - 29 (1 bit)
access : read-write
READ_ERROR : If 1, the channel received a read bus error. Write one to clear.
READ_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 3 transfers later)
bits : 30 - 30 (1 bit)
access : read-write
AHB_ERROR : Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel halts when it encounters any bus error, and always raises its channel IRQ flag.
bits : 31 - 31 (1 bit)
access : read-only
Alias for channel 4 CTRL register
address_offset : 0x110 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH4_AL1_CTRL :
bits : 0 - 31 (32 bit)
access : read-write
Alias for channel 4 READ_ADDR register
address_offset : 0x114 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH4_AL1_READ_ADDR :
bits : 0 - 31 (32 bit)
access : read-write
Alias for channel 4 WRITE_ADDR register
address_offset : 0x118 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH4_AL1_WRITE_ADDR :
bits : 0 - 31 (32 bit)
access : read-write
Alias for channel 4 TRANS_COUNT register
This is a trigger register (0xc). Writing a nonzero value will
reload the channel counter and start the channel.
address_offset : 0x11C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH4_AL1_TRANS_COUNT_TRIG :
bits : 0 - 31 (32 bit)
access : read-write
Alias for channel 4 CTRL register
address_offset : 0x120 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH4_AL2_CTRL :
bits : 0 - 31 (32 bit)
access : read-write
Alias for channel 4 TRANS_COUNT register
address_offset : 0x124 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH4_AL2_TRANS_COUNT :
bits : 0 - 31 (32 bit)
access : read-write
Alias for channel 4 READ_ADDR register
address_offset : 0x128 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH4_AL2_READ_ADDR :
bits : 0 - 31 (32 bit)
access : read-write
Alias for channel 4 WRITE_ADDR register
This is a trigger register (0xc). Writing a nonzero value will
reload the channel counter and start the channel.
address_offset : 0x12C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH4_AL2_WRITE_ADDR_TRIG :
bits : 0 - 31 (32 bit)
access : read-write
Alias for channel 4 CTRL register
address_offset : 0x130 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH4_AL3_CTRL :
bits : 0 - 31 (32 bit)
access : read-write
Alias for channel 4 WRITE_ADDR register
address_offset : 0x134 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH4_AL3_WRITE_ADDR :
bits : 0 - 31 (32 bit)
access : read-write
Alias for channel 4 TRANS_COUNT register
address_offset : 0x138 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH4_AL3_TRANS_COUNT :
bits : 0 - 31 (32 bit)
access : read-write
Alias for channel 4 READ_ADDR register
This is a trigger register (0xc). Writing a nonzero value will
reload the channel counter and start the channel.
address_offset : 0x13C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH4_AL3_READ_ADDR_TRIG :
bits : 0 - 31 (32 bit)
access : read-write
Alias for channel 0 READ_ADDR register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH0_AL1_READ_ADDR :
bits : 0 - 31 (32 bit)
access : read-write
DMA Channel 5 Read Address pointer
address_offset : 0x140 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH5_READ_ADDR : This register updates automatically each time a read completes. The current value is the next address to be read by this channel.
bits : 0 - 31 (32 bit)
access : read-write
DMA Channel 5 Write Address pointer
address_offset : 0x144 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH5_WRITE_ADDR : This register updates automatically each time a write completes. The current value is the next address to be written by this channel.
bits : 0 - 31 (32 bit)
access : read-write
DMA Channel 5 Transfer Count
address_offset : 0x148 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
COUNT : 28-bit transfer count (256 million transfers maximum).
Program the number of bus transfers a channel will perform before halting. Note that, if transfers are larger than one byte in size, this is not equal to the number of bytes transferred (see CTRL_DATA_SIZE).
When the channel is active, reading this register shows the number of transfers remaining, updating automatically each time a write transfer completes.
Writing this register sets the RELOAD value for the transfer counter. Each time this channel is triggered, the RELOAD value is copied into the live transfer counter. The channel can be started multiple times, and will perform the same number of transfers each time, as programmed by most recent write.
The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a trigger, the written value is used immediately as the length of the new transfer sequence, as well as being written to RELOAD.
bits : 0 - 27 (28 bit)
access : read-write
MODE : When MODE is 0x0, the transfer count decrements with each transfer until 0, and then the channel triggers the next channel indicated by CTRL_CHAIN_TO.
When MODE is 0x1, the transfer count decrements with each transfer until 0, and then the channel re-triggers itself, in addition to the trigger indicated by CTRL_CHAIN_TO. This is useful for e.g. an endless ring-buffer DMA with periodic interrupts.
When MODE is 0xf, the transfer count does not decrement. The DMA channel performs an endless sequence of transfers, never triggering other channels or raising interrupts, until an ABORT is raised.
All other values are reserved.
bits : 28 - 31 (4 bit)
access : read-write
Enumeration:
0 : NORMAL
1 : TRIGGER_SELF
15 : ENDLESS
End of enumeration elements list.
DMA Channel 5 Control and Status
address_offset : 0x14C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : DMA Channel Enable.
When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high)
bits : 0 - 0 (1 bit)
access : read-write
HIGH_PRIORITY : HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels.
This only affects the order in which the DMA schedules channels. The DMA's bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput.
bits : 1 - 1 (1 bit)
access : read-write
DATA_SIZE : Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer.
bits : 2 - 3 (2 bit)
access : read-write
Enumeration:
0 : SIZE_BYTE
1 : SIZE_HALFWORD
2 : SIZE_WORD
End of enumeration elements list.
INCR_READ : If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address.
Generally this should be disabled for peripheral-to-memory transfers.
bits : 4 - 4 (1 bit)
access : read-write
INCR_READ_REV : If 1, and INCR_READ is 1, the read address is decremented rather than incremented with each transfer.
If 1, and INCR_READ is 0, this otherwise-unused combination causes the read address to be incremented by twice the transfer size, i.e. skipping over alternate addresses.
bits : 5 - 5 (1 bit)
access : read-write
INCR_WRITE : If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address.
Generally this should be disabled for memory-to-peripheral transfers.
bits : 6 - 6 (1 bit)
access : read-write
INCR_WRITE_REV : If 1, and INCR_WRITE is 1, the write address is decremented rather than incremented with each transfer.
If 1, and INCR_WRITE is 0, this otherwise-unused combination causes the write address to be incremented by twice the transfer size, i.e. skipping over alternate addresses.
bits : 7 - 7 (1 bit)
access : read-write
RING_SIZE : Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned ring buffers.
Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL.
bits : 8 - 11 (4 bit)
access : read-write
Enumeration:
0 : RING_NONE
End of enumeration elements list.
RING_SEL : Select whether RING_SIZE applies to read or write addresses.
If 0, read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, write addresses are wrapped.
bits : 12 - 12 (1 bit)
access : read-write
CHAIN_TO : When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_.
Note this field resets to 0, so channels 1 and above will chain to channel 0 by default. Set this field to avoid this behaviour.
bits : 13 - 16 (4 bit)
access : read-write
TREQ_SEL : Select a Transfer Request signal.
The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system).
0x0 to 0x3a -> select DREQ n as TREQ
bits : 17 - 22 (6 bit)
access : read-write
Enumeration:
0 : PIO0_TX0
Select PIO0's TX FIFO 0 as TREQ
1 : PIO0_TX1
Select PIO0's TX FIFO 1 as TREQ
2 : PIO0_TX2
Select PIO0's TX FIFO 2 as TREQ
3 : PIO0_TX3
Select PIO0's TX FIFO 3 as TREQ
4 : PIO0_RX0
Select PIO0's RX FIFO 0 as TREQ
5 : PIO0_RX1
Select PIO0's RX FIFO 1 as TREQ
6 : PIO0_RX2
Select PIO0's RX FIFO 2 as TREQ
7 : PIO0_RX3
Select PIO0's RX FIFO 3 as TREQ
8 : PIO1_TX0
Select PIO1's TX FIFO 0 as TREQ
9 : PIO1_TX1
Select PIO1's TX FIFO 1 as TREQ
10 : PIO1_TX2
Select PIO1's TX FIFO 2 as TREQ
11 : PIO1_TX3
Select PIO1's TX FIFO 3 as TREQ
12 : PIO1_RX0
Select PIO1's RX FIFO 0 as TREQ
13 : PIO1_RX1
Select PIO1's RX FIFO 1 as TREQ
14 : PIO1_RX2
Select PIO1's RX FIFO 2 as TREQ
15 : PIO1_RX3
Select PIO1's RX FIFO 3 as TREQ
16 : PIO2_TX0
Select PIO2's TX FIFO 0 as TREQ
17 : PIO2_TX1
Select PIO2's TX FIFO 1 as TREQ
18 : PIO2_TX2
Select PIO2's TX FIFO 2 as TREQ
19 : PIO2_TX3
Select PIO2's TX FIFO 3 as TREQ
20 : PIO2_RX0
Select PIO2's RX FIFO 0 as TREQ
21 : PIO2_RX1
Select PIO2's RX FIFO 1 as TREQ
22 : PIO2_RX2
Select PIO2's RX FIFO 2 as TREQ
23 : PIO2_RX3
Select PIO2's RX FIFO 3 as TREQ
24 : SPI0_TX
Select SPI0's TX FIFO as TREQ
25 : SPI0_RX
Select SPI0's RX FIFO as TREQ
26 : SPI1_TX
Select SPI1's TX FIFO as TREQ
27 : SPI1_RX
Select SPI1's RX FIFO as TREQ
28 : UART0_TX
Select UART0's TX FIFO as TREQ
29 : UART0_RX
Select UART0's RX FIFO as TREQ
30 : UART1_TX
Select UART1's TX FIFO as TREQ
31 : UART1_RX
Select UART1's RX FIFO as TREQ
32 : PWM_WRAP0
Select PWM Counter 0's Wrap Value as TREQ
33 : PWM_WRAP1
Select PWM Counter 1's Wrap Value as TREQ
34 : PWM_WRAP2
Select PWM Counter 2's Wrap Value as TREQ
35 : PWM_WRAP3
Select PWM Counter 3's Wrap Value as TREQ
36 : PWM_WRAP4
Select PWM Counter 4's Wrap Value as TREQ
37 : PWM_WRAP5
Select PWM Counter 5's Wrap Value as TREQ
38 : PWM_WRAP6
Select PWM Counter 6's Wrap Value as TREQ
39 : PWM_WRAP7
Select PWM Counter 7's Wrap Value as TREQ
40 : PWM_WRAP8
Select PWM Counter 8's Wrap Value as TREQ
41 : PWM_WRAP9
Select PWM Counter 9's Wrap Value as TREQ
42 : PWM_WRAP10
Select PWM Counter 0's Wrap Value as TREQ
43 : PWM_WRAP11
Select PWM Counter 1's Wrap Value as TREQ
44 : I2C0_TX
Select I2C0's TX FIFO as TREQ
45 : I2C0_RX
Select I2C0's RX FIFO as TREQ
46 : I2C1_TX
Select I2C1's TX FIFO as TREQ
47 : I2C1_RX
Select I2C1's RX FIFO as TREQ
48 : ADC
Select the ADC as TREQ
49 : XIP_STREAM
Select the XIP Streaming FIFO as TREQ
50 : XIP_QMITX
Select XIP_QMITX as TREQ
51 : XIP_QMIRX
Select XIP_QMIRX as TREQ
52 : HSTX
Select HSTX as TREQ
53 : CORESIGHT
Select CORESIGHT as TREQ
54 : SHA256
Select SHA256 as TREQ
59 : TIMER0
Select Timer 0 as TREQ
60 : TIMER1
Select Timer 1 as TREQ
61 : TIMER2
Select Timer 2 as TREQ (Optional)
62 : TIMER3
Select Timer 3 as TREQ (Optional)
63 : PERMANENT
Permanent request, for unpaced transfers.
End of enumeration elements list.
IRQ_QUIET : In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain.
This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks.
bits : 23 - 23 (1 bit)
access : read-write
BSWAP : Apply byte-swap transformation to DMA data.
For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order.
bits : 24 - 24 (1 bit)
access : read-write
SNIFF_EN : If 1, this channel's data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected.
This allows checksum to be enabled or disabled on a per-control- block basis.
bits : 25 - 25 (1 bit)
access : read-write
BUSY : This flag goes high when the channel starts a new transfer sequence, and low when the last transfer of that sequence completes. Clearing EN while BUSY is high pauses the channel, and BUSY will stay high while paused.
To terminate a sequence early (and clear the BUSY flag), see CHAN_ABORT.
bits : 26 - 26 (1 bit)
access : read-only
WRITE_ERROR : If 1, the channel received a write bus error. Write one to clear.
WRITE_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 5 transfers later)
bits : 29 - 29 (1 bit)
access : read-write
READ_ERROR : If 1, the channel received a read bus error. Write one to clear.
READ_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 3 transfers later)
bits : 30 - 30 (1 bit)
access : read-write
AHB_ERROR : Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel halts when it encounters any bus error, and always raises its channel IRQ flag.
bits : 31 - 31 (1 bit)
access : read-only
Alias for channel 5 CTRL register
address_offset : 0x150 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH5_AL1_CTRL :
bits : 0 - 31 (32 bit)
access : read-write
Alias for channel 5 READ_ADDR register
address_offset : 0x154 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH5_AL1_READ_ADDR :
bits : 0 - 31 (32 bit)
access : read-write
Alias for channel 5 WRITE_ADDR register
address_offset : 0x158 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH5_AL1_WRITE_ADDR :
bits : 0 - 31 (32 bit)
access : read-write
Alias for channel 5 TRANS_COUNT register
This is a trigger register (0xc). Writing a nonzero value will
reload the channel counter and start the channel.
address_offset : 0x15C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH5_AL1_TRANS_COUNT_TRIG :
bits : 0 - 31 (32 bit)
access : read-write
Alias for channel 5 CTRL register
address_offset : 0x160 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH5_AL2_CTRL :
bits : 0 - 31 (32 bit)
access : read-write
Alias for channel 5 TRANS_COUNT register
address_offset : 0x164 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH5_AL2_TRANS_COUNT :
bits : 0 - 31 (32 bit)
access : read-write
Alias for channel 5 READ_ADDR register
address_offset : 0x168 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH5_AL2_READ_ADDR :
bits : 0 - 31 (32 bit)
access : read-write
Alias for channel 5 WRITE_ADDR register
This is a trigger register (0xc). Writing a nonzero value will
reload the channel counter and start the channel.
address_offset : 0x16C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH5_AL2_WRITE_ADDR_TRIG :
bits : 0 - 31 (32 bit)
access : read-write
Alias for channel 5 CTRL register
address_offset : 0x170 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH5_AL3_CTRL :
bits : 0 - 31 (32 bit)
access : read-write
Alias for channel 5 WRITE_ADDR register
address_offset : 0x174 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH5_AL3_WRITE_ADDR :
bits : 0 - 31 (32 bit)
access : read-write
Alias for channel 5 TRANS_COUNT register
address_offset : 0x178 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH5_AL3_TRANS_COUNT :
bits : 0 - 31 (32 bit)
access : read-write
Alias for channel 5 READ_ADDR register
This is a trigger register (0xc). Writing a nonzero value will
reload the channel counter and start the channel.
address_offset : 0x17C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH5_AL3_READ_ADDR_TRIG :
bits : 0 - 31 (32 bit)
access : read-write
Alias for channel 0 WRITE_ADDR register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH0_AL1_WRITE_ADDR :
bits : 0 - 31 (32 bit)
access : read-write
DMA Channel 6 Read Address pointer
address_offset : 0x180 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH6_READ_ADDR : This register updates automatically each time a read completes. The current value is the next address to be read by this channel.
bits : 0 - 31 (32 bit)
access : read-write
DMA Channel 6 Write Address pointer
address_offset : 0x184 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH6_WRITE_ADDR : This register updates automatically each time a write completes. The current value is the next address to be written by this channel.
bits : 0 - 31 (32 bit)
access : read-write
DMA Channel 6 Transfer Count
address_offset : 0x188 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
COUNT : 28-bit transfer count (256 million transfers maximum).
Program the number of bus transfers a channel will perform before halting. Note that, if transfers are larger than one byte in size, this is not equal to the number of bytes transferred (see CTRL_DATA_SIZE).
When the channel is active, reading this register shows the number of transfers remaining, updating automatically each time a write transfer completes.
Writing this register sets the RELOAD value for the transfer counter. Each time this channel is triggered, the RELOAD value is copied into the live transfer counter. The channel can be started multiple times, and will perform the same number of transfers each time, as programmed by most recent write.
The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a trigger, the written value is used immediately as the length of the new transfer sequence, as well as being written to RELOAD.
bits : 0 - 27 (28 bit)
access : read-write
MODE : When MODE is 0x0, the transfer count decrements with each transfer until 0, and then the channel triggers the next channel indicated by CTRL_CHAIN_TO.
When MODE is 0x1, the transfer count decrements with each transfer until 0, and then the channel re-triggers itself, in addition to the trigger indicated by CTRL_CHAIN_TO. This is useful for e.g. an endless ring-buffer DMA with periodic interrupts.
When MODE is 0xf, the transfer count does not decrement. The DMA channel performs an endless sequence of transfers, never triggering other channels or raising interrupts, until an ABORT is raised.
All other values are reserved.
bits : 28 - 31 (4 bit)
access : read-write
Enumeration:
0 : NORMAL
1 : TRIGGER_SELF
15 : ENDLESS
End of enumeration elements list.
DMA Channel 6 Control and Status
address_offset : 0x18C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : DMA Channel Enable.
When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high)
bits : 0 - 0 (1 bit)
access : read-write
HIGH_PRIORITY : HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels.
This only affects the order in which the DMA schedules channels. The DMA's bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput.
bits : 1 - 1 (1 bit)
access : read-write
DATA_SIZE : Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer.
bits : 2 - 3 (2 bit)
access : read-write
Enumeration:
0 : SIZE_BYTE
1 : SIZE_HALFWORD
2 : SIZE_WORD
End of enumeration elements list.
INCR_READ : If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address.
Generally this should be disabled for peripheral-to-memory transfers.
bits : 4 - 4 (1 bit)
access : read-write
INCR_READ_REV : If 1, and INCR_READ is 1, the read address is decremented rather than incremented with each transfer.
If 1, and INCR_READ is 0, this otherwise-unused combination causes the read address to be incremented by twice the transfer size, i.e. skipping over alternate addresses.
bits : 5 - 5 (1 bit)
access : read-write
INCR_WRITE : If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address.
Generally this should be disabled for memory-to-peripheral transfers.
bits : 6 - 6 (1 bit)
access : read-write
INCR_WRITE_REV : If 1, and INCR_WRITE is 1, the write address is decremented rather than incremented with each transfer.
If 1, and INCR_WRITE is 0, this otherwise-unused combination causes the write address to be incremented by twice the transfer size, i.e. skipping over alternate addresses.
bits : 7 - 7 (1 bit)
access : read-write
RING_SIZE : Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned ring buffers.
Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL.
bits : 8 - 11 (4 bit)
access : read-write
Enumeration:
0 : RING_NONE
End of enumeration elements list.
RING_SEL : Select whether RING_SIZE applies to read or write addresses.
If 0, read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, write addresses are wrapped.
bits : 12 - 12 (1 bit)
access : read-write
CHAIN_TO : When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_.
Note this field resets to 0, so channels 1 and above will chain to channel 0 by default. Set this field to avoid this behaviour.
bits : 13 - 16 (4 bit)
access : read-write
TREQ_SEL : Select a Transfer Request signal.
The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system).
0x0 to 0x3a -> select DREQ n as TREQ
bits : 17 - 22 (6 bit)
access : read-write
Enumeration:
0 : PIO0_TX0
Select PIO0's TX FIFO 0 as TREQ
1 : PIO0_TX1
Select PIO0's TX FIFO 1 as TREQ
2 : PIO0_TX2
Select PIO0's TX FIFO 2 as TREQ
3 : PIO0_TX3
Select PIO0's TX FIFO 3 as TREQ
4 : PIO0_RX0
Select PIO0's RX FIFO 0 as TREQ
5 : PIO0_RX1
Select PIO0's RX FIFO 1 as TREQ
6 : PIO0_RX2
Select PIO0's RX FIFO 2 as TREQ
7 : PIO0_RX3
Select PIO0's RX FIFO 3 as TREQ
8 : PIO1_TX0
Select PIO1's TX FIFO 0 as TREQ
9 : PIO1_TX1
Select PIO1's TX FIFO 1 as TREQ
10 : PIO1_TX2
Select PIO1's TX FIFO 2 as TREQ
11 : PIO1_TX3
Select PIO1's TX FIFO 3 as TREQ
12 : PIO1_RX0
Select PIO1's RX FIFO 0 as TREQ
13 : PIO1_RX1
Select PIO1's RX FIFO 1 as TREQ
14 : PIO1_RX2
Select PIO1's RX FIFO 2 as TREQ
15 : PIO1_RX3
Select PIO1's RX FIFO 3 as TREQ
16 : PIO2_TX0
Select PIO2's TX FIFO 0 as TREQ
17 : PIO2_TX1
Select PIO2's TX FIFO 1 as TREQ
18 : PIO2_TX2
Select PIO2's TX FIFO 2 as TREQ
19 : PIO2_TX3
Select PIO2's TX FIFO 3 as TREQ
20 : PIO2_RX0
Select PIO2's RX FIFO 0 as TREQ
21 : PIO2_RX1
Select PIO2's RX FIFO 1 as TREQ
22 : PIO2_RX2
Select PIO2's RX FIFO 2 as TREQ
23 : PIO2_RX3
Select PIO2's RX FIFO 3 as TREQ
24 : SPI0_TX
Select SPI0's TX FIFO as TREQ
25 : SPI0_RX
Select SPI0's RX FIFO as TREQ
26 : SPI1_TX
Select SPI1's TX FIFO as TREQ
27 : SPI1_RX
Select SPI1's RX FIFO as TREQ
28 : UART0_TX
Select UART0's TX FIFO as TREQ
29 : UART0_RX
Select UART0's RX FIFO as TREQ
30 : UART1_TX
Select UART1's TX FIFO as TREQ
31 : UART1_RX
Select UART1's RX FIFO as TREQ
32 : PWM_WRAP0
Select PWM Counter 0's Wrap Value as TREQ
33 : PWM_WRAP1
Select PWM Counter 1's Wrap Value as TREQ
34 : PWM_WRAP2
Select PWM Counter 2's Wrap Value as TREQ
35 : PWM_WRAP3
Select PWM Counter 3's Wrap Value as TREQ
36 : PWM_WRAP4
Select PWM Counter 4's Wrap Value as TREQ
37 : PWM_WRAP5
Select PWM Counter 5's Wrap Value as TREQ
38 : PWM_WRAP6
Select PWM Counter 6's Wrap Value as TREQ
39 : PWM_WRAP7
Select PWM Counter 7's Wrap Value as TREQ
40 : PWM_WRAP8
Select PWM Counter 8's Wrap Value as TREQ
41 : PWM_WRAP9
Select PWM Counter 9's Wrap Value as TREQ
42 : PWM_WRAP10
Select PWM Counter 0's Wrap Value as TREQ
43 : PWM_WRAP11
Select PWM Counter 1's Wrap Value as TREQ
44 : I2C0_TX
Select I2C0's TX FIFO as TREQ
45 : I2C0_RX
Select I2C0's RX FIFO as TREQ
46 : I2C1_TX
Select I2C1's TX FIFO as TREQ
47 : I2C1_RX
Select I2C1's RX FIFO as TREQ
48 : ADC
Select the ADC as TREQ
49 : XIP_STREAM
Select the XIP Streaming FIFO as TREQ
50 : XIP_QMITX
Select XIP_QMITX as TREQ
51 : XIP_QMIRX
Select XIP_QMIRX as TREQ
52 : HSTX
Select HSTX as TREQ
53 : CORESIGHT
Select CORESIGHT as TREQ
54 : SHA256
Select SHA256 as TREQ
59 : TIMER0
Select Timer 0 as TREQ
60 : TIMER1
Select Timer 1 as TREQ
61 : TIMER2
Select Timer 2 as TREQ (Optional)
62 : TIMER3
Select Timer 3 as TREQ (Optional)
63 : PERMANENT
Permanent request, for unpaced transfers.
End of enumeration elements list.
IRQ_QUIET : In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain.
This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks.
bits : 23 - 23 (1 bit)
access : read-write
BSWAP : Apply byte-swap transformation to DMA data.
For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order.
bits : 24 - 24 (1 bit)
access : read-write
SNIFF_EN : If 1, this channel's data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected.
This allows checksum to be enabled or disabled on a per-control- block basis.
bits : 25 - 25 (1 bit)
access : read-write
BUSY : This flag goes high when the channel starts a new transfer sequence, and low when the last transfer of that sequence completes. Clearing EN while BUSY is high pauses the channel, and BUSY will stay high while paused.
To terminate a sequence early (and clear the BUSY flag), see CHAN_ABORT.
bits : 26 - 26 (1 bit)
access : read-only
WRITE_ERROR : If 1, the channel received a write bus error. Write one to clear.
WRITE_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 5 transfers later)
bits : 29 - 29 (1 bit)
access : read-write
READ_ERROR : If 1, the channel received a read bus error. Write one to clear.
READ_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 3 transfers later)
bits : 30 - 30 (1 bit)
access : read-write
AHB_ERROR : Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel halts when it encounters any bus error, and always raises its channel IRQ flag.
bits : 31 - 31 (1 bit)
access : read-only
Alias for channel 6 CTRL register
address_offset : 0x190 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH6_AL1_CTRL :
bits : 0 - 31 (32 bit)
access : read-write
Alias for channel 6 READ_ADDR register
address_offset : 0x194 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH6_AL1_READ_ADDR :
bits : 0 - 31 (32 bit)
access : read-write
Alias for channel 6 WRITE_ADDR register
address_offset : 0x198 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH6_AL1_WRITE_ADDR :
bits : 0 - 31 (32 bit)
access : read-write
Alias for channel 6 TRANS_COUNT register
This is a trigger register (0xc). Writing a nonzero value will
reload the channel counter and start the channel.
address_offset : 0x19C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH6_AL1_TRANS_COUNT_TRIG :
bits : 0 - 31 (32 bit)
access : read-write
Alias for channel 6 CTRL register
address_offset : 0x1A0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH6_AL2_CTRL :
bits : 0 - 31 (32 bit)
access : read-write
Alias for channel 6 TRANS_COUNT register
address_offset : 0x1A4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH6_AL2_TRANS_COUNT :
bits : 0 - 31 (32 bit)
access : read-write
Alias for channel 6 READ_ADDR register
address_offset : 0x1A8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH6_AL2_READ_ADDR :
bits : 0 - 31 (32 bit)
access : read-write
Alias for channel 6 WRITE_ADDR register
This is a trigger register (0xc). Writing a nonzero value will
reload the channel counter and start the channel.
address_offset : 0x1AC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH6_AL2_WRITE_ADDR_TRIG :
bits : 0 - 31 (32 bit)
access : read-write
Alias for channel 6 CTRL register
address_offset : 0x1B0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH6_AL3_CTRL :
bits : 0 - 31 (32 bit)
access : read-write
Alias for channel 6 WRITE_ADDR register
address_offset : 0x1B4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH6_AL3_WRITE_ADDR :
bits : 0 - 31 (32 bit)
access : read-write
Alias for channel 6 TRANS_COUNT register
address_offset : 0x1B8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH6_AL3_TRANS_COUNT :
bits : 0 - 31 (32 bit)
access : read-write
Alias for channel 6 READ_ADDR register
This is a trigger register (0xc). Writing a nonzero value will
reload the channel counter and start the channel.
address_offset : 0x1BC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH6_AL3_READ_ADDR_TRIG :
bits : 0 - 31 (32 bit)
access : read-write
Alias for channel 0 TRANS_COUNT register
This is a trigger register (0xc). Writing a nonzero value will
reload the channel counter and start the channel.
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH0_AL1_TRANS_COUNT_TRIG :
bits : 0 - 31 (32 bit)
access : read-write
DMA Channel 7 Read Address pointer
address_offset : 0x1C0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH7_READ_ADDR : This register updates automatically each time a read completes. The current value is the next address to be read by this channel.
bits : 0 - 31 (32 bit)
access : read-write
DMA Channel 7 Write Address pointer
address_offset : 0x1C4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH7_WRITE_ADDR : This register updates automatically each time a write completes. The current value is the next address to be written by this channel.
bits : 0 - 31 (32 bit)
access : read-write
DMA Channel 7 Transfer Count
address_offset : 0x1C8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
COUNT : 28-bit transfer count (256 million transfers maximum).
Program the number of bus transfers a channel will perform before halting. Note that, if transfers are larger than one byte in size, this is not equal to the number of bytes transferred (see CTRL_DATA_SIZE).
When the channel is active, reading this register shows the number of transfers remaining, updating automatically each time a write transfer completes.
Writing this register sets the RELOAD value for the transfer counter. Each time this channel is triggered, the RELOAD value is copied into the live transfer counter. The channel can be started multiple times, and will perform the same number of transfers each time, as programmed by most recent write.
The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a trigger, the written value is used immediately as the length of the new transfer sequence, as well as being written to RELOAD.
bits : 0 - 27 (28 bit)
access : read-write
MODE : When MODE is 0x0, the transfer count decrements with each transfer until 0, and then the channel triggers the next channel indicated by CTRL_CHAIN_TO.
When MODE is 0x1, the transfer count decrements with each transfer until 0, and then the channel re-triggers itself, in addition to the trigger indicated by CTRL_CHAIN_TO. This is useful for e.g. an endless ring-buffer DMA with periodic interrupts.
When MODE is 0xf, the transfer count does not decrement. The DMA channel performs an endless sequence of transfers, never triggering other channels or raising interrupts, until an ABORT is raised.
All other values are reserved.
bits : 28 - 31 (4 bit)
access : read-write
Enumeration:
0 : NORMAL
1 : TRIGGER_SELF
15 : ENDLESS
End of enumeration elements list.
DMA Channel 7 Control and Status
address_offset : 0x1CC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : DMA Channel Enable.
When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high)
bits : 0 - 0 (1 bit)
access : read-write
HIGH_PRIORITY : HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels.
This only affects the order in which the DMA schedules channels. The DMA's bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput.
bits : 1 - 1 (1 bit)
access : read-write
DATA_SIZE : Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer.
bits : 2 - 3 (2 bit)
access : read-write
Enumeration:
0 : SIZE_BYTE
1 : SIZE_HALFWORD
2 : SIZE_WORD
End of enumeration elements list.
INCR_READ : If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address.
Generally this should be disabled for peripheral-to-memory transfers.
bits : 4 - 4 (1 bit)
access : read-write
INCR_READ_REV : If 1, and INCR_READ is 1, the read address is decremented rather than incremented with each transfer.
If 1, and INCR_READ is 0, this otherwise-unused combination causes the read address to be incremented by twice the transfer size, i.e. skipping over alternate addresses.
bits : 5 - 5 (1 bit)
access : read-write
INCR_WRITE : If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address.
Generally this should be disabled for memory-to-peripheral transfers.
bits : 6 - 6 (1 bit)
access : read-write
INCR_WRITE_REV : If 1, and INCR_WRITE is 1, the write address is decremented rather than incremented with each transfer.
If 1, and INCR_WRITE is 0, this otherwise-unused combination causes the write address to be incremented by twice the transfer size, i.e. skipping over alternate addresses.
bits : 7 - 7 (1 bit)
access : read-write
RING_SIZE : Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned ring buffers.
Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL.
bits : 8 - 11 (4 bit)
access : read-write
Enumeration:
0 : RING_NONE
End of enumeration elements list.
RING_SEL : Select whether RING_SIZE applies to read or write addresses.
If 0, read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, write addresses are wrapped.
bits : 12 - 12 (1 bit)
access : read-write
CHAIN_TO : When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_.
Note this field resets to 0, so channels 1 and above will chain to channel 0 by default. Set this field to avoid this behaviour.
bits : 13 - 16 (4 bit)
access : read-write
TREQ_SEL : Select a Transfer Request signal.
The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system).
0x0 to 0x3a -> select DREQ n as TREQ
bits : 17 - 22 (6 bit)
access : read-write
Enumeration:
0 : PIO0_TX0
Select PIO0's TX FIFO 0 as TREQ
1 : PIO0_TX1
Select PIO0's TX FIFO 1 as TREQ
2 : PIO0_TX2
Select PIO0's TX FIFO 2 as TREQ
3 : PIO0_TX3
Select PIO0's TX FIFO 3 as TREQ
4 : PIO0_RX0
Select PIO0's RX FIFO 0 as TREQ
5 : PIO0_RX1
Select PIO0's RX FIFO 1 as TREQ
6 : PIO0_RX2
Select PIO0's RX FIFO 2 as TREQ
7 : PIO0_RX3
Select PIO0's RX FIFO 3 as TREQ
8 : PIO1_TX0
Select PIO1's TX FIFO 0 as TREQ
9 : PIO1_TX1
Select PIO1's TX FIFO 1 as TREQ
10 : PIO1_TX2
Select PIO1's TX FIFO 2 as TREQ
11 : PIO1_TX3
Select PIO1's TX FIFO 3 as TREQ
12 : PIO1_RX0
Select PIO1's RX FIFO 0 as TREQ
13 : PIO1_RX1
Select PIO1's RX FIFO 1 as TREQ
14 : PIO1_RX2
Select PIO1's RX FIFO 2 as TREQ
15 : PIO1_RX3
Select PIO1's RX FIFO 3 as TREQ
16 : PIO2_TX0
Select PIO2's TX FIFO 0 as TREQ
17 : PIO2_TX1
Select PIO2's TX FIFO 1 as TREQ
18 : PIO2_TX2
Select PIO2's TX FIFO 2 as TREQ
19 : PIO2_TX3
Select PIO2's TX FIFO 3 as TREQ
20 : PIO2_RX0
Select PIO2's RX FIFO 0 as TREQ
21 : PIO2_RX1
Select PIO2's RX FIFO 1 as TREQ
22 : PIO2_RX2
Select PIO2's RX FIFO 2 as TREQ
23 : PIO2_RX3
Select PIO2's RX FIFO 3 as TREQ
24 : SPI0_TX
Select SPI0's TX FIFO as TREQ
25 : SPI0_RX
Select SPI0's RX FIFO as TREQ
26 : SPI1_TX
Select SPI1's TX FIFO as TREQ
27 : SPI1_RX
Select SPI1's RX FIFO as TREQ
28 : UART0_TX
Select UART0's TX FIFO as TREQ
29 : UART0_RX
Select UART0's RX FIFO as TREQ
30 : UART1_TX
Select UART1's TX FIFO as TREQ
31 : UART1_RX
Select UART1's RX FIFO as TREQ
32 : PWM_WRAP0
Select PWM Counter 0's Wrap Value as TREQ
33 : PWM_WRAP1
Select PWM Counter 1's Wrap Value as TREQ
34 : PWM_WRAP2
Select PWM Counter 2's Wrap Value as TREQ
35 : PWM_WRAP3
Select PWM Counter 3's Wrap Value as TREQ
36 : PWM_WRAP4
Select PWM Counter 4's Wrap Value as TREQ
37 : PWM_WRAP5
Select PWM Counter 5's Wrap Value as TREQ
38 : PWM_WRAP6
Select PWM Counter 6's Wrap Value as TREQ
39 : PWM_WRAP7
Select PWM Counter 7's Wrap Value as TREQ
40 : PWM_WRAP8
Select PWM Counter 8's Wrap Value as TREQ
41 : PWM_WRAP9
Select PWM Counter 9's Wrap Value as TREQ
42 : PWM_WRAP10
Select PWM Counter 0's Wrap Value as TREQ
43 : PWM_WRAP11
Select PWM Counter 1's Wrap Value as TREQ
44 : I2C0_TX
Select I2C0's TX FIFO as TREQ
45 : I2C0_RX
Select I2C0's RX FIFO as TREQ
46 : I2C1_TX
Select I2C1's TX FIFO as TREQ
47 : I2C1_RX
Select I2C1's RX FIFO as TREQ
48 : ADC
Select the ADC as TREQ
49 : XIP_STREAM
Select the XIP Streaming FIFO as TREQ
50 : XIP_QMITX
Select XIP_QMITX as TREQ
51 : XIP_QMIRX
Select XIP_QMIRX as TREQ
52 : HSTX
Select HSTX as TREQ
53 : CORESIGHT
Select CORESIGHT as TREQ
54 : SHA256
Select SHA256 as TREQ
59 : TIMER0
Select Timer 0 as TREQ
60 : TIMER1
Select Timer 1 as TREQ
61 : TIMER2
Select Timer 2 as TREQ (Optional)
62 : TIMER3
Select Timer 3 as TREQ (Optional)
63 : PERMANENT
Permanent request, for unpaced transfers.
End of enumeration elements list.
IRQ_QUIET : In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain.
This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks.
bits : 23 - 23 (1 bit)
access : read-write
BSWAP : Apply byte-swap transformation to DMA data.
For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order.
bits : 24 - 24 (1 bit)
access : read-write
SNIFF_EN : If 1, this channel's data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected.
This allows checksum to be enabled or disabled on a per-control- block basis.
bits : 25 - 25 (1 bit)
access : read-write
BUSY : This flag goes high when the channel starts a new transfer sequence, and low when the last transfer of that sequence completes. Clearing EN while BUSY is high pauses the channel, and BUSY will stay high while paused.
To terminate a sequence early (and clear the BUSY flag), see CHAN_ABORT.
bits : 26 - 26 (1 bit)
access : read-only
WRITE_ERROR : If 1, the channel received a write bus error. Write one to clear.
WRITE_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 5 transfers later)
bits : 29 - 29 (1 bit)
access : read-write
READ_ERROR : If 1, the channel received a read bus error. Write one to clear.
READ_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 3 transfers later)
bits : 30 - 30 (1 bit)
access : read-write
AHB_ERROR : Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel halts when it encounters any bus error, and always raises its channel IRQ flag.
bits : 31 - 31 (1 bit)
access : read-only
Alias for channel 7 CTRL register
address_offset : 0x1D0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH7_AL1_CTRL :
bits : 0 - 31 (32 bit)
access : read-write
Alias for channel 7 READ_ADDR register
address_offset : 0x1D4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH7_AL1_READ_ADDR :
bits : 0 - 31 (32 bit)
access : read-write
Alias for channel 7 WRITE_ADDR register
address_offset : 0x1D8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH7_AL1_WRITE_ADDR :
bits : 0 - 31 (32 bit)
access : read-write
Alias for channel 7 TRANS_COUNT register
This is a trigger register (0xc). Writing a nonzero value will
reload the channel counter and start the channel.
address_offset : 0x1DC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH7_AL1_TRANS_COUNT_TRIG :
bits : 0 - 31 (32 bit)
access : read-write
Alias for channel 7 CTRL register
address_offset : 0x1E0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH7_AL2_CTRL :
bits : 0 - 31 (32 bit)
access : read-write
Alias for channel 7 TRANS_COUNT register
address_offset : 0x1E4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH7_AL2_TRANS_COUNT :
bits : 0 - 31 (32 bit)
access : read-write
Alias for channel 7 READ_ADDR register
address_offset : 0x1E8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH7_AL2_READ_ADDR :
bits : 0 - 31 (32 bit)
access : read-write
Alias for channel 7 WRITE_ADDR register
This is a trigger register (0xc). Writing a nonzero value will
reload the channel counter and start the channel.
address_offset : 0x1EC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH7_AL2_WRITE_ADDR_TRIG :
bits : 0 - 31 (32 bit)
access : read-write
Alias for channel 7 CTRL register
address_offset : 0x1F0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH7_AL3_CTRL :
bits : 0 - 31 (32 bit)
access : read-write
Alias for channel 7 WRITE_ADDR register
address_offset : 0x1F4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH7_AL3_WRITE_ADDR :
bits : 0 - 31 (32 bit)
access : read-write
Alias for channel 7 TRANS_COUNT register
address_offset : 0x1F8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH7_AL3_TRANS_COUNT :
bits : 0 - 31 (32 bit)
access : read-write
Alias for channel 7 READ_ADDR register
This is a trigger register (0xc). Writing a nonzero value will
reload the channel counter and start the channel.
address_offset : 0x1FC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH7_AL3_READ_ADDR_TRIG :
bits : 0 - 31 (32 bit)
access : read-write
Alias for channel 0 CTRL register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH0_AL2_CTRL :
bits : 0 - 31 (32 bit)
access : read-write
DMA Channel 8 Read Address pointer
address_offset : 0x200 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH8_READ_ADDR : This register updates automatically each time a read completes. The current value is the next address to be read by this channel.
bits : 0 - 31 (32 bit)
access : read-write
DMA Channel 8 Write Address pointer
address_offset : 0x204 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH8_WRITE_ADDR : This register updates automatically each time a write completes. The current value is the next address to be written by this channel.
bits : 0 - 31 (32 bit)
access : read-write
DMA Channel 8 Transfer Count
address_offset : 0x208 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
COUNT : 28-bit transfer count (256 million transfers maximum).
Program the number of bus transfers a channel will perform before halting. Note that, if transfers are larger than one byte in size, this is not equal to the number of bytes transferred (see CTRL_DATA_SIZE).
When the channel is active, reading this register shows the number of transfers remaining, updating automatically each time a write transfer completes.
Writing this register sets the RELOAD value for the transfer counter. Each time this channel is triggered, the RELOAD value is copied into the live transfer counter. The channel can be started multiple times, and will perform the same number of transfers each time, as programmed by most recent write.
The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a trigger, the written value is used immediately as the length of the new transfer sequence, as well as being written to RELOAD.
bits : 0 - 27 (28 bit)
access : read-write
MODE : When MODE is 0x0, the transfer count decrements with each transfer until 0, and then the channel triggers the next channel indicated by CTRL_CHAIN_TO.
When MODE is 0x1, the transfer count decrements with each transfer until 0, and then the channel re-triggers itself, in addition to the trigger indicated by CTRL_CHAIN_TO. This is useful for e.g. an endless ring-buffer DMA with periodic interrupts.
When MODE is 0xf, the transfer count does not decrement. The DMA channel performs an endless sequence of transfers, never triggering other channels or raising interrupts, until an ABORT is raised.
All other values are reserved.
bits : 28 - 31 (4 bit)
access : read-write
Enumeration:
0 : NORMAL
1 : TRIGGER_SELF
15 : ENDLESS
End of enumeration elements list.
DMA Channel 8 Control and Status
address_offset : 0x20C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : DMA Channel Enable.
When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high)
bits : 0 - 0 (1 bit)
access : read-write
HIGH_PRIORITY : HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels.
This only affects the order in which the DMA schedules channels. The DMA's bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput.
bits : 1 - 1 (1 bit)
access : read-write
DATA_SIZE : Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer.
bits : 2 - 3 (2 bit)
access : read-write
Enumeration:
0 : SIZE_BYTE
1 : SIZE_HALFWORD
2 : SIZE_WORD
End of enumeration elements list.
INCR_READ : If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address.
Generally this should be disabled for peripheral-to-memory transfers.
bits : 4 - 4 (1 bit)
access : read-write
INCR_READ_REV : If 1, and INCR_READ is 1, the read address is decremented rather than incremented with each transfer.
If 1, and INCR_READ is 0, this otherwise-unused combination causes the read address to be incremented by twice the transfer size, i.e. skipping over alternate addresses.
bits : 5 - 5 (1 bit)
access : read-write
INCR_WRITE : If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address.
Generally this should be disabled for memory-to-peripheral transfers.
bits : 6 - 6 (1 bit)
access : read-write
INCR_WRITE_REV : If 1, and INCR_WRITE is 1, the write address is decremented rather than incremented with each transfer.
If 1, and INCR_WRITE is 0, this otherwise-unused combination causes the write address to be incremented by twice the transfer size, i.e. skipping over alternate addresses.
bits : 7 - 7 (1 bit)
access : read-write
RING_SIZE : Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned ring buffers.
Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL.
bits : 8 - 11 (4 bit)
access : read-write
Enumeration:
0 : RING_NONE
End of enumeration elements list.
RING_SEL : Select whether RING_SIZE applies to read or write addresses.
If 0, read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, write addresses are wrapped.
bits : 12 - 12 (1 bit)
access : read-write
CHAIN_TO : When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_.
Note this field resets to 0, so channels 1 and above will chain to channel 0 by default. Set this field to avoid this behaviour.
bits : 13 - 16 (4 bit)
access : read-write
TREQ_SEL : Select a Transfer Request signal.
The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system).
0x0 to 0x3a -> select DREQ n as TREQ
bits : 17 - 22 (6 bit)
access : read-write
Enumeration:
0 : PIO0_TX0
Select PIO0's TX FIFO 0 as TREQ
1 : PIO0_TX1
Select PIO0's TX FIFO 1 as TREQ
2 : PIO0_TX2
Select PIO0's TX FIFO 2 as TREQ
3 : PIO0_TX3
Select PIO0's TX FIFO 3 as TREQ
4 : PIO0_RX0
Select PIO0's RX FIFO 0 as TREQ
5 : PIO0_RX1
Select PIO0's RX FIFO 1 as TREQ
6 : PIO0_RX2
Select PIO0's RX FIFO 2 as TREQ
7 : PIO0_RX3
Select PIO0's RX FIFO 3 as TREQ
8 : PIO1_TX0
Select PIO1's TX FIFO 0 as TREQ
9 : PIO1_TX1
Select PIO1's TX FIFO 1 as TREQ
10 : PIO1_TX2
Select PIO1's TX FIFO 2 as TREQ
11 : PIO1_TX3
Select PIO1's TX FIFO 3 as TREQ
12 : PIO1_RX0
Select PIO1's RX FIFO 0 as TREQ
13 : PIO1_RX1
Select PIO1's RX FIFO 1 as TREQ
14 : PIO1_RX2
Select PIO1's RX FIFO 2 as TREQ
15 : PIO1_RX3
Select PIO1's RX FIFO 3 as TREQ
16 : PIO2_TX0
Select PIO2's TX FIFO 0 as TREQ
17 : PIO2_TX1
Select PIO2's TX FIFO 1 as TREQ
18 : PIO2_TX2
Select PIO2's TX FIFO 2 as TREQ
19 : PIO2_TX3
Select PIO2's TX FIFO 3 as TREQ
20 : PIO2_RX0
Select PIO2's RX FIFO 0 as TREQ
21 : PIO2_RX1
Select PIO2's RX FIFO 1 as TREQ
22 : PIO2_RX2
Select PIO2's RX FIFO 2 as TREQ
23 : PIO2_RX3
Select PIO2's RX FIFO 3 as TREQ
24 : SPI0_TX
Select SPI0's TX FIFO as TREQ
25 : SPI0_RX
Select SPI0's RX FIFO as TREQ
26 : SPI1_TX
Select SPI1's TX FIFO as TREQ
27 : SPI1_RX
Select SPI1's RX FIFO as TREQ
28 : UART0_TX
Select UART0's TX FIFO as TREQ
29 : UART0_RX
Select UART0's RX FIFO as TREQ
30 : UART1_TX
Select UART1's TX FIFO as TREQ
31 : UART1_RX
Select UART1's RX FIFO as TREQ
32 : PWM_WRAP0
Select PWM Counter 0's Wrap Value as TREQ
33 : PWM_WRAP1
Select PWM Counter 1's Wrap Value as TREQ
34 : PWM_WRAP2
Select PWM Counter 2's Wrap Value as TREQ
35 : PWM_WRAP3
Select PWM Counter 3's Wrap Value as TREQ
36 : PWM_WRAP4
Select PWM Counter 4's Wrap Value as TREQ
37 : PWM_WRAP5
Select PWM Counter 5's Wrap Value as TREQ
38 : PWM_WRAP6
Select PWM Counter 6's Wrap Value as TREQ
39 : PWM_WRAP7
Select PWM Counter 7's Wrap Value as TREQ
40 : PWM_WRAP8
Select PWM Counter 8's Wrap Value as TREQ
41 : PWM_WRAP9
Select PWM Counter 9's Wrap Value as TREQ
42 : PWM_WRAP10
Select PWM Counter 0's Wrap Value as TREQ
43 : PWM_WRAP11
Select PWM Counter 1's Wrap Value as TREQ
44 : I2C0_TX
Select I2C0's TX FIFO as TREQ
45 : I2C0_RX
Select I2C0's RX FIFO as TREQ
46 : I2C1_TX
Select I2C1's TX FIFO as TREQ
47 : I2C1_RX
Select I2C1's RX FIFO as TREQ
48 : ADC
Select the ADC as TREQ
49 : XIP_STREAM
Select the XIP Streaming FIFO as TREQ
50 : XIP_QMITX
Select XIP_QMITX as TREQ
51 : XIP_QMIRX
Select XIP_QMIRX as TREQ
52 : HSTX
Select HSTX as TREQ
53 : CORESIGHT
Select CORESIGHT as TREQ
54 : SHA256
Select SHA256 as TREQ
59 : TIMER0
Select Timer 0 as TREQ
60 : TIMER1
Select Timer 1 as TREQ
61 : TIMER2
Select Timer 2 as TREQ (Optional)
62 : TIMER3
Select Timer 3 as TREQ (Optional)
63 : PERMANENT
Permanent request, for unpaced transfers.
End of enumeration elements list.
IRQ_QUIET : In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain.
This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks.
bits : 23 - 23 (1 bit)
access : read-write
BSWAP : Apply byte-swap transformation to DMA data.
For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order.
bits : 24 - 24 (1 bit)
access : read-write
SNIFF_EN : If 1, this channel's data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected.
This allows checksum to be enabled or disabled on a per-control- block basis.
bits : 25 - 25 (1 bit)
access : read-write
BUSY : This flag goes high when the channel starts a new transfer sequence, and low when the last transfer of that sequence completes. Clearing EN while BUSY is high pauses the channel, and BUSY will stay high while paused.
To terminate a sequence early (and clear the BUSY flag), see CHAN_ABORT.
bits : 26 - 26 (1 bit)
access : read-only
WRITE_ERROR : If 1, the channel received a write bus error. Write one to clear.
WRITE_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 5 transfers later)
bits : 29 - 29 (1 bit)
access : read-write
READ_ERROR : If 1, the channel received a read bus error. Write one to clear.
READ_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 3 transfers later)
bits : 30 - 30 (1 bit)
access : read-write
AHB_ERROR : Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel halts when it encounters any bus error, and always raises its channel IRQ flag.
bits : 31 - 31 (1 bit)
access : read-only
Alias for channel 8 CTRL register
address_offset : 0x210 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH8_AL1_CTRL :
bits : 0 - 31 (32 bit)
access : read-write
Alias for channel 8 READ_ADDR register
address_offset : 0x214 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH8_AL1_READ_ADDR :
bits : 0 - 31 (32 bit)
access : read-write
Alias for channel 8 WRITE_ADDR register
address_offset : 0x218 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH8_AL1_WRITE_ADDR :
bits : 0 - 31 (32 bit)
access : read-write
Alias for channel 8 TRANS_COUNT register
This is a trigger register (0xc). Writing a nonzero value will
reload the channel counter and start the channel.
address_offset : 0x21C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH8_AL1_TRANS_COUNT_TRIG :
bits : 0 - 31 (32 bit)
access : read-write
Alias for channel 8 CTRL register
address_offset : 0x220 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH8_AL2_CTRL :
bits : 0 - 31 (32 bit)
access : read-write
Alias for channel 8 TRANS_COUNT register
address_offset : 0x224 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH8_AL2_TRANS_COUNT :
bits : 0 - 31 (32 bit)
access : read-write
Alias for channel 8 READ_ADDR register
address_offset : 0x228 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH8_AL2_READ_ADDR :
bits : 0 - 31 (32 bit)
access : read-write
Alias for channel 8 WRITE_ADDR register
This is a trigger register (0xc). Writing a nonzero value will
reload the channel counter and start the channel.
address_offset : 0x22C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH8_AL2_WRITE_ADDR_TRIG :
bits : 0 - 31 (32 bit)
access : read-write
Alias for channel 8 CTRL register
address_offset : 0x230 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH8_AL3_CTRL :
bits : 0 - 31 (32 bit)
access : read-write
Alias for channel 8 WRITE_ADDR register
address_offset : 0x234 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH8_AL3_WRITE_ADDR :
bits : 0 - 31 (32 bit)
access : read-write
Alias for channel 8 TRANS_COUNT register
address_offset : 0x238 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH8_AL3_TRANS_COUNT :
bits : 0 - 31 (32 bit)
access : read-write
Alias for channel 8 READ_ADDR register
This is a trigger register (0xc). Writing a nonzero value will
reload the channel counter and start the channel.
address_offset : 0x23C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH8_AL3_READ_ADDR_TRIG :
bits : 0 - 31 (32 bit)
access : read-write
Alias for channel 0 TRANS_COUNT register
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH0_AL2_TRANS_COUNT :
bits : 0 - 31 (32 bit)
access : read-write
DMA Channel 9 Read Address pointer
address_offset : 0x240 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH9_READ_ADDR : This register updates automatically each time a read completes. The current value is the next address to be read by this channel.
bits : 0 - 31 (32 bit)
access : read-write
DMA Channel 9 Write Address pointer
address_offset : 0x244 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH9_WRITE_ADDR : This register updates automatically each time a write completes. The current value is the next address to be written by this channel.
bits : 0 - 31 (32 bit)
access : read-write
DMA Channel 9 Transfer Count
address_offset : 0x248 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
COUNT : 28-bit transfer count (256 million transfers maximum).
Program the number of bus transfers a channel will perform before halting. Note that, if transfers are larger than one byte in size, this is not equal to the number of bytes transferred (see CTRL_DATA_SIZE).
When the channel is active, reading this register shows the number of transfers remaining, updating automatically each time a write transfer completes.
Writing this register sets the RELOAD value for the transfer counter. Each time this channel is triggered, the RELOAD value is copied into the live transfer counter. The channel can be started multiple times, and will perform the same number of transfers each time, as programmed by most recent write.
The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a trigger, the written value is used immediately as the length of the new transfer sequence, as well as being written to RELOAD.
bits : 0 - 27 (28 bit)
access : read-write
MODE : When MODE is 0x0, the transfer count decrements with each transfer until 0, and then the channel triggers the next channel indicated by CTRL_CHAIN_TO.
When MODE is 0x1, the transfer count decrements with each transfer until 0, and then the channel re-triggers itself, in addition to the trigger indicated by CTRL_CHAIN_TO. This is useful for e.g. an endless ring-buffer DMA with periodic interrupts.
When MODE is 0xf, the transfer count does not decrement. The DMA channel performs an endless sequence of transfers, never triggering other channels or raising interrupts, until an ABORT is raised.
All other values are reserved.
bits : 28 - 31 (4 bit)
access : read-write
Enumeration:
0 : NORMAL
1 : TRIGGER_SELF
15 : ENDLESS
End of enumeration elements list.
DMA Channel 9 Control and Status
address_offset : 0x24C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : DMA Channel Enable.
When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high)
bits : 0 - 0 (1 bit)
access : read-write
HIGH_PRIORITY : HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels.
This only affects the order in which the DMA schedules channels. The DMA's bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput.
bits : 1 - 1 (1 bit)
access : read-write
DATA_SIZE : Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer.
bits : 2 - 3 (2 bit)
access : read-write
Enumeration:
0 : SIZE_BYTE
1 : SIZE_HALFWORD
2 : SIZE_WORD
End of enumeration elements list.
INCR_READ : If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address.
Generally this should be disabled for peripheral-to-memory transfers.
bits : 4 - 4 (1 bit)
access : read-write
INCR_READ_REV : If 1, and INCR_READ is 1, the read address is decremented rather than incremented with each transfer.
If 1, and INCR_READ is 0, this otherwise-unused combination causes the read address to be incremented by twice the transfer size, i.e. skipping over alternate addresses.
bits : 5 - 5 (1 bit)
access : read-write
INCR_WRITE : If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address.
Generally this should be disabled for memory-to-peripheral transfers.
bits : 6 - 6 (1 bit)
access : read-write
INCR_WRITE_REV : If 1, and INCR_WRITE is 1, the write address is decremented rather than incremented with each transfer.
If 1, and INCR_WRITE is 0, this otherwise-unused combination causes the write address to be incremented by twice the transfer size, i.e. skipping over alternate addresses.
bits : 7 - 7 (1 bit)
access : read-write
RING_SIZE : Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned ring buffers.
Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL.
bits : 8 - 11 (4 bit)
access : read-write
Enumeration:
0 : RING_NONE
End of enumeration elements list.
RING_SEL : Select whether RING_SIZE applies to read or write addresses.
If 0, read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, write addresses are wrapped.
bits : 12 - 12 (1 bit)
access : read-write
CHAIN_TO : When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_.
Note this field resets to 0, so channels 1 and above will chain to channel 0 by default. Set this field to avoid this behaviour.
bits : 13 - 16 (4 bit)
access : read-write
TREQ_SEL : Select a Transfer Request signal.
The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system).
0x0 to 0x3a -> select DREQ n as TREQ
bits : 17 - 22 (6 bit)
access : read-write
Enumeration:
0 : PIO0_TX0
Select PIO0's TX FIFO 0 as TREQ
1 : PIO0_TX1
Select PIO0's TX FIFO 1 as TREQ
2 : PIO0_TX2
Select PIO0's TX FIFO 2 as TREQ
3 : PIO0_TX3
Select PIO0's TX FIFO 3 as TREQ
4 : PIO0_RX0
Select PIO0's RX FIFO 0 as TREQ
5 : PIO0_RX1
Select PIO0's RX FIFO 1 as TREQ
6 : PIO0_RX2
Select PIO0's RX FIFO 2 as TREQ
7 : PIO0_RX3
Select PIO0's RX FIFO 3 as TREQ
8 : PIO1_TX0
Select PIO1's TX FIFO 0 as TREQ
9 : PIO1_TX1
Select PIO1's TX FIFO 1 as TREQ
10 : PIO1_TX2
Select PIO1's TX FIFO 2 as TREQ
11 : PIO1_TX3
Select PIO1's TX FIFO 3 as TREQ
12 : PIO1_RX0
Select PIO1's RX FIFO 0 as TREQ
13 : PIO1_RX1
Select PIO1's RX FIFO 1 as TREQ
14 : PIO1_RX2
Select PIO1's RX FIFO 2 as TREQ
15 : PIO1_RX3
Select PIO1's RX FIFO 3 as TREQ
16 : PIO2_TX0
Select PIO2's TX FIFO 0 as TREQ
17 : PIO2_TX1
Select PIO2's TX FIFO 1 as TREQ
18 : PIO2_TX2
Select PIO2's TX FIFO 2 as TREQ
19 : PIO2_TX3
Select PIO2's TX FIFO 3 as TREQ
20 : PIO2_RX0
Select PIO2's RX FIFO 0 as TREQ
21 : PIO2_RX1
Select PIO2's RX FIFO 1 as TREQ
22 : PIO2_RX2
Select PIO2's RX FIFO 2 as TREQ
23 : PIO2_RX3
Select PIO2's RX FIFO 3 as TREQ
24 : SPI0_TX
Select SPI0's TX FIFO as TREQ
25 : SPI0_RX
Select SPI0's RX FIFO as TREQ
26 : SPI1_TX
Select SPI1's TX FIFO as TREQ
27 : SPI1_RX
Select SPI1's RX FIFO as TREQ
28 : UART0_TX
Select UART0's TX FIFO as TREQ
29 : UART0_RX
Select UART0's RX FIFO as TREQ
30 : UART1_TX
Select UART1's TX FIFO as TREQ
31 : UART1_RX
Select UART1's RX FIFO as TREQ
32 : PWM_WRAP0
Select PWM Counter 0's Wrap Value as TREQ
33 : PWM_WRAP1
Select PWM Counter 1's Wrap Value as TREQ
34 : PWM_WRAP2
Select PWM Counter 2's Wrap Value as TREQ
35 : PWM_WRAP3
Select PWM Counter 3's Wrap Value as TREQ
36 : PWM_WRAP4
Select PWM Counter 4's Wrap Value as TREQ
37 : PWM_WRAP5
Select PWM Counter 5's Wrap Value as TREQ
38 : PWM_WRAP6
Select PWM Counter 6's Wrap Value as TREQ
39 : PWM_WRAP7
Select PWM Counter 7's Wrap Value as TREQ
40 : PWM_WRAP8
Select PWM Counter 8's Wrap Value as TREQ
41 : PWM_WRAP9
Select PWM Counter 9's Wrap Value as TREQ
42 : PWM_WRAP10
Select PWM Counter 0's Wrap Value as TREQ
43 : PWM_WRAP11
Select PWM Counter 1's Wrap Value as TREQ
44 : I2C0_TX
Select I2C0's TX FIFO as TREQ
45 : I2C0_RX
Select I2C0's RX FIFO as TREQ
46 : I2C1_TX
Select I2C1's TX FIFO as TREQ
47 : I2C1_RX
Select I2C1's RX FIFO as TREQ
48 : ADC
Select the ADC as TREQ
49 : XIP_STREAM
Select the XIP Streaming FIFO as TREQ
50 : XIP_QMITX
Select XIP_QMITX as TREQ
51 : XIP_QMIRX
Select XIP_QMIRX as TREQ
52 : HSTX
Select HSTX as TREQ
53 : CORESIGHT
Select CORESIGHT as TREQ
54 : SHA256
Select SHA256 as TREQ
59 : TIMER0
Select Timer 0 as TREQ
60 : TIMER1
Select Timer 1 as TREQ
61 : TIMER2
Select Timer 2 as TREQ (Optional)
62 : TIMER3
Select Timer 3 as TREQ (Optional)
63 : PERMANENT
Permanent request, for unpaced transfers.
End of enumeration elements list.
IRQ_QUIET : In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain.
This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks.
bits : 23 - 23 (1 bit)
access : read-write
BSWAP : Apply byte-swap transformation to DMA data.
For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order.
bits : 24 - 24 (1 bit)
access : read-write
SNIFF_EN : If 1, this channel's data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected.
This allows checksum to be enabled or disabled on a per-control- block basis.
bits : 25 - 25 (1 bit)
access : read-write
BUSY : This flag goes high when the channel starts a new transfer sequence, and low when the last transfer of that sequence completes. Clearing EN while BUSY is high pauses the channel, and BUSY will stay high while paused.
To terminate a sequence early (and clear the BUSY flag), see CHAN_ABORT.
bits : 26 - 26 (1 bit)
access : read-only
WRITE_ERROR : If 1, the channel received a write bus error. Write one to clear.
WRITE_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 5 transfers later)
bits : 29 - 29 (1 bit)
access : read-write
READ_ERROR : If 1, the channel received a read bus error. Write one to clear.
READ_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 3 transfers later)
bits : 30 - 30 (1 bit)
access : read-write
AHB_ERROR : Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel halts when it encounters any bus error, and always raises its channel IRQ flag.
bits : 31 - 31 (1 bit)
access : read-only
Alias for channel 9 CTRL register
address_offset : 0x250 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH9_AL1_CTRL :
bits : 0 - 31 (32 bit)
access : read-write
Alias for channel 9 READ_ADDR register
address_offset : 0x254 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH9_AL1_READ_ADDR :
bits : 0 - 31 (32 bit)
access : read-write
Alias for channel 9 WRITE_ADDR register
address_offset : 0x258 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH9_AL1_WRITE_ADDR :
bits : 0 - 31 (32 bit)
access : read-write
Alias for channel 9 TRANS_COUNT register
This is a trigger register (0xc). Writing a nonzero value will
reload the channel counter and start the channel.
address_offset : 0x25C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH9_AL1_TRANS_COUNT_TRIG :
bits : 0 - 31 (32 bit)
access : read-write
Alias for channel 9 CTRL register
address_offset : 0x260 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH9_AL2_CTRL :
bits : 0 - 31 (32 bit)
access : read-write
Alias for channel 9 TRANS_COUNT register
address_offset : 0x264 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH9_AL2_TRANS_COUNT :
bits : 0 - 31 (32 bit)
access : read-write
Alias for channel 9 READ_ADDR register
address_offset : 0x268 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH9_AL2_READ_ADDR :
bits : 0 - 31 (32 bit)
access : read-write
Alias for channel 9 WRITE_ADDR register
This is a trigger register (0xc). Writing a nonzero value will
reload the channel counter and start the channel.
address_offset : 0x26C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH9_AL2_WRITE_ADDR_TRIG :
bits : 0 - 31 (32 bit)
access : read-write
Alias for channel 9 CTRL register
address_offset : 0x270 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH9_AL3_CTRL :
bits : 0 - 31 (32 bit)
access : read-write
Alias for channel 9 WRITE_ADDR register
address_offset : 0x274 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH9_AL3_WRITE_ADDR :
bits : 0 - 31 (32 bit)
access : read-write
Alias for channel 9 TRANS_COUNT register
address_offset : 0x278 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH9_AL3_TRANS_COUNT :
bits : 0 - 31 (32 bit)
access : read-write
Alias for channel 9 READ_ADDR register
This is a trigger register (0xc). Writing a nonzero value will
reload the channel counter and start the channel.
address_offset : 0x27C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH9_AL3_READ_ADDR_TRIG :
bits : 0 - 31 (32 bit)
access : read-write
Alias for channel 0 READ_ADDR register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH0_AL2_READ_ADDR :
bits : 0 - 31 (32 bit)
access : read-write
DMA Channel 10 Read Address pointer
address_offset : 0x280 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH10_READ_ADDR : This register updates automatically each time a read completes. The current value is the next address to be read by this channel.
bits : 0 - 31 (32 bit)
access : read-write
DMA Channel 10 Write Address pointer
address_offset : 0x284 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH10_WRITE_ADDR : This register updates automatically each time a write completes. The current value is the next address to be written by this channel.
bits : 0 - 31 (32 bit)
access : read-write
DMA Channel 10 Transfer Count
address_offset : 0x288 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
COUNT : 28-bit transfer count (256 million transfers maximum).
Program the number of bus transfers a channel will perform before halting. Note that, if transfers are larger than one byte in size, this is not equal to the number of bytes transferred (see CTRL_DATA_SIZE).
When the channel is active, reading this register shows the number of transfers remaining, updating automatically each time a write transfer completes.
Writing this register sets the RELOAD value for the transfer counter. Each time this channel is triggered, the RELOAD value is copied into the live transfer counter. The channel can be started multiple times, and will perform the same number of transfers each time, as programmed by most recent write.
The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a trigger, the written value is used immediately as the length of the new transfer sequence, as well as being written to RELOAD.
bits : 0 - 27 (28 bit)
access : read-write
MODE : When MODE is 0x0, the transfer count decrements with each transfer until 0, and then the channel triggers the next channel indicated by CTRL_CHAIN_TO.
When MODE is 0x1, the transfer count decrements with each transfer until 0, and then the channel re-triggers itself, in addition to the trigger indicated by CTRL_CHAIN_TO. This is useful for e.g. an endless ring-buffer DMA with periodic interrupts.
When MODE is 0xf, the transfer count does not decrement. The DMA channel performs an endless sequence of transfers, never triggering other channels or raising interrupts, until an ABORT is raised.
All other values are reserved.
bits : 28 - 31 (4 bit)
access : read-write
Enumeration:
0 : NORMAL
1 : TRIGGER_SELF
15 : ENDLESS
End of enumeration elements list.
DMA Channel 10 Control and Status
address_offset : 0x28C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : DMA Channel Enable.
When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high)
bits : 0 - 0 (1 bit)
access : read-write
HIGH_PRIORITY : HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels.
This only affects the order in which the DMA schedules channels. The DMA's bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput.
bits : 1 - 1 (1 bit)
access : read-write
DATA_SIZE : Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer.
bits : 2 - 3 (2 bit)
access : read-write
Enumeration:
0 : SIZE_BYTE
1 : SIZE_HALFWORD
2 : SIZE_WORD
End of enumeration elements list.
INCR_READ : If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address.
Generally this should be disabled for peripheral-to-memory transfers.
bits : 4 - 4 (1 bit)
access : read-write
INCR_READ_REV : If 1, and INCR_READ is 1, the read address is decremented rather than incremented with each transfer.
If 1, and INCR_READ is 0, this otherwise-unused combination causes the read address to be incremented by twice the transfer size, i.e. skipping over alternate addresses.
bits : 5 - 5 (1 bit)
access : read-write
INCR_WRITE : If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address.
Generally this should be disabled for memory-to-peripheral transfers.
bits : 6 - 6 (1 bit)
access : read-write
INCR_WRITE_REV : If 1, and INCR_WRITE is 1, the write address is decremented rather than incremented with each transfer.
If 1, and INCR_WRITE is 0, this otherwise-unused combination causes the write address to be incremented by twice the transfer size, i.e. skipping over alternate addresses.
bits : 7 - 7 (1 bit)
access : read-write
RING_SIZE : Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned ring buffers.
Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL.
bits : 8 - 11 (4 bit)
access : read-write
Enumeration:
0 : RING_NONE
End of enumeration elements list.
RING_SEL : Select whether RING_SIZE applies to read or write addresses.
If 0, read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, write addresses are wrapped.
bits : 12 - 12 (1 bit)
access : read-write
CHAIN_TO : When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_.
Note this field resets to 0, so channels 1 and above will chain to channel 0 by default. Set this field to avoid this behaviour.
bits : 13 - 16 (4 bit)
access : read-write
TREQ_SEL : Select a Transfer Request signal.
The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system).
0x0 to 0x3a -> select DREQ n as TREQ
bits : 17 - 22 (6 bit)
access : read-write
Enumeration:
0 : PIO0_TX0
Select PIO0's TX FIFO 0 as TREQ
1 : PIO0_TX1
Select PIO0's TX FIFO 1 as TREQ
2 : PIO0_TX2
Select PIO0's TX FIFO 2 as TREQ
3 : PIO0_TX3
Select PIO0's TX FIFO 3 as TREQ
4 : PIO0_RX0
Select PIO0's RX FIFO 0 as TREQ
5 : PIO0_RX1
Select PIO0's RX FIFO 1 as TREQ
6 : PIO0_RX2
Select PIO0's RX FIFO 2 as TREQ
7 : PIO0_RX3
Select PIO0's RX FIFO 3 as TREQ
8 : PIO1_TX0
Select PIO1's TX FIFO 0 as TREQ
9 : PIO1_TX1
Select PIO1's TX FIFO 1 as TREQ
10 : PIO1_TX2
Select PIO1's TX FIFO 2 as TREQ
11 : PIO1_TX3
Select PIO1's TX FIFO 3 as TREQ
12 : PIO1_RX0
Select PIO1's RX FIFO 0 as TREQ
13 : PIO1_RX1
Select PIO1's RX FIFO 1 as TREQ
14 : PIO1_RX2
Select PIO1's RX FIFO 2 as TREQ
15 : PIO1_RX3
Select PIO1's RX FIFO 3 as TREQ
16 : PIO2_TX0
Select PIO2's TX FIFO 0 as TREQ
17 : PIO2_TX1
Select PIO2's TX FIFO 1 as TREQ
18 : PIO2_TX2
Select PIO2's TX FIFO 2 as TREQ
19 : PIO2_TX3
Select PIO2's TX FIFO 3 as TREQ
20 : PIO2_RX0
Select PIO2's RX FIFO 0 as TREQ
21 : PIO2_RX1
Select PIO2's RX FIFO 1 as TREQ
22 : PIO2_RX2
Select PIO2's RX FIFO 2 as TREQ
23 : PIO2_RX3
Select PIO2's RX FIFO 3 as TREQ
24 : SPI0_TX
Select SPI0's TX FIFO as TREQ
25 : SPI0_RX
Select SPI0's RX FIFO as TREQ
26 : SPI1_TX
Select SPI1's TX FIFO as TREQ
27 : SPI1_RX
Select SPI1's RX FIFO as TREQ
28 : UART0_TX
Select UART0's TX FIFO as TREQ
29 : UART0_RX
Select UART0's RX FIFO as TREQ
30 : UART1_TX
Select UART1's TX FIFO as TREQ
31 : UART1_RX
Select UART1's RX FIFO as TREQ
32 : PWM_WRAP0
Select PWM Counter 0's Wrap Value as TREQ
33 : PWM_WRAP1
Select PWM Counter 1's Wrap Value as TREQ
34 : PWM_WRAP2
Select PWM Counter 2's Wrap Value as TREQ
35 : PWM_WRAP3
Select PWM Counter 3's Wrap Value as TREQ
36 : PWM_WRAP4
Select PWM Counter 4's Wrap Value as TREQ
37 : PWM_WRAP5
Select PWM Counter 5's Wrap Value as TREQ
38 : PWM_WRAP6
Select PWM Counter 6's Wrap Value as TREQ
39 : PWM_WRAP7
Select PWM Counter 7's Wrap Value as TREQ
40 : PWM_WRAP8
Select PWM Counter 8's Wrap Value as TREQ
41 : PWM_WRAP9
Select PWM Counter 9's Wrap Value as TREQ
42 : PWM_WRAP10
Select PWM Counter 0's Wrap Value as TREQ
43 : PWM_WRAP11
Select PWM Counter 1's Wrap Value as TREQ
44 : I2C0_TX
Select I2C0's TX FIFO as TREQ
45 : I2C0_RX
Select I2C0's RX FIFO as TREQ
46 : I2C1_TX
Select I2C1's TX FIFO as TREQ
47 : I2C1_RX
Select I2C1's RX FIFO as TREQ
48 : ADC
Select the ADC as TREQ
49 : XIP_STREAM
Select the XIP Streaming FIFO as TREQ
50 : XIP_QMITX
Select XIP_QMITX as TREQ
51 : XIP_QMIRX
Select XIP_QMIRX as TREQ
52 : HSTX
Select HSTX as TREQ
53 : CORESIGHT
Select CORESIGHT as TREQ
54 : SHA256
Select SHA256 as TREQ
59 : TIMER0
Select Timer 0 as TREQ
60 : TIMER1
Select Timer 1 as TREQ
61 : TIMER2
Select Timer 2 as TREQ (Optional)
62 : TIMER3
Select Timer 3 as TREQ (Optional)
63 : PERMANENT
Permanent request, for unpaced transfers.
End of enumeration elements list.
IRQ_QUIET : In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain.
This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks.
bits : 23 - 23 (1 bit)
access : read-write
BSWAP : Apply byte-swap transformation to DMA data.
For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order.
bits : 24 - 24 (1 bit)
access : read-write
SNIFF_EN : If 1, this channel's data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected.
This allows checksum to be enabled or disabled on a per-control- block basis.
bits : 25 - 25 (1 bit)
access : read-write
BUSY : This flag goes high when the channel starts a new transfer sequence, and low when the last transfer of that sequence completes. Clearing EN while BUSY is high pauses the channel, and BUSY will stay high while paused.
To terminate a sequence early (and clear the BUSY flag), see CHAN_ABORT.
bits : 26 - 26 (1 bit)
access : read-only
WRITE_ERROR : If 1, the channel received a write bus error. Write one to clear.
WRITE_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 5 transfers later)
bits : 29 - 29 (1 bit)
access : read-write
READ_ERROR : If 1, the channel received a read bus error. Write one to clear.
READ_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 3 transfers later)
bits : 30 - 30 (1 bit)
access : read-write
AHB_ERROR : Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel halts when it encounters any bus error, and always raises its channel IRQ flag.
bits : 31 - 31 (1 bit)
access : read-only
Alias for channel 10 CTRL register
address_offset : 0x290 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH10_AL1_CTRL :
bits : 0 - 31 (32 bit)
access : read-write
Alias for channel 10 READ_ADDR register
address_offset : 0x294 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH10_AL1_READ_ADDR :
bits : 0 - 31 (32 bit)
access : read-write
Alias for channel 10 WRITE_ADDR register
address_offset : 0x298 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH10_AL1_WRITE_ADDR :
bits : 0 - 31 (32 bit)
access : read-write
Alias for channel 10 TRANS_COUNT register
This is a trigger register (0xc). Writing a nonzero value will
reload the channel counter and start the channel.
address_offset : 0x29C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH10_AL1_TRANS_COUNT_TRIG :
bits : 0 - 31 (32 bit)
access : read-write
Alias for channel 10 CTRL register
address_offset : 0x2A0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH10_AL2_CTRL :
bits : 0 - 31 (32 bit)
access : read-write
Alias for channel 10 TRANS_COUNT register
address_offset : 0x2A4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH10_AL2_TRANS_COUNT :
bits : 0 - 31 (32 bit)
access : read-write
Alias for channel 10 READ_ADDR register
address_offset : 0x2A8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH10_AL2_READ_ADDR :
bits : 0 - 31 (32 bit)
access : read-write
Alias for channel 10 WRITE_ADDR register
This is a trigger register (0xc). Writing a nonzero value will
reload the channel counter and start the channel.
address_offset : 0x2AC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH10_AL2_WRITE_ADDR_TRIG :
bits : 0 - 31 (32 bit)
access : read-write
Alias for channel 10 CTRL register
address_offset : 0x2B0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH10_AL3_CTRL :
bits : 0 - 31 (32 bit)
access : read-write
Alias for channel 10 WRITE_ADDR register
address_offset : 0x2B4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH10_AL3_WRITE_ADDR :
bits : 0 - 31 (32 bit)
access : read-write
Alias for channel 10 TRANS_COUNT register
address_offset : 0x2B8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH10_AL3_TRANS_COUNT :
bits : 0 - 31 (32 bit)
access : read-write
Alias for channel 10 READ_ADDR register
This is a trigger register (0xc). Writing a nonzero value will
reload the channel counter and start the channel.
address_offset : 0x2BC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH10_AL3_READ_ADDR_TRIG :
bits : 0 - 31 (32 bit)
access : read-write
Alias for channel 0 WRITE_ADDR register
This is a trigger register (0xc). Writing a nonzero value will
reload the channel counter and start the channel.
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH0_AL2_WRITE_ADDR_TRIG :
bits : 0 - 31 (32 bit)
access : read-write
DMA Channel 11 Read Address pointer
address_offset : 0x2C0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH11_READ_ADDR : This register updates automatically each time a read completes. The current value is the next address to be read by this channel.
bits : 0 - 31 (32 bit)
access : read-write
DMA Channel 11 Write Address pointer
address_offset : 0x2C4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH11_WRITE_ADDR : This register updates automatically each time a write completes. The current value is the next address to be written by this channel.
bits : 0 - 31 (32 bit)
access : read-write
DMA Channel 11 Transfer Count
address_offset : 0x2C8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
COUNT : 28-bit transfer count (256 million transfers maximum).
Program the number of bus transfers a channel will perform before halting. Note that, if transfers are larger than one byte in size, this is not equal to the number of bytes transferred (see CTRL_DATA_SIZE).
When the channel is active, reading this register shows the number of transfers remaining, updating automatically each time a write transfer completes.
Writing this register sets the RELOAD value for the transfer counter. Each time this channel is triggered, the RELOAD value is copied into the live transfer counter. The channel can be started multiple times, and will perform the same number of transfers each time, as programmed by most recent write.
The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a trigger, the written value is used immediately as the length of the new transfer sequence, as well as being written to RELOAD.
bits : 0 - 27 (28 bit)
access : read-write
MODE : When MODE is 0x0, the transfer count decrements with each transfer until 0, and then the channel triggers the next channel indicated by CTRL_CHAIN_TO.
When MODE is 0x1, the transfer count decrements with each transfer until 0, and then the channel re-triggers itself, in addition to the trigger indicated by CTRL_CHAIN_TO. This is useful for e.g. an endless ring-buffer DMA with periodic interrupts.
When MODE is 0xf, the transfer count does not decrement. The DMA channel performs an endless sequence of transfers, never triggering other channels or raising interrupts, until an ABORT is raised.
All other values are reserved.
bits : 28 - 31 (4 bit)
access : read-write
Enumeration:
0 : NORMAL
1 : TRIGGER_SELF
15 : ENDLESS
End of enumeration elements list.
DMA Channel 11 Control and Status
address_offset : 0x2CC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : DMA Channel Enable.
When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high)
bits : 0 - 0 (1 bit)
access : read-write
HIGH_PRIORITY : HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels.
This only affects the order in which the DMA schedules channels. The DMA's bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput.
bits : 1 - 1 (1 bit)
access : read-write
DATA_SIZE : Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer.
bits : 2 - 3 (2 bit)
access : read-write
Enumeration:
0 : SIZE_BYTE
1 : SIZE_HALFWORD
2 : SIZE_WORD
End of enumeration elements list.
INCR_READ : If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address.
Generally this should be disabled for peripheral-to-memory transfers.
bits : 4 - 4 (1 bit)
access : read-write
INCR_READ_REV : If 1, and INCR_READ is 1, the read address is decremented rather than incremented with each transfer.
If 1, and INCR_READ is 0, this otherwise-unused combination causes the read address to be incremented by twice the transfer size, i.e. skipping over alternate addresses.
bits : 5 - 5 (1 bit)
access : read-write
INCR_WRITE : If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address.
Generally this should be disabled for memory-to-peripheral transfers.
bits : 6 - 6 (1 bit)
access : read-write
INCR_WRITE_REV : If 1, and INCR_WRITE is 1, the write address is decremented rather than incremented with each transfer.
If 1, and INCR_WRITE is 0, this otherwise-unused combination causes the write address to be incremented by twice the transfer size, i.e. skipping over alternate addresses.
bits : 7 - 7 (1 bit)
access : read-write
RING_SIZE : Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned ring buffers.
Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL.
bits : 8 - 11 (4 bit)
access : read-write
Enumeration:
0 : RING_NONE
End of enumeration elements list.
RING_SEL : Select whether RING_SIZE applies to read or write addresses.
If 0, read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, write addresses are wrapped.
bits : 12 - 12 (1 bit)
access : read-write
CHAIN_TO : When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_.
Note this field resets to 0, so channels 1 and above will chain to channel 0 by default. Set this field to avoid this behaviour.
bits : 13 - 16 (4 bit)
access : read-write
TREQ_SEL : Select a Transfer Request signal.
The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system).
0x0 to 0x3a -> select DREQ n as TREQ
bits : 17 - 22 (6 bit)
access : read-write
Enumeration:
0 : PIO0_TX0
Select PIO0's TX FIFO 0 as TREQ
1 : PIO0_TX1
Select PIO0's TX FIFO 1 as TREQ
2 : PIO0_TX2
Select PIO0's TX FIFO 2 as TREQ
3 : PIO0_TX3
Select PIO0's TX FIFO 3 as TREQ
4 : PIO0_RX0
Select PIO0's RX FIFO 0 as TREQ
5 : PIO0_RX1
Select PIO0's RX FIFO 1 as TREQ
6 : PIO0_RX2
Select PIO0's RX FIFO 2 as TREQ
7 : PIO0_RX3
Select PIO0's RX FIFO 3 as TREQ
8 : PIO1_TX0
Select PIO1's TX FIFO 0 as TREQ
9 : PIO1_TX1
Select PIO1's TX FIFO 1 as TREQ
10 : PIO1_TX2
Select PIO1's TX FIFO 2 as TREQ
11 : PIO1_TX3
Select PIO1's TX FIFO 3 as TREQ
12 : PIO1_RX0
Select PIO1's RX FIFO 0 as TREQ
13 : PIO1_RX1
Select PIO1's RX FIFO 1 as TREQ
14 : PIO1_RX2
Select PIO1's RX FIFO 2 as TREQ
15 : PIO1_RX3
Select PIO1's RX FIFO 3 as TREQ
16 : PIO2_TX0
Select PIO2's TX FIFO 0 as TREQ
17 : PIO2_TX1
Select PIO2's TX FIFO 1 as TREQ
18 : PIO2_TX2
Select PIO2's TX FIFO 2 as TREQ
19 : PIO2_TX3
Select PIO2's TX FIFO 3 as TREQ
20 : PIO2_RX0
Select PIO2's RX FIFO 0 as TREQ
21 : PIO2_RX1
Select PIO2's RX FIFO 1 as TREQ
22 : PIO2_RX2
Select PIO2's RX FIFO 2 as TREQ
23 : PIO2_RX3
Select PIO2's RX FIFO 3 as TREQ
24 : SPI0_TX
Select SPI0's TX FIFO as TREQ
25 : SPI0_RX
Select SPI0's RX FIFO as TREQ
26 : SPI1_TX
Select SPI1's TX FIFO as TREQ
27 : SPI1_RX
Select SPI1's RX FIFO as TREQ
28 : UART0_TX
Select UART0's TX FIFO as TREQ
29 : UART0_RX
Select UART0's RX FIFO as TREQ
30 : UART1_TX
Select UART1's TX FIFO as TREQ
31 : UART1_RX
Select UART1's RX FIFO as TREQ
32 : PWM_WRAP0
Select PWM Counter 0's Wrap Value as TREQ
33 : PWM_WRAP1
Select PWM Counter 1's Wrap Value as TREQ
34 : PWM_WRAP2
Select PWM Counter 2's Wrap Value as TREQ
35 : PWM_WRAP3
Select PWM Counter 3's Wrap Value as TREQ
36 : PWM_WRAP4
Select PWM Counter 4's Wrap Value as TREQ
37 : PWM_WRAP5
Select PWM Counter 5's Wrap Value as TREQ
38 : PWM_WRAP6
Select PWM Counter 6's Wrap Value as TREQ
39 : PWM_WRAP7
Select PWM Counter 7's Wrap Value as TREQ
40 : PWM_WRAP8
Select PWM Counter 8's Wrap Value as TREQ
41 : PWM_WRAP9
Select PWM Counter 9's Wrap Value as TREQ
42 : PWM_WRAP10
Select PWM Counter 0's Wrap Value as TREQ
43 : PWM_WRAP11
Select PWM Counter 1's Wrap Value as TREQ
44 : I2C0_TX
Select I2C0's TX FIFO as TREQ
45 : I2C0_RX
Select I2C0's RX FIFO as TREQ
46 : I2C1_TX
Select I2C1's TX FIFO as TREQ
47 : I2C1_RX
Select I2C1's RX FIFO as TREQ
48 : ADC
Select the ADC as TREQ
49 : XIP_STREAM
Select the XIP Streaming FIFO as TREQ
50 : XIP_QMITX
Select XIP_QMITX as TREQ
51 : XIP_QMIRX
Select XIP_QMIRX as TREQ
52 : HSTX
Select HSTX as TREQ
53 : CORESIGHT
Select CORESIGHT as TREQ
54 : SHA256
Select SHA256 as TREQ
59 : TIMER0
Select Timer 0 as TREQ
60 : TIMER1
Select Timer 1 as TREQ
61 : TIMER2
Select Timer 2 as TREQ (Optional)
62 : TIMER3
Select Timer 3 as TREQ (Optional)
63 : PERMANENT
Permanent request, for unpaced transfers.
End of enumeration elements list.
IRQ_QUIET : In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain.
This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks.
bits : 23 - 23 (1 bit)
access : read-write
BSWAP : Apply byte-swap transformation to DMA data.
For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order.
bits : 24 - 24 (1 bit)
access : read-write
SNIFF_EN : If 1, this channel's data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected.
This allows checksum to be enabled or disabled on a per-control- block basis.
bits : 25 - 25 (1 bit)
access : read-write
BUSY : This flag goes high when the channel starts a new transfer sequence, and low when the last transfer of that sequence completes. Clearing EN while BUSY is high pauses the channel, and BUSY will stay high while paused.
To terminate a sequence early (and clear the BUSY flag), see CHAN_ABORT.
bits : 26 - 26 (1 bit)
access : read-only
WRITE_ERROR : If 1, the channel received a write bus error. Write one to clear.
WRITE_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 5 transfers later)
bits : 29 - 29 (1 bit)
access : read-write
READ_ERROR : If 1, the channel received a read bus error. Write one to clear.
READ_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 3 transfers later)
bits : 30 - 30 (1 bit)
access : read-write
AHB_ERROR : Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel halts when it encounters any bus error, and always raises its channel IRQ flag.
bits : 31 - 31 (1 bit)
access : read-only
Alias for channel 11 CTRL register
address_offset : 0x2D0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH11_AL1_CTRL :
bits : 0 - 31 (32 bit)
access : read-write
Alias for channel 11 READ_ADDR register
address_offset : 0x2D4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH11_AL1_READ_ADDR :
bits : 0 - 31 (32 bit)
access : read-write
Alias for channel 11 WRITE_ADDR register
address_offset : 0x2D8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH11_AL1_WRITE_ADDR :
bits : 0 - 31 (32 bit)
access : read-write
Alias for channel 11 TRANS_COUNT register
This is a trigger register (0xc). Writing a nonzero value will
reload the channel counter and start the channel.
address_offset : 0x2DC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH11_AL1_TRANS_COUNT_TRIG :
bits : 0 - 31 (32 bit)
access : read-write
Alias for channel 11 CTRL register
address_offset : 0x2E0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH11_AL2_CTRL :
bits : 0 - 31 (32 bit)
access : read-write
Alias for channel 11 TRANS_COUNT register
address_offset : 0x2E4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH11_AL2_TRANS_COUNT :
bits : 0 - 31 (32 bit)
access : read-write
Alias for channel 11 READ_ADDR register
address_offset : 0x2E8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH11_AL2_READ_ADDR :
bits : 0 - 31 (32 bit)
access : read-write
Alias for channel 11 WRITE_ADDR register
This is a trigger register (0xc). Writing a nonzero value will
reload the channel counter and start the channel.
address_offset : 0x2EC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH11_AL2_WRITE_ADDR_TRIG :
bits : 0 - 31 (32 bit)
access : read-write
Alias for channel 11 CTRL register
address_offset : 0x2F0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH11_AL3_CTRL :
bits : 0 - 31 (32 bit)
access : read-write
Alias for channel 11 WRITE_ADDR register
address_offset : 0x2F4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH11_AL3_WRITE_ADDR :
bits : 0 - 31 (32 bit)
access : read-write
Alias for channel 11 TRANS_COUNT register
address_offset : 0x2F8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH11_AL3_TRANS_COUNT :
bits : 0 - 31 (32 bit)
access : read-write
Alias for channel 11 READ_ADDR register
This is a trigger register (0xc). Writing a nonzero value will
reload the channel counter and start the channel.
address_offset : 0x2FC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH11_AL3_READ_ADDR_TRIG :
bits : 0 - 31 (32 bit)
access : read-write
Alias for channel 0 CTRL register
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH0_AL3_CTRL :
bits : 0 - 31 (32 bit)
access : read-write
DMA Channel 12 Read Address pointer
address_offset : 0x300 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH12_READ_ADDR : This register updates automatically each time a read completes. The current value is the next address to be read by this channel.
bits : 0 - 31 (32 bit)
access : read-write
DMA Channel 12 Write Address pointer
address_offset : 0x304 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH12_WRITE_ADDR : This register updates automatically each time a write completes. The current value is the next address to be written by this channel.
bits : 0 - 31 (32 bit)
access : read-write
DMA Channel 12 Transfer Count
address_offset : 0x308 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
COUNT : 28-bit transfer count (256 million transfers maximum).
Program the number of bus transfers a channel will perform before halting. Note that, if transfers are larger than one byte in size, this is not equal to the number of bytes transferred (see CTRL_DATA_SIZE).
When the channel is active, reading this register shows the number of transfers remaining, updating automatically each time a write transfer completes.
Writing this register sets the RELOAD value for the transfer counter. Each time this channel is triggered, the RELOAD value is copied into the live transfer counter. The channel can be started multiple times, and will perform the same number of transfers each time, as programmed by most recent write.
The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a trigger, the written value is used immediately as the length of the new transfer sequence, as well as being written to RELOAD.
bits : 0 - 27 (28 bit)
access : read-write
MODE : When MODE is 0x0, the transfer count decrements with each transfer until 0, and then the channel triggers the next channel indicated by CTRL_CHAIN_TO.
When MODE is 0x1, the transfer count decrements with each transfer until 0, and then the channel re-triggers itself, in addition to the trigger indicated by CTRL_CHAIN_TO. This is useful for e.g. an endless ring-buffer DMA with periodic interrupts.
When MODE is 0xf, the transfer count does not decrement. The DMA channel performs an endless sequence of transfers, never triggering other channels or raising interrupts, until an ABORT is raised.
All other values are reserved.
bits : 28 - 31 (4 bit)
access : read-write
Enumeration:
0 : NORMAL
1 : TRIGGER_SELF
15 : ENDLESS
End of enumeration elements list.
DMA Channel 12 Control and Status
address_offset : 0x30C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : DMA Channel Enable.
When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high)
bits : 0 - 0 (1 bit)
access : read-write
HIGH_PRIORITY : HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels.
This only affects the order in which the DMA schedules channels. The DMA's bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput.
bits : 1 - 1 (1 bit)
access : read-write
DATA_SIZE : Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer.
bits : 2 - 3 (2 bit)
access : read-write
Enumeration:
0 : SIZE_BYTE
1 : SIZE_HALFWORD
2 : SIZE_WORD
End of enumeration elements list.
INCR_READ : If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address.
Generally this should be disabled for peripheral-to-memory transfers.
bits : 4 - 4 (1 bit)
access : read-write
INCR_READ_REV : If 1, and INCR_READ is 1, the read address is decremented rather than incremented with each transfer.
If 1, and INCR_READ is 0, this otherwise-unused combination causes the read address to be incremented by twice the transfer size, i.e. skipping over alternate addresses.
bits : 5 - 5 (1 bit)
access : read-write
INCR_WRITE : If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address.
Generally this should be disabled for memory-to-peripheral transfers.
bits : 6 - 6 (1 bit)
access : read-write
INCR_WRITE_REV : If 1, and INCR_WRITE is 1, the write address is decremented rather than incremented with each transfer.
If 1, and INCR_WRITE is 0, this otherwise-unused combination causes the write address to be incremented by twice the transfer size, i.e. skipping over alternate addresses.
bits : 7 - 7 (1 bit)
access : read-write
RING_SIZE : Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned ring buffers.
Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL.
bits : 8 - 11 (4 bit)
access : read-write
Enumeration:
0 : RING_NONE
End of enumeration elements list.
RING_SEL : Select whether RING_SIZE applies to read or write addresses.
If 0, read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, write addresses are wrapped.
bits : 12 - 12 (1 bit)
access : read-write
CHAIN_TO : When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_.
Note this field resets to 0, so channels 1 and above will chain to channel 0 by default. Set this field to avoid this behaviour.
bits : 13 - 16 (4 bit)
access : read-write
TREQ_SEL : Select a Transfer Request signal.
The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system).
0x0 to 0x3a -> select DREQ n as TREQ
bits : 17 - 22 (6 bit)
access : read-write
Enumeration:
0 : PIO0_TX0
Select PIO0's TX FIFO 0 as TREQ
1 : PIO0_TX1
Select PIO0's TX FIFO 1 as TREQ
2 : PIO0_TX2
Select PIO0's TX FIFO 2 as TREQ
3 : PIO0_TX3
Select PIO0's TX FIFO 3 as TREQ
4 : PIO0_RX0
Select PIO0's RX FIFO 0 as TREQ
5 : PIO0_RX1
Select PIO0's RX FIFO 1 as TREQ
6 : PIO0_RX2
Select PIO0's RX FIFO 2 as TREQ
7 : PIO0_RX3
Select PIO0's RX FIFO 3 as TREQ
8 : PIO1_TX0
Select PIO1's TX FIFO 0 as TREQ
9 : PIO1_TX1
Select PIO1's TX FIFO 1 as TREQ
10 : PIO1_TX2
Select PIO1's TX FIFO 2 as TREQ
11 : PIO1_TX3
Select PIO1's TX FIFO 3 as TREQ
12 : PIO1_RX0
Select PIO1's RX FIFO 0 as TREQ
13 : PIO1_RX1
Select PIO1's RX FIFO 1 as TREQ
14 : PIO1_RX2
Select PIO1's RX FIFO 2 as TREQ
15 : PIO1_RX3
Select PIO1's RX FIFO 3 as TREQ
16 : PIO2_TX0
Select PIO2's TX FIFO 0 as TREQ
17 : PIO2_TX1
Select PIO2's TX FIFO 1 as TREQ
18 : PIO2_TX2
Select PIO2's TX FIFO 2 as TREQ
19 : PIO2_TX3
Select PIO2's TX FIFO 3 as TREQ
20 : PIO2_RX0
Select PIO2's RX FIFO 0 as TREQ
21 : PIO2_RX1
Select PIO2's RX FIFO 1 as TREQ
22 : PIO2_RX2
Select PIO2's RX FIFO 2 as TREQ
23 : PIO2_RX3
Select PIO2's RX FIFO 3 as TREQ
24 : SPI0_TX
Select SPI0's TX FIFO as TREQ
25 : SPI0_RX
Select SPI0's RX FIFO as TREQ
26 : SPI1_TX
Select SPI1's TX FIFO as TREQ
27 : SPI1_RX
Select SPI1's RX FIFO as TREQ
28 : UART0_TX
Select UART0's TX FIFO as TREQ
29 : UART0_RX
Select UART0's RX FIFO as TREQ
30 : UART1_TX
Select UART1's TX FIFO as TREQ
31 : UART1_RX
Select UART1's RX FIFO as TREQ
32 : PWM_WRAP0
Select PWM Counter 0's Wrap Value as TREQ
33 : PWM_WRAP1
Select PWM Counter 1's Wrap Value as TREQ
34 : PWM_WRAP2
Select PWM Counter 2's Wrap Value as TREQ
35 : PWM_WRAP3
Select PWM Counter 3's Wrap Value as TREQ
36 : PWM_WRAP4
Select PWM Counter 4's Wrap Value as TREQ
37 : PWM_WRAP5
Select PWM Counter 5's Wrap Value as TREQ
38 : PWM_WRAP6
Select PWM Counter 6's Wrap Value as TREQ
39 : PWM_WRAP7
Select PWM Counter 7's Wrap Value as TREQ
40 : PWM_WRAP8
Select PWM Counter 8's Wrap Value as TREQ
41 : PWM_WRAP9
Select PWM Counter 9's Wrap Value as TREQ
42 : PWM_WRAP10
Select PWM Counter 0's Wrap Value as TREQ
43 : PWM_WRAP11
Select PWM Counter 1's Wrap Value as TREQ
44 : I2C0_TX
Select I2C0's TX FIFO as TREQ
45 : I2C0_RX
Select I2C0's RX FIFO as TREQ
46 : I2C1_TX
Select I2C1's TX FIFO as TREQ
47 : I2C1_RX
Select I2C1's RX FIFO as TREQ
48 : ADC
Select the ADC as TREQ
49 : XIP_STREAM
Select the XIP Streaming FIFO as TREQ
50 : XIP_QMITX
Select XIP_QMITX as TREQ
51 : XIP_QMIRX
Select XIP_QMIRX as TREQ
52 : HSTX
Select HSTX as TREQ
53 : CORESIGHT
Select CORESIGHT as TREQ
54 : SHA256
Select SHA256 as TREQ
59 : TIMER0
Select Timer 0 as TREQ
60 : TIMER1
Select Timer 1 as TREQ
61 : TIMER2
Select Timer 2 as TREQ (Optional)
62 : TIMER3
Select Timer 3 as TREQ (Optional)
63 : PERMANENT
Permanent request, for unpaced transfers.
End of enumeration elements list.
IRQ_QUIET : In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain.
This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks.
bits : 23 - 23 (1 bit)
access : read-write
BSWAP : Apply byte-swap transformation to DMA data.
For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order.
bits : 24 - 24 (1 bit)
access : read-write
SNIFF_EN : If 1, this channel's data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected.
This allows checksum to be enabled or disabled on a per-control- block basis.
bits : 25 - 25 (1 bit)
access : read-write
BUSY : This flag goes high when the channel starts a new transfer sequence, and low when the last transfer of that sequence completes. Clearing EN while BUSY is high pauses the channel, and BUSY will stay high while paused.
To terminate a sequence early (and clear the BUSY flag), see CHAN_ABORT.
bits : 26 - 26 (1 bit)
access : read-only
WRITE_ERROR : If 1, the channel received a write bus error. Write one to clear.
WRITE_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 5 transfers later)
bits : 29 - 29 (1 bit)
access : read-write
READ_ERROR : If 1, the channel received a read bus error. Write one to clear.
READ_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 3 transfers later)
bits : 30 - 30 (1 bit)
access : read-write
AHB_ERROR : Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel halts when it encounters any bus error, and always raises its channel IRQ flag.
bits : 31 - 31 (1 bit)
access : read-only
Alias for channel 12 CTRL register
address_offset : 0x310 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH12_AL1_CTRL :
bits : 0 - 31 (32 bit)
access : read-write
Alias for channel 12 READ_ADDR register
address_offset : 0x314 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH12_AL1_READ_ADDR :
bits : 0 - 31 (32 bit)
access : read-write
Alias for channel 12 WRITE_ADDR register
address_offset : 0x318 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH12_AL1_WRITE_ADDR :
bits : 0 - 31 (32 bit)
access : read-write
Alias for channel 12 TRANS_COUNT register
This is a trigger register (0xc). Writing a nonzero value will
reload the channel counter and start the channel.
address_offset : 0x31C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH12_AL1_TRANS_COUNT_TRIG :
bits : 0 - 31 (32 bit)
access : read-write
Alias for channel 12 CTRL register
address_offset : 0x320 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH12_AL2_CTRL :
bits : 0 - 31 (32 bit)
access : read-write
Alias for channel 12 TRANS_COUNT register
address_offset : 0x324 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH12_AL2_TRANS_COUNT :
bits : 0 - 31 (32 bit)
access : read-write
Alias for channel 12 READ_ADDR register
address_offset : 0x328 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH12_AL2_READ_ADDR :
bits : 0 - 31 (32 bit)
access : read-write
Alias for channel 12 WRITE_ADDR register
This is a trigger register (0xc). Writing a nonzero value will
reload the channel counter and start the channel.
address_offset : 0x32C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH12_AL2_WRITE_ADDR_TRIG :
bits : 0 - 31 (32 bit)
access : read-write
Alias for channel 12 CTRL register
address_offset : 0x330 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH12_AL3_CTRL :
bits : 0 - 31 (32 bit)
access : read-write
Alias for channel 12 WRITE_ADDR register
address_offset : 0x334 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH12_AL3_WRITE_ADDR :
bits : 0 - 31 (32 bit)
access : read-write
Alias for channel 12 TRANS_COUNT register
address_offset : 0x338 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH12_AL3_TRANS_COUNT :
bits : 0 - 31 (32 bit)
access : read-write
Alias for channel 12 READ_ADDR register
This is a trigger register (0xc). Writing a nonzero value will
reload the channel counter and start the channel.
address_offset : 0x33C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH12_AL3_READ_ADDR_TRIG :
bits : 0 - 31 (32 bit)
access : read-write
Alias for channel 0 WRITE_ADDR register
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH0_AL3_WRITE_ADDR :
bits : 0 - 31 (32 bit)
access : read-write
DMA Channel 13 Read Address pointer
address_offset : 0x340 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH13_READ_ADDR : This register updates automatically each time a read completes. The current value is the next address to be read by this channel.
bits : 0 - 31 (32 bit)
access : read-write
DMA Channel 13 Write Address pointer
address_offset : 0x344 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH13_WRITE_ADDR : This register updates automatically each time a write completes. The current value is the next address to be written by this channel.
bits : 0 - 31 (32 bit)
access : read-write
DMA Channel 13 Transfer Count
address_offset : 0x348 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
COUNT : 28-bit transfer count (256 million transfers maximum).
Program the number of bus transfers a channel will perform before halting. Note that, if transfers are larger than one byte in size, this is not equal to the number of bytes transferred (see CTRL_DATA_SIZE).
When the channel is active, reading this register shows the number of transfers remaining, updating automatically each time a write transfer completes.
Writing this register sets the RELOAD value for the transfer counter. Each time this channel is triggered, the RELOAD value is copied into the live transfer counter. The channel can be started multiple times, and will perform the same number of transfers each time, as programmed by most recent write.
The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a trigger, the written value is used immediately as the length of the new transfer sequence, as well as being written to RELOAD.
bits : 0 - 27 (28 bit)
access : read-write
MODE : When MODE is 0x0, the transfer count decrements with each transfer until 0, and then the channel triggers the next channel indicated by CTRL_CHAIN_TO.
When MODE is 0x1, the transfer count decrements with each transfer until 0, and then the channel re-triggers itself, in addition to the trigger indicated by CTRL_CHAIN_TO. This is useful for e.g. an endless ring-buffer DMA with periodic interrupts.
When MODE is 0xf, the transfer count does not decrement. The DMA channel performs an endless sequence of transfers, never triggering other channels or raising interrupts, until an ABORT is raised.
All other values are reserved.
bits : 28 - 31 (4 bit)
access : read-write
Enumeration:
0 : NORMAL
1 : TRIGGER_SELF
15 : ENDLESS
End of enumeration elements list.
DMA Channel 13 Control and Status
address_offset : 0x34C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : DMA Channel Enable.
When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high)
bits : 0 - 0 (1 bit)
access : read-write
HIGH_PRIORITY : HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels.
This only affects the order in which the DMA schedules channels. The DMA's bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput.
bits : 1 - 1 (1 bit)
access : read-write
DATA_SIZE : Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer.
bits : 2 - 3 (2 bit)
access : read-write
Enumeration:
0 : SIZE_BYTE
1 : SIZE_HALFWORD
2 : SIZE_WORD
End of enumeration elements list.
INCR_READ : If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address.
Generally this should be disabled for peripheral-to-memory transfers.
bits : 4 - 4 (1 bit)
access : read-write
INCR_READ_REV : If 1, and INCR_READ is 1, the read address is decremented rather than incremented with each transfer.
If 1, and INCR_READ is 0, this otherwise-unused combination causes the read address to be incremented by twice the transfer size, i.e. skipping over alternate addresses.
bits : 5 - 5 (1 bit)
access : read-write
INCR_WRITE : If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address.
Generally this should be disabled for memory-to-peripheral transfers.
bits : 6 - 6 (1 bit)
access : read-write
INCR_WRITE_REV : If 1, and INCR_WRITE is 1, the write address is decremented rather than incremented with each transfer.
If 1, and INCR_WRITE is 0, this otherwise-unused combination causes the write address to be incremented by twice the transfer size, i.e. skipping over alternate addresses.
bits : 7 - 7 (1 bit)
access : read-write
RING_SIZE : Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned ring buffers.
Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL.
bits : 8 - 11 (4 bit)
access : read-write
Enumeration:
0 : RING_NONE
End of enumeration elements list.
RING_SEL : Select whether RING_SIZE applies to read or write addresses.
If 0, read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, write addresses are wrapped.
bits : 12 - 12 (1 bit)
access : read-write
CHAIN_TO : When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_.
Note this field resets to 0, so channels 1 and above will chain to channel 0 by default. Set this field to avoid this behaviour.
bits : 13 - 16 (4 bit)
access : read-write
TREQ_SEL : Select a Transfer Request signal.
The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system).
0x0 to 0x3a -> select DREQ n as TREQ
bits : 17 - 22 (6 bit)
access : read-write
Enumeration:
0 : PIO0_TX0
Select PIO0's TX FIFO 0 as TREQ
1 : PIO0_TX1
Select PIO0's TX FIFO 1 as TREQ
2 : PIO0_TX2
Select PIO0's TX FIFO 2 as TREQ
3 : PIO0_TX3
Select PIO0's TX FIFO 3 as TREQ
4 : PIO0_RX0
Select PIO0's RX FIFO 0 as TREQ
5 : PIO0_RX1
Select PIO0's RX FIFO 1 as TREQ
6 : PIO0_RX2
Select PIO0's RX FIFO 2 as TREQ
7 : PIO0_RX3
Select PIO0's RX FIFO 3 as TREQ
8 : PIO1_TX0
Select PIO1's TX FIFO 0 as TREQ
9 : PIO1_TX1
Select PIO1's TX FIFO 1 as TREQ
10 : PIO1_TX2
Select PIO1's TX FIFO 2 as TREQ
11 : PIO1_TX3
Select PIO1's TX FIFO 3 as TREQ
12 : PIO1_RX0
Select PIO1's RX FIFO 0 as TREQ
13 : PIO1_RX1
Select PIO1's RX FIFO 1 as TREQ
14 : PIO1_RX2
Select PIO1's RX FIFO 2 as TREQ
15 : PIO1_RX3
Select PIO1's RX FIFO 3 as TREQ
16 : PIO2_TX0
Select PIO2's TX FIFO 0 as TREQ
17 : PIO2_TX1
Select PIO2's TX FIFO 1 as TREQ
18 : PIO2_TX2
Select PIO2's TX FIFO 2 as TREQ
19 : PIO2_TX3
Select PIO2's TX FIFO 3 as TREQ
20 : PIO2_RX0
Select PIO2's RX FIFO 0 as TREQ
21 : PIO2_RX1
Select PIO2's RX FIFO 1 as TREQ
22 : PIO2_RX2
Select PIO2's RX FIFO 2 as TREQ
23 : PIO2_RX3
Select PIO2's RX FIFO 3 as TREQ
24 : SPI0_TX
Select SPI0's TX FIFO as TREQ
25 : SPI0_RX
Select SPI0's RX FIFO as TREQ
26 : SPI1_TX
Select SPI1's TX FIFO as TREQ
27 : SPI1_RX
Select SPI1's RX FIFO as TREQ
28 : UART0_TX
Select UART0's TX FIFO as TREQ
29 : UART0_RX
Select UART0's RX FIFO as TREQ
30 : UART1_TX
Select UART1's TX FIFO as TREQ
31 : UART1_RX
Select UART1's RX FIFO as TREQ
32 : PWM_WRAP0
Select PWM Counter 0's Wrap Value as TREQ
33 : PWM_WRAP1
Select PWM Counter 1's Wrap Value as TREQ
34 : PWM_WRAP2
Select PWM Counter 2's Wrap Value as TREQ
35 : PWM_WRAP3
Select PWM Counter 3's Wrap Value as TREQ
36 : PWM_WRAP4
Select PWM Counter 4's Wrap Value as TREQ
37 : PWM_WRAP5
Select PWM Counter 5's Wrap Value as TREQ
38 : PWM_WRAP6
Select PWM Counter 6's Wrap Value as TREQ
39 : PWM_WRAP7
Select PWM Counter 7's Wrap Value as TREQ
40 : PWM_WRAP8
Select PWM Counter 8's Wrap Value as TREQ
41 : PWM_WRAP9
Select PWM Counter 9's Wrap Value as TREQ
42 : PWM_WRAP10
Select PWM Counter 0's Wrap Value as TREQ
43 : PWM_WRAP11
Select PWM Counter 1's Wrap Value as TREQ
44 : I2C0_TX
Select I2C0's TX FIFO as TREQ
45 : I2C0_RX
Select I2C0's RX FIFO as TREQ
46 : I2C1_TX
Select I2C1's TX FIFO as TREQ
47 : I2C1_RX
Select I2C1's RX FIFO as TREQ
48 : ADC
Select the ADC as TREQ
49 : XIP_STREAM
Select the XIP Streaming FIFO as TREQ
50 : XIP_QMITX
Select XIP_QMITX as TREQ
51 : XIP_QMIRX
Select XIP_QMIRX as TREQ
52 : HSTX
Select HSTX as TREQ
53 : CORESIGHT
Select CORESIGHT as TREQ
54 : SHA256
Select SHA256 as TREQ
59 : TIMER0
Select Timer 0 as TREQ
60 : TIMER1
Select Timer 1 as TREQ
61 : TIMER2
Select Timer 2 as TREQ (Optional)
62 : TIMER3
Select Timer 3 as TREQ (Optional)
63 : PERMANENT
Permanent request, for unpaced transfers.
End of enumeration elements list.
IRQ_QUIET : In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain.
This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks.
bits : 23 - 23 (1 bit)
access : read-write
BSWAP : Apply byte-swap transformation to DMA data.
For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order.
bits : 24 - 24 (1 bit)
access : read-write
SNIFF_EN : If 1, this channel's data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected.
This allows checksum to be enabled or disabled on a per-control- block basis.
bits : 25 - 25 (1 bit)
access : read-write
BUSY : This flag goes high when the channel starts a new transfer sequence, and low when the last transfer of that sequence completes. Clearing EN while BUSY is high pauses the channel, and BUSY will stay high while paused.
To terminate a sequence early (and clear the BUSY flag), see CHAN_ABORT.
bits : 26 - 26 (1 bit)
access : read-only
WRITE_ERROR : If 1, the channel received a write bus error. Write one to clear.
WRITE_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 5 transfers later)
bits : 29 - 29 (1 bit)
access : read-write
READ_ERROR : If 1, the channel received a read bus error. Write one to clear.
READ_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 3 transfers later)
bits : 30 - 30 (1 bit)
access : read-write
AHB_ERROR : Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel halts when it encounters any bus error, and always raises its channel IRQ flag.
bits : 31 - 31 (1 bit)
access : read-only
Alias for channel 13 CTRL register
address_offset : 0x350 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH13_AL1_CTRL :
bits : 0 - 31 (32 bit)
access : read-write
Alias for channel 13 READ_ADDR register
address_offset : 0x354 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH13_AL1_READ_ADDR :
bits : 0 - 31 (32 bit)
access : read-write
Alias for channel 13 WRITE_ADDR register
address_offset : 0x358 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH13_AL1_WRITE_ADDR :
bits : 0 - 31 (32 bit)
access : read-write
Alias for channel 13 TRANS_COUNT register
This is a trigger register (0xc). Writing a nonzero value will
reload the channel counter and start the channel.
address_offset : 0x35C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH13_AL1_TRANS_COUNT_TRIG :
bits : 0 - 31 (32 bit)
access : read-write
Alias for channel 13 CTRL register
address_offset : 0x360 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH13_AL2_CTRL :
bits : 0 - 31 (32 bit)
access : read-write
Alias for channel 13 TRANS_COUNT register
address_offset : 0x364 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH13_AL2_TRANS_COUNT :
bits : 0 - 31 (32 bit)
access : read-write
Alias for channel 13 READ_ADDR register
address_offset : 0x368 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH13_AL2_READ_ADDR :
bits : 0 - 31 (32 bit)
access : read-write
Alias for channel 13 WRITE_ADDR register
This is a trigger register (0xc). Writing a nonzero value will
reload the channel counter and start the channel.
address_offset : 0x36C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH13_AL2_WRITE_ADDR_TRIG :
bits : 0 - 31 (32 bit)
access : read-write
Alias for channel 13 CTRL register
address_offset : 0x370 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH13_AL3_CTRL :
bits : 0 - 31 (32 bit)
access : read-write
Alias for channel 13 WRITE_ADDR register
address_offset : 0x374 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH13_AL3_WRITE_ADDR :
bits : 0 - 31 (32 bit)
access : read-write
Alias for channel 13 TRANS_COUNT register
address_offset : 0x378 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH13_AL3_TRANS_COUNT :
bits : 0 - 31 (32 bit)
access : read-write
Alias for channel 13 READ_ADDR register
This is a trigger register (0xc). Writing a nonzero value will
reload the channel counter and start the channel.
address_offset : 0x37C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH13_AL3_READ_ADDR_TRIG :
bits : 0 - 31 (32 bit)
access : read-write
Alias for channel 0 TRANS_COUNT register
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH0_AL3_TRANS_COUNT :
bits : 0 - 31 (32 bit)
access : read-write
DMA Channel 14 Read Address pointer
address_offset : 0x380 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH14_READ_ADDR : This register updates automatically each time a read completes. The current value is the next address to be read by this channel.
bits : 0 - 31 (32 bit)
access : read-write
DMA Channel 14 Write Address pointer
address_offset : 0x384 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH14_WRITE_ADDR : This register updates automatically each time a write completes. The current value is the next address to be written by this channel.
bits : 0 - 31 (32 bit)
access : read-write
DMA Channel 14 Transfer Count
address_offset : 0x388 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
COUNT : 28-bit transfer count (256 million transfers maximum).
Program the number of bus transfers a channel will perform before halting. Note that, if transfers are larger than one byte in size, this is not equal to the number of bytes transferred (see CTRL_DATA_SIZE).
When the channel is active, reading this register shows the number of transfers remaining, updating automatically each time a write transfer completes.
Writing this register sets the RELOAD value for the transfer counter. Each time this channel is triggered, the RELOAD value is copied into the live transfer counter. The channel can be started multiple times, and will perform the same number of transfers each time, as programmed by most recent write.
The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a trigger, the written value is used immediately as the length of the new transfer sequence, as well as being written to RELOAD.
bits : 0 - 27 (28 bit)
access : read-write
MODE : When MODE is 0x0, the transfer count decrements with each transfer until 0, and then the channel triggers the next channel indicated by CTRL_CHAIN_TO.
When MODE is 0x1, the transfer count decrements with each transfer until 0, and then the channel re-triggers itself, in addition to the trigger indicated by CTRL_CHAIN_TO. This is useful for e.g. an endless ring-buffer DMA with periodic interrupts.
When MODE is 0xf, the transfer count does not decrement. The DMA channel performs an endless sequence of transfers, never triggering other channels or raising interrupts, until an ABORT is raised.
All other values are reserved.
bits : 28 - 31 (4 bit)
access : read-write
Enumeration:
0 : NORMAL
1 : TRIGGER_SELF
15 : ENDLESS
End of enumeration elements list.
DMA Channel 14 Control and Status
address_offset : 0x38C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : DMA Channel Enable.
When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high)
bits : 0 - 0 (1 bit)
access : read-write
HIGH_PRIORITY : HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels.
This only affects the order in which the DMA schedules channels. The DMA's bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput.
bits : 1 - 1 (1 bit)
access : read-write
DATA_SIZE : Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer.
bits : 2 - 3 (2 bit)
access : read-write
Enumeration:
0 : SIZE_BYTE
1 : SIZE_HALFWORD
2 : SIZE_WORD
End of enumeration elements list.
INCR_READ : If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address.
Generally this should be disabled for peripheral-to-memory transfers.
bits : 4 - 4 (1 bit)
access : read-write
INCR_READ_REV : If 1, and INCR_READ is 1, the read address is decremented rather than incremented with each transfer.
If 1, and INCR_READ is 0, this otherwise-unused combination causes the read address to be incremented by twice the transfer size, i.e. skipping over alternate addresses.
bits : 5 - 5 (1 bit)
access : read-write
INCR_WRITE : If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address.
Generally this should be disabled for memory-to-peripheral transfers.
bits : 6 - 6 (1 bit)
access : read-write
INCR_WRITE_REV : If 1, and INCR_WRITE is 1, the write address is decremented rather than incremented with each transfer.
If 1, and INCR_WRITE is 0, this otherwise-unused combination causes the write address to be incremented by twice the transfer size, i.e. skipping over alternate addresses.
bits : 7 - 7 (1 bit)
access : read-write
RING_SIZE : Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned ring buffers.
Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL.
bits : 8 - 11 (4 bit)
access : read-write
Enumeration:
0 : RING_NONE
End of enumeration elements list.
RING_SEL : Select whether RING_SIZE applies to read or write addresses.
If 0, read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, write addresses are wrapped.
bits : 12 - 12 (1 bit)
access : read-write
CHAIN_TO : When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_.
Note this field resets to 0, so channels 1 and above will chain to channel 0 by default. Set this field to avoid this behaviour.
bits : 13 - 16 (4 bit)
access : read-write
TREQ_SEL : Select a Transfer Request signal.
The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system).
0x0 to 0x3a -> select DREQ n as TREQ
bits : 17 - 22 (6 bit)
access : read-write
Enumeration:
0 : PIO0_TX0
Select PIO0's TX FIFO 0 as TREQ
1 : PIO0_TX1
Select PIO0's TX FIFO 1 as TREQ
2 : PIO0_TX2
Select PIO0's TX FIFO 2 as TREQ
3 : PIO0_TX3
Select PIO0's TX FIFO 3 as TREQ
4 : PIO0_RX0
Select PIO0's RX FIFO 0 as TREQ
5 : PIO0_RX1
Select PIO0's RX FIFO 1 as TREQ
6 : PIO0_RX2
Select PIO0's RX FIFO 2 as TREQ
7 : PIO0_RX3
Select PIO0's RX FIFO 3 as TREQ
8 : PIO1_TX0
Select PIO1's TX FIFO 0 as TREQ
9 : PIO1_TX1
Select PIO1's TX FIFO 1 as TREQ
10 : PIO1_TX2
Select PIO1's TX FIFO 2 as TREQ
11 : PIO1_TX3
Select PIO1's TX FIFO 3 as TREQ
12 : PIO1_RX0
Select PIO1's RX FIFO 0 as TREQ
13 : PIO1_RX1
Select PIO1's RX FIFO 1 as TREQ
14 : PIO1_RX2
Select PIO1's RX FIFO 2 as TREQ
15 : PIO1_RX3
Select PIO1's RX FIFO 3 as TREQ
16 : PIO2_TX0
Select PIO2's TX FIFO 0 as TREQ
17 : PIO2_TX1
Select PIO2's TX FIFO 1 as TREQ
18 : PIO2_TX2
Select PIO2's TX FIFO 2 as TREQ
19 : PIO2_TX3
Select PIO2's TX FIFO 3 as TREQ
20 : PIO2_RX0
Select PIO2's RX FIFO 0 as TREQ
21 : PIO2_RX1
Select PIO2's RX FIFO 1 as TREQ
22 : PIO2_RX2
Select PIO2's RX FIFO 2 as TREQ
23 : PIO2_RX3
Select PIO2's RX FIFO 3 as TREQ
24 : SPI0_TX
Select SPI0's TX FIFO as TREQ
25 : SPI0_RX
Select SPI0's RX FIFO as TREQ
26 : SPI1_TX
Select SPI1's TX FIFO as TREQ
27 : SPI1_RX
Select SPI1's RX FIFO as TREQ
28 : UART0_TX
Select UART0's TX FIFO as TREQ
29 : UART0_RX
Select UART0's RX FIFO as TREQ
30 : UART1_TX
Select UART1's TX FIFO as TREQ
31 : UART1_RX
Select UART1's RX FIFO as TREQ
32 : PWM_WRAP0
Select PWM Counter 0's Wrap Value as TREQ
33 : PWM_WRAP1
Select PWM Counter 1's Wrap Value as TREQ
34 : PWM_WRAP2
Select PWM Counter 2's Wrap Value as TREQ
35 : PWM_WRAP3
Select PWM Counter 3's Wrap Value as TREQ
36 : PWM_WRAP4
Select PWM Counter 4's Wrap Value as TREQ
37 : PWM_WRAP5
Select PWM Counter 5's Wrap Value as TREQ
38 : PWM_WRAP6
Select PWM Counter 6's Wrap Value as TREQ
39 : PWM_WRAP7
Select PWM Counter 7's Wrap Value as TREQ
40 : PWM_WRAP8
Select PWM Counter 8's Wrap Value as TREQ
41 : PWM_WRAP9
Select PWM Counter 9's Wrap Value as TREQ
42 : PWM_WRAP10
Select PWM Counter 0's Wrap Value as TREQ
43 : PWM_WRAP11
Select PWM Counter 1's Wrap Value as TREQ
44 : I2C0_TX
Select I2C0's TX FIFO as TREQ
45 : I2C0_RX
Select I2C0's RX FIFO as TREQ
46 : I2C1_TX
Select I2C1's TX FIFO as TREQ
47 : I2C1_RX
Select I2C1's RX FIFO as TREQ
48 : ADC
Select the ADC as TREQ
49 : XIP_STREAM
Select the XIP Streaming FIFO as TREQ
50 : XIP_QMITX
Select XIP_QMITX as TREQ
51 : XIP_QMIRX
Select XIP_QMIRX as TREQ
52 : HSTX
Select HSTX as TREQ
53 : CORESIGHT
Select CORESIGHT as TREQ
54 : SHA256
Select SHA256 as TREQ
59 : TIMER0
Select Timer 0 as TREQ
60 : TIMER1
Select Timer 1 as TREQ
61 : TIMER2
Select Timer 2 as TREQ (Optional)
62 : TIMER3
Select Timer 3 as TREQ (Optional)
63 : PERMANENT
Permanent request, for unpaced transfers.
End of enumeration elements list.
IRQ_QUIET : In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain.
This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks.
bits : 23 - 23 (1 bit)
access : read-write
BSWAP : Apply byte-swap transformation to DMA data.
For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order.
bits : 24 - 24 (1 bit)
access : read-write
SNIFF_EN : If 1, this channel's data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected.
This allows checksum to be enabled or disabled on a per-control- block basis.
bits : 25 - 25 (1 bit)
access : read-write
BUSY : This flag goes high when the channel starts a new transfer sequence, and low when the last transfer of that sequence completes. Clearing EN while BUSY is high pauses the channel, and BUSY will stay high while paused.
To terminate a sequence early (and clear the BUSY flag), see CHAN_ABORT.
bits : 26 - 26 (1 bit)
access : read-only
WRITE_ERROR : If 1, the channel received a write bus error. Write one to clear.
WRITE_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 5 transfers later)
bits : 29 - 29 (1 bit)
access : read-write
READ_ERROR : If 1, the channel received a read bus error. Write one to clear.
READ_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 3 transfers later)
bits : 30 - 30 (1 bit)
access : read-write
AHB_ERROR : Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel halts when it encounters any bus error, and always raises its channel IRQ flag.
bits : 31 - 31 (1 bit)
access : read-only
Alias for channel 14 CTRL register
address_offset : 0x390 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH14_AL1_CTRL :
bits : 0 - 31 (32 bit)
access : read-write
Alias for channel 14 READ_ADDR register
address_offset : 0x394 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH14_AL1_READ_ADDR :
bits : 0 - 31 (32 bit)
access : read-write
Alias for channel 14 WRITE_ADDR register
address_offset : 0x398 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH14_AL1_WRITE_ADDR :
bits : 0 - 31 (32 bit)
access : read-write
Alias for channel 14 TRANS_COUNT register
This is a trigger register (0xc). Writing a nonzero value will
reload the channel counter and start the channel.
address_offset : 0x39C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH14_AL1_TRANS_COUNT_TRIG :
bits : 0 - 31 (32 bit)
access : read-write
Alias for channel 14 CTRL register
address_offset : 0x3A0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH14_AL2_CTRL :
bits : 0 - 31 (32 bit)
access : read-write
Alias for channel 14 TRANS_COUNT register
address_offset : 0x3A4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH14_AL2_TRANS_COUNT :
bits : 0 - 31 (32 bit)
access : read-write
Alias for channel 14 READ_ADDR register
address_offset : 0x3A8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH14_AL2_READ_ADDR :
bits : 0 - 31 (32 bit)
access : read-write
Alias for channel 14 WRITE_ADDR register
This is a trigger register (0xc). Writing a nonzero value will
reload the channel counter and start the channel.
address_offset : 0x3AC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH14_AL2_WRITE_ADDR_TRIG :
bits : 0 - 31 (32 bit)
access : read-write
Alias for channel 14 CTRL register
address_offset : 0x3B0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH14_AL3_CTRL :
bits : 0 - 31 (32 bit)
access : read-write
Alias for channel 14 WRITE_ADDR register
address_offset : 0x3B4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH14_AL3_WRITE_ADDR :
bits : 0 - 31 (32 bit)
access : read-write
Alias for channel 14 TRANS_COUNT register
address_offset : 0x3B8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH14_AL3_TRANS_COUNT :
bits : 0 - 31 (32 bit)
access : read-write
Alias for channel 14 READ_ADDR register
This is a trigger register (0xc). Writing a nonzero value will
reload the channel counter and start the channel.
address_offset : 0x3BC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH14_AL3_READ_ADDR_TRIG :
bits : 0 - 31 (32 bit)
access : read-write
Alias for channel 0 READ_ADDR register
This is a trigger register (0xc). Writing a nonzero value will
reload the channel counter and start the channel.
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH0_AL3_READ_ADDR_TRIG :
bits : 0 - 31 (32 bit)
access : read-write
DMA Channel 15 Read Address pointer
address_offset : 0x3C0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH15_READ_ADDR : This register updates automatically each time a read completes. The current value is the next address to be read by this channel.
bits : 0 - 31 (32 bit)
access : read-write
DMA Channel 15 Write Address pointer
address_offset : 0x3C4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH15_WRITE_ADDR : This register updates automatically each time a write completes. The current value is the next address to be written by this channel.
bits : 0 - 31 (32 bit)
access : read-write
DMA Channel 15 Transfer Count
address_offset : 0x3C8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
COUNT : 28-bit transfer count (256 million transfers maximum).
Program the number of bus transfers a channel will perform before halting. Note that, if transfers are larger than one byte in size, this is not equal to the number of bytes transferred (see CTRL_DATA_SIZE).
When the channel is active, reading this register shows the number of transfers remaining, updating automatically each time a write transfer completes.
Writing this register sets the RELOAD value for the transfer counter. Each time this channel is triggered, the RELOAD value is copied into the live transfer counter. The channel can be started multiple times, and will perform the same number of transfers each time, as programmed by most recent write.
The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a trigger, the written value is used immediately as the length of the new transfer sequence, as well as being written to RELOAD.
bits : 0 - 27 (28 bit)
access : read-write
MODE : When MODE is 0x0, the transfer count decrements with each transfer until 0, and then the channel triggers the next channel indicated by CTRL_CHAIN_TO.
When MODE is 0x1, the transfer count decrements with each transfer until 0, and then the channel re-triggers itself, in addition to the trigger indicated by CTRL_CHAIN_TO. This is useful for e.g. an endless ring-buffer DMA with periodic interrupts.
When MODE is 0xf, the transfer count does not decrement. The DMA channel performs an endless sequence of transfers, never triggering other channels or raising interrupts, until an ABORT is raised.
All other values are reserved.
bits : 28 - 31 (4 bit)
access : read-write
Enumeration:
0 : NORMAL
1 : TRIGGER_SELF
15 : ENDLESS
End of enumeration elements list.
DMA Channel 15 Control and Status
address_offset : 0x3CC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : DMA Channel Enable.
When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high)
bits : 0 - 0 (1 bit)
access : read-write
HIGH_PRIORITY : HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels.
This only affects the order in which the DMA schedules channels. The DMA's bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput.
bits : 1 - 1 (1 bit)
access : read-write
DATA_SIZE : Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer.
bits : 2 - 3 (2 bit)
access : read-write
Enumeration:
0 : SIZE_BYTE
1 : SIZE_HALFWORD
2 : SIZE_WORD
End of enumeration elements list.
INCR_READ : If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address.
Generally this should be disabled for peripheral-to-memory transfers.
bits : 4 - 4 (1 bit)
access : read-write
INCR_READ_REV : If 1, and INCR_READ is 1, the read address is decremented rather than incremented with each transfer.
If 1, and INCR_READ is 0, this otherwise-unused combination causes the read address to be incremented by twice the transfer size, i.e. skipping over alternate addresses.
bits : 5 - 5 (1 bit)
access : read-write
INCR_WRITE : If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address.
Generally this should be disabled for memory-to-peripheral transfers.
bits : 6 - 6 (1 bit)
access : read-write
INCR_WRITE_REV : If 1, and INCR_WRITE is 1, the write address is decremented rather than incremented with each transfer.
If 1, and INCR_WRITE is 0, this otherwise-unused combination causes the write address to be incremented by twice the transfer size, i.e. skipping over alternate addresses.
bits : 7 - 7 (1 bit)
access : read-write
RING_SIZE : Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned ring buffers.
Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL.
bits : 8 - 11 (4 bit)
access : read-write
Enumeration:
0 : RING_NONE
End of enumeration elements list.
RING_SEL : Select whether RING_SIZE applies to read or write addresses.
If 0, read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, write addresses are wrapped.
bits : 12 - 12 (1 bit)
access : read-write
CHAIN_TO : When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_.
Note this field resets to 0, so channels 1 and above will chain to channel 0 by default. Set this field to avoid this behaviour.
bits : 13 - 16 (4 bit)
access : read-write
TREQ_SEL : Select a Transfer Request signal.
The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system).
0x0 to 0x3a -> select DREQ n as TREQ
bits : 17 - 22 (6 bit)
access : read-write
Enumeration:
0 : PIO0_TX0
Select PIO0's TX FIFO 0 as TREQ
1 : PIO0_TX1
Select PIO0's TX FIFO 1 as TREQ
2 : PIO0_TX2
Select PIO0's TX FIFO 2 as TREQ
3 : PIO0_TX3
Select PIO0's TX FIFO 3 as TREQ
4 : PIO0_RX0
Select PIO0's RX FIFO 0 as TREQ
5 : PIO0_RX1
Select PIO0's RX FIFO 1 as TREQ
6 : PIO0_RX2
Select PIO0's RX FIFO 2 as TREQ
7 : PIO0_RX3
Select PIO0's RX FIFO 3 as TREQ
8 : PIO1_TX0
Select PIO1's TX FIFO 0 as TREQ
9 : PIO1_TX1
Select PIO1's TX FIFO 1 as TREQ
10 : PIO1_TX2
Select PIO1's TX FIFO 2 as TREQ
11 : PIO1_TX3
Select PIO1's TX FIFO 3 as TREQ
12 : PIO1_RX0
Select PIO1's RX FIFO 0 as TREQ
13 : PIO1_RX1
Select PIO1's RX FIFO 1 as TREQ
14 : PIO1_RX2
Select PIO1's RX FIFO 2 as TREQ
15 : PIO1_RX3
Select PIO1's RX FIFO 3 as TREQ
16 : PIO2_TX0
Select PIO2's TX FIFO 0 as TREQ
17 : PIO2_TX1
Select PIO2's TX FIFO 1 as TREQ
18 : PIO2_TX2
Select PIO2's TX FIFO 2 as TREQ
19 : PIO2_TX3
Select PIO2's TX FIFO 3 as TREQ
20 : PIO2_RX0
Select PIO2's RX FIFO 0 as TREQ
21 : PIO2_RX1
Select PIO2's RX FIFO 1 as TREQ
22 : PIO2_RX2
Select PIO2's RX FIFO 2 as TREQ
23 : PIO2_RX3
Select PIO2's RX FIFO 3 as TREQ
24 : SPI0_TX
Select SPI0's TX FIFO as TREQ
25 : SPI0_RX
Select SPI0's RX FIFO as TREQ
26 : SPI1_TX
Select SPI1's TX FIFO as TREQ
27 : SPI1_RX
Select SPI1's RX FIFO as TREQ
28 : UART0_TX
Select UART0's TX FIFO as TREQ
29 : UART0_RX
Select UART0's RX FIFO as TREQ
30 : UART1_TX
Select UART1's TX FIFO as TREQ
31 : UART1_RX
Select UART1's RX FIFO as TREQ
32 : PWM_WRAP0
Select PWM Counter 0's Wrap Value as TREQ
33 : PWM_WRAP1
Select PWM Counter 1's Wrap Value as TREQ
34 : PWM_WRAP2
Select PWM Counter 2's Wrap Value as TREQ
35 : PWM_WRAP3
Select PWM Counter 3's Wrap Value as TREQ
36 : PWM_WRAP4
Select PWM Counter 4's Wrap Value as TREQ
37 : PWM_WRAP5
Select PWM Counter 5's Wrap Value as TREQ
38 : PWM_WRAP6
Select PWM Counter 6's Wrap Value as TREQ
39 : PWM_WRAP7
Select PWM Counter 7's Wrap Value as TREQ
40 : PWM_WRAP8
Select PWM Counter 8's Wrap Value as TREQ
41 : PWM_WRAP9
Select PWM Counter 9's Wrap Value as TREQ
42 : PWM_WRAP10
Select PWM Counter 0's Wrap Value as TREQ
43 : PWM_WRAP11
Select PWM Counter 1's Wrap Value as TREQ
44 : I2C0_TX
Select I2C0's TX FIFO as TREQ
45 : I2C0_RX
Select I2C0's RX FIFO as TREQ
46 : I2C1_TX
Select I2C1's TX FIFO as TREQ
47 : I2C1_RX
Select I2C1's RX FIFO as TREQ
48 : ADC
Select the ADC as TREQ
49 : XIP_STREAM
Select the XIP Streaming FIFO as TREQ
50 : XIP_QMITX
Select XIP_QMITX as TREQ
51 : XIP_QMIRX
Select XIP_QMIRX as TREQ
52 : HSTX
Select HSTX as TREQ
53 : CORESIGHT
Select CORESIGHT as TREQ
54 : SHA256
Select SHA256 as TREQ
59 : TIMER0
Select Timer 0 as TREQ
60 : TIMER1
Select Timer 1 as TREQ
61 : TIMER2
Select Timer 2 as TREQ (Optional)
62 : TIMER3
Select Timer 3 as TREQ (Optional)
63 : PERMANENT
Permanent request, for unpaced transfers.
End of enumeration elements list.
IRQ_QUIET : In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain.
This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks.
bits : 23 - 23 (1 bit)
access : read-write
BSWAP : Apply byte-swap transformation to DMA data.
For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order.
bits : 24 - 24 (1 bit)
access : read-write
SNIFF_EN : If 1, this channel's data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected.
This allows checksum to be enabled or disabled on a per-control- block basis.
bits : 25 - 25 (1 bit)
access : read-write
BUSY : This flag goes high when the channel starts a new transfer sequence, and low when the last transfer of that sequence completes. Clearing EN while BUSY is high pauses the channel, and BUSY will stay high while paused.
To terminate a sequence early (and clear the BUSY flag), see CHAN_ABORT.
bits : 26 - 26 (1 bit)
access : read-only
WRITE_ERROR : If 1, the channel received a write bus error. Write one to clear.
WRITE_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 5 transfers later)
bits : 29 - 29 (1 bit)
access : read-write
READ_ERROR : If 1, the channel received a read bus error. Write one to clear.
READ_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 3 transfers later)
bits : 30 - 30 (1 bit)
access : read-write
AHB_ERROR : Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel halts when it encounters any bus error, and always raises its channel IRQ flag.
bits : 31 - 31 (1 bit)
access : read-only
Alias for channel 15 CTRL register
address_offset : 0x3D0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH15_AL1_CTRL :
bits : 0 - 31 (32 bit)
access : read-write
Alias for channel 15 READ_ADDR register
address_offset : 0x3D4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH15_AL1_READ_ADDR :
bits : 0 - 31 (32 bit)
access : read-write
Alias for channel 15 WRITE_ADDR register
address_offset : 0x3D8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH15_AL1_WRITE_ADDR :
bits : 0 - 31 (32 bit)
access : read-write
Alias for channel 15 TRANS_COUNT register
This is a trigger register (0xc). Writing a nonzero value will
reload the channel counter and start the channel.
address_offset : 0x3DC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH15_AL1_TRANS_COUNT_TRIG :
bits : 0 - 31 (32 bit)
access : read-write
Alias for channel 15 CTRL register
address_offset : 0x3E0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH15_AL2_CTRL :
bits : 0 - 31 (32 bit)
access : read-write
Alias for channel 15 TRANS_COUNT register
address_offset : 0x3E4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH15_AL2_TRANS_COUNT :
bits : 0 - 31 (32 bit)
access : read-write
Alias for channel 15 READ_ADDR register
address_offset : 0x3E8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH15_AL2_READ_ADDR :
bits : 0 - 31 (32 bit)
access : read-write
Alias for channel 15 WRITE_ADDR register
This is a trigger register (0xc). Writing a nonzero value will
reload the channel counter and start the channel.
address_offset : 0x3EC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH15_AL2_WRITE_ADDR_TRIG :
bits : 0 - 31 (32 bit)
access : read-write
Alias for channel 15 CTRL register
address_offset : 0x3F0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH15_AL3_CTRL :
bits : 0 - 31 (32 bit)
access : read-write
Alias for channel 15 WRITE_ADDR register
address_offset : 0x3F4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH15_AL3_WRITE_ADDR :
bits : 0 - 31 (32 bit)
access : read-write
Alias for channel 15 TRANS_COUNT register
address_offset : 0x3F8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH15_AL3_TRANS_COUNT :
bits : 0 - 31 (32 bit)
access : read-write
Alias for channel 15 READ_ADDR register
This is a trigger register (0xc). Writing a nonzero value will
reload the channel counter and start the channel.
address_offset : 0x3FC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH15_AL3_READ_ADDR_TRIG :
bits : 0 - 31 (32 bit)
access : read-write
DMA Channel 0 Write Address pointer
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH0_WRITE_ADDR : This register updates automatically each time a write completes. The current value is the next address to be written by this channel.
bits : 0 - 31 (32 bit)
access : read-write
DMA Channel 1 Read Address pointer
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH1_READ_ADDR : This register updates automatically each time a read completes. The current value is the next address to be read by this channel.
bits : 0 - 31 (32 bit)
access : read-write
Interrupt Status (raw)
address_offset : 0x400 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INTR : Raw interrupt status for DMA Channels 0..15. Bit n corresponds to channel n. Ignores any masking or forcing. Channel interrupts can be cleared by writing a bit mask to INTR or INTS0/1/2/3.
Channel interrupts can be routed to either of four system-level IRQs based on INTE0, INTE1, INTE2 and INTE3.
The multiple system-level interrupts might be used to allow NVIC IRQ preemption for more time-critical channels, to spread IRQ load across different cores, or to target IRQs to different security domains.
It is also valid to ignore the multiple IRQs, and just use INTE0/INTS0/IRQ 0.
If this register is accessed at a security/privilege level less than that of a given channel (as defined by that channel's SECCFG_CHx register), then that channel's interrupt status will read as 0, ignore writes.
bits : 0 - 15 (16 bit)
access : read-write
Interrupt Enables for IRQ 0
address_offset : 0x404 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INTE0 : Set bit n to pass interrupts from channel n to DMA IRQ 0.
Note this bit has no effect if the channel security/privilege level, defined by SECCFG_CHx, is greater than the IRQ security/privilege defined by SECCFG_IRQ0.
bits : 0 - 15 (16 bit)
access : read-write
Force Interrupts
address_offset : 0x408 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INTF0 : Write 1s to force the corresponding bits in INTS0. The interrupt remains asserted until INTF0 is cleared.
bits : 0 - 15 (16 bit)
access : read-write
Interrupt Status for IRQ 0
address_offset : 0x40C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INTS0 : Indicates active channel interrupt requests which are currently causing IRQ 0 to be asserted.
Channel interrupts can be cleared by writing a bit mask here.
Channels with a security/privilege (SECCFG_CHx) greater SECCFG_IRQ0) read as 0 in this register, and ignore writes.
bits : 0 - 15 (16 bit)
access : read-write
Interrupt Status (raw)
address_offset : 0x410 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INTR1 : Raw interrupt status for DMA Channels 0..15. Bit n corresponds to channel n. Ignores any masking or forcing. Channel interrupts can be cleared by writing a bit mask to INTR or INTS0/1/2/3.
Channel interrupts can be routed to either of four system-level IRQs based on INTE0, INTE1, INTE2 and INTE3.
The multiple system-level interrupts might be used to allow NVIC IRQ preemption for more time-critical channels, to spread IRQ load across different cores, or to target IRQs to different security domains.
It is also valid to ignore the multiple IRQs, and just use INTE0/INTS0/IRQ 0.
If this register is accessed at a security/privilege level less than that of a given channel (as defined by that channel's SECCFG_CHx register), then that channel's interrupt status will read as 0, ignore writes.
bits : 0 - 15 (16 bit)
access : read-write
Interrupt Enables for IRQ 1
address_offset : 0x414 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INTE1 : Set bit n to pass interrupts from channel n to DMA IRQ 1.
Note this bit has no effect if the channel security/privilege level, defined by SECCFG_CHx, is greater than the IRQ security/privilege defined by SECCFG_IRQ1.
bits : 0 - 15 (16 bit)
access : read-write
Force Interrupts
address_offset : 0x418 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INTF1 : Write 1s to force the corresponding bits in INTS1. The interrupt remains asserted until INTF1 is cleared.
bits : 0 - 15 (16 bit)
access : read-write
Interrupt Status for IRQ 1
address_offset : 0x41C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INTS1 : Indicates active channel interrupt requests which are currently causing IRQ 1 to be asserted.
Channel interrupts can be cleared by writing a bit mask here.
Channels with a security/privilege (SECCFG_CHx) greater SECCFG_IRQ1) read as 0 in this register, and ignore writes.
bits : 0 - 15 (16 bit)
access : read-write
Interrupt Status (raw)
address_offset : 0x420 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INTR2 : Raw interrupt status for DMA Channels 0..15. Bit n corresponds to channel n. Ignores any masking or forcing. Channel interrupts can be cleared by writing a bit mask to INTR or INTS0/1/2/3.
Channel interrupts can be routed to either of four system-level IRQs based on INTE0, INTE1, INTE2 and INTE3.
The multiple system-level interrupts might be used to allow NVIC IRQ preemption for more time-critical channels, to spread IRQ load across different cores, or to target IRQs to different security domains.
It is also valid to ignore the multiple IRQs, and just use INTE0/INTS0/IRQ 0.
If this register is accessed at a security/privilege level less than that of a given channel (as defined by that channel's SECCFG_CHx register), then that channel's interrupt status will read as 0, ignore writes.
bits : 0 - 15 (16 bit)
access : read-write
Interrupt Enables for IRQ 2
address_offset : 0x424 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INTE2 : Set bit n to pass interrupts from channel n to DMA IRQ 2.
Note this bit has no effect if the channel security/privilege level, defined by SECCFG_CHx, is greater than the IRQ security/privilege defined by SECCFG_IRQ2.
bits : 0 - 15 (16 bit)
access : read-write
Force Interrupts
address_offset : 0x428 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INTF2 : Write 1s to force the corresponding bits in INTS2. The interrupt remains asserted until INTF2 is cleared.
bits : 0 - 15 (16 bit)
access : read-write
Interrupt Status for IRQ 2
address_offset : 0x42C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INTS2 : Indicates active channel interrupt requests which are currently causing IRQ 2 to be asserted.
Channel interrupts can be cleared by writing a bit mask here.
Channels with a security/privilege (SECCFG_CHx) greater SECCFG_IRQ2) read as 0 in this register, and ignore writes.
bits : 0 - 15 (16 bit)
access : read-write
Interrupt Status (raw)
address_offset : 0x430 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INTR3 : Raw interrupt status for DMA Channels 0..15. Bit n corresponds to channel n. Ignores any masking or forcing. Channel interrupts can be cleared by writing a bit mask to INTR or INTS0/1/2/3.
Channel interrupts can be routed to either of four system-level IRQs based on INTE0, INTE1, INTE2 and INTE3.
The multiple system-level interrupts might be used to allow NVIC IRQ preemption for more time-critical channels, to spread IRQ load across different cores, or to target IRQs to different security domains.
It is also valid to ignore the multiple IRQs, and just use INTE0/INTS0/IRQ 0.
If this register is accessed at a security/privilege level less than that of a given channel (as defined by that channel's SECCFG_CHx register), then that channel's interrupt status will read as 0, ignore writes.
bits : 0 - 15 (16 bit)
access : read-write
Interrupt Enables for IRQ 3
address_offset : 0x434 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INTE3 : Set bit n to pass interrupts from channel n to DMA IRQ 3.
Note this bit has no effect if the channel security/privilege level, defined by SECCFG_CHx, is greater than the IRQ security/privilege defined by SECCFG_IRQ3.
bits : 0 - 15 (16 bit)
access : read-write
Force Interrupts
address_offset : 0x438 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INTF3 : Write 1s to force the corresponding bits in INTS3. The interrupt remains asserted until INTF3 is cleared.
bits : 0 - 15 (16 bit)
access : read-write
Interrupt Status for IRQ 3
address_offset : 0x43C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INTS3 : Indicates active channel interrupt requests which are currently causing IRQ 3 to be asserted.
Channel interrupts can be cleared by writing a bit mask here.
Channels with a security/privilege (SECCFG_CHx) greater SECCFG_IRQ3) read as 0 in this register, and ignore writes.
bits : 0 - 15 (16 bit)
access : read-write
DMA Channel 1 Write Address pointer
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH1_WRITE_ADDR : This register updates automatically each time a write completes. The current value is the next address to be written by this channel.
bits : 0 - 31 (32 bit)
access : read-write
Pacing (X/Y) fractional timer
The pacing timer produces TREQ assertions at a rate set by ((X/Y) * sys_clk). This equation is evaluated every sys_clk cycles and therefore can only generate TREQs at a rate of 1 per sys_clk (i.e. permanent TREQ) or less.
address_offset : 0x440 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Y : Pacing Timer Divisor. Specifies the Y value for the (X/Y) fractional timer.
bits : 0 - 15 (16 bit)
access : read-write
X : Pacing Timer Dividend. Specifies the X value for the (X/Y) fractional timer.
bits : 16 - 31 (16 bit)
access : read-write
Pacing (X/Y) fractional timer
The pacing timer produces TREQ assertions at a rate set by ((X/Y) * sys_clk). This equation is evaluated every sys_clk cycles and therefore can only generate TREQs at a rate of 1 per sys_clk (i.e. permanent TREQ) or less.
address_offset : 0x444 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Y : Pacing Timer Divisor. Specifies the Y value for the (X/Y) fractional timer.
bits : 0 - 15 (16 bit)
access : read-write
X : Pacing Timer Dividend. Specifies the X value for the (X/Y) fractional timer.
bits : 16 - 31 (16 bit)
access : read-write
Pacing (X/Y) fractional timer
The pacing timer produces TREQ assertions at a rate set by ((X/Y) * sys_clk). This equation is evaluated every sys_clk cycles and therefore can only generate TREQs at a rate of 1 per sys_clk (i.e. permanent TREQ) or less.
address_offset : 0x448 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Y : Pacing Timer Divisor. Specifies the Y value for the (X/Y) fractional timer.
bits : 0 - 15 (16 bit)
access : read-write
X : Pacing Timer Dividend. Specifies the X value for the (X/Y) fractional timer.
bits : 16 - 31 (16 bit)
access : read-write
Pacing (X/Y) fractional timer
The pacing timer produces TREQ assertions at a rate set by ((X/Y) * sys_clk). This equation is evaluated every sys_clk cycles and therefore can only generate TREQs at a rate of 1 per sys_clk (i.e. permanent TREQ) or less.
address_offset : 0x44C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Y : Pacing Timer Divisor. Specifies the Y value for the (X/Y) fractional timer.
bits : 0 - 15 (16 bit)
access : read-write
X : Pacing Timer Dividend. Specifies the X value for the (X/Y) fractional timer.
bits : 16 - 31 (16 bit)
access : read-write
Trigger one or more channels simultaneously
address_offset : 0x450 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MULTI_CHAN_TRIGGER : Each bit in this register corresponds to a DMA channel. Writing a 1 to the relevant bit is the same as writing to that channel's trigger register the channel will start if it is currently enabled and not already busy.
bits : 0 - 15 (16 bit)
access : write-only
Sniffer Control
address_offset : 0x454 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : Enable sniffer
bits : 0 - 0 (1 bit)
access : read-write
DMACH : DMA channel for Sniffer to observe
bits : 1 - 4 (4 bit)
access : read-write
CALC :
bits : 5 - 8 (4 bit)
access : read-write
Enumeration:
0 : CRC32
Calculate a CRC-32 (IEEE802.3 polynomial)
1 : CRC32R
Calculate a CRC-32 (IEEE802.3 polynomial) with bit reversed data
2 : CRC16
Calculate a CRC-16-CCITT
3 : CRC16R
Calculate a CRC-16-CCITT with bit reversed data
14 : EVEN
XOR reduction over all data. == 1 if the total 1 population count is odd.
15 : SUM
Calculate a simple 32-bit checksum (addition with a 32 bit accumulator)
End of enumeration elements list.
BSWAP : Locally perform a byte reverse on the sniffed data, before feeding into checksum.
Note that the sniff hardware is downstream of the DMA channel byteswap performed in the read master: if channel CTRL_BSWAP and SNIFF_CTRL_BSWAP are both enabled, their effects cancel from the sniffer's point of view.
bits : 9 - 9 (1 bit)
access : read-write
OUT_REV : If set, the result appears bit-reversed when read. This does not affect the way the checksum is calculated the result is transformed on-the-fly between the result register and the bus.
bits : 10 - 10 (1 bit)
access : read-write
OUT_INV : If set, the result appears inverted (bitwise complement) when read. This does not affect the way the checksum is calculated the result is transformed on-the-fly between the result register and the bus.
bits : 11 - 11 (1 bit)
access : read-write
Data accumulator for sniff hardware
address_offset : 0x458 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SNIFF_DATA : Write an initial seed value here before starting a DMA transfer on the channel indicated by SNIFF_CTRL_DMACH. The hardware will update this register each time it observes a read from the indicated channel. Once the channel completes, the final result can be read from this register.
bits : 0 - 31 (32 bit)
access : read-write
Debug RAF, WAF, TDF levels
address_offset : 0x460 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TDF_LVL : Current Transfer-Data-FIFO fill level
bits : 0 - 7 (8 bit)
access : read-only
WAF_LVL : Current Write-Address-FIFO fill level
bits : 8 - 15 (8 bit)
access : read-only
RAF_LVL : Current Read-Address-FIFO fill level
bits : 16 - 23 (8 bit)
access : read-only
Abort an in-progress transfer sequence on one or more channels
address_offset : 0x464 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHAN_ABORT : Each bit corresponds to a channel. Writing a 1 aborts whatever transfer sequence is in progress on that channel. The bit will remain high until any in-flight transfers have been flushed through the address and data FIFOs.
After writing, this register must be polled until it returns all-zero. Until this point, it is unsafe to restart the channel.
bits : 0 - 15 (16 bit)
access : write-only
The number of channels this DMA instance is equipped with. This DMA supports up to 16 hardware channels, but can be configured with as few as one, to minimise silicon area.
address_offset : 0x468 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
N_CHANNELS :
bits : 0 - 4 (5 bit)
access : read-only
DMA Channel 1 Transfer Count
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
COUNT : 28-bit transfer count (256 million transfers maximum).
Program the number of bus transfers a channel will perform before halting. Note that, if transfers are larger than one byte in size, this is not equal to the number of bytes transferred (see CTRL_DATA_SIZE).
When the channel is active, reading this register shows the number of transfers remaining, updating automatically each time a write transfer completes.
Writing this register sets the RELOAD value for the transfer counter. Each time this channel is triggered, the RELOAD value is copied into the live transfer counter. The channel can be started multiple times, and will perform the same number of transfers each time, as programmed by most recent write.
The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a trigger, the written value is used immediately as the length of the new transfer sequence, as well as being written to RELOAD.
bits : 0 - 27 (28 bit)
access : read-write
MODE : When MODE is 0x0, the transfer count decrements with each transfer until 0, and then the channel triggers the next channel indicated by CTRL_CHAIN_TO.
When MODE is 0x1, the transfer count decrements with each transfer until 0, and then the channel re-triggers itself, in addition to the trigger indicated by CTRL_CHAIN_TO. This is useful for e.g. an endless ring-buffer DMA with periodic interrupts.
When MODE is 0xf, the transfer count does not decrement. The DMA channel performs an endless sequence of transfers, never triggering other channels or raising interrupts, until an ABORT is raised.
All other values are reserved.
bits : 28 - 31 (4 bit)
access : read-write
Enumeration:
0 : NORMAL
1 : TRIGGER_SELF
15 : ENDLESS
End of enumeration elements list.
Security configuration for channel 0. Control whether this channel performs Secure/Non-secure and Privileged/Unprivileged bus accesses.
If this channel generates bus accesses of some security level, an access of at least that level (in the order S+P > S+U > NS+P > NS+U) is required to program, trigger, abort, check the status of, interrupt on or acknowledge the interrupt of this channel.
This register automatically locks down (becomes read-only) once software starts to configure the channel.
This register is world-readable, but is writable only from a Secure, Privileged context.
address_offset : 0x480 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
P : Privileged channel. If 1, this channel performs Privileged bus accesses. If 0, it performs Unprivileged bus accesses.
If 1, this channel is controllable only from a Privileged context of the same Secure/Non-secure level, or any context of a higher Secure/Non-secure level.
bits : 0 - 0 (1 bit)
access : read-write
S : Secure channel. If 1, this channel performs Secure bus accesses. If 0, it performs Non-secure bus accesses.
If 1, this channel is controllable only from a Secure context.
bits : 1 - 1 (1 bit)
access : read-write
LOCK : LOCK is 0 at reset, and is set to 1 automatically upon a successful write to this channel's control registers. That is, a write to CTRL, READ_ADDR, WRITE_ADDR, TRANS_COUNT and their aliases.
Once its LOCK bit is set, this register becomes read-only.
A failed write, for example due to the write's privilege being lower than that specified in the channel's SECCFG register, will not set the LOCK bit.
bits : 2 - 2 (1 bit)
access : read-write
Security configuration for channel 1. Control whether this channel performs Secure/Non-secure and Privileged/Unprivileged bus accesses.
If this channel generates bus accesses of some security level, an access of at least that level (in the order S+P > S+U > NS+P > NS+U) is required to program, trigger, abort, check the status of, interrupt on or acknowledge the interrupt of this channel.
This register automatically locks down (becomes read-only) once software starts to configure the channel.
This register is world-readable, but is writable only from a Secure, Privileged context.
address_offset : 0x484 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
P : Privileged channel. If 1, this channel performs Privileged bus accesses. If 0, it performs Unprivileged bus accesses.
If 1, this channel is controllable only from a Privileged context of the same Secure/Non-secure level, or any context of a higher Secure/Non-secure level.
bits : 0 - 0 (1 bit)
access : read-write
S : Secure channel. If 1, this channel performs Secure bus accesses. If 0, it performs Non-secure bus accesses.
If 1, this channel is controllable only from a Secure context.
bits : 1 - 1 (1 bit)
access : read-write
LOCK : LOCK is 0 at reset, and is set to 1 automatically upon a successful write to this channel's control registers. That is, a write to CTRL, READ_ADDR, WRITE_ADDR, TRANS_COUNT and their aliases.
Once its LOCK bit is set, this register becomes read-only.
A failed write, for example due to the write's privilege being lower than that specified in the channel's SECCFG register, will not set the LOCK bit.
bits : 2 - 2 (1 bit)
access : read-write
Security configuration for channel 2. Control whether this channel performs Secure/Non-secure and Privileged/Unprivileged bus accesses.
If this channel generates bus accesses of some security level, an access of at least that level (in the order S+P > S+U > NS+P > NS+U) is required to program, trigger, abort, check the status of, interrupt on or acknowledge the interrupt of this channel.
This register automatically locks down (becomes read-only) once software starts to configure the channel.
This register is world-readable, but is writable only from a Secure, Privileged context.
address_offset : 0x488 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
P : Privileged channel. If 1, this channel performs Privileged bus accesses. If 0, it performs Unprivileged bus accesses.
If 1, this channel is controllable only from a Privileged context of the same Secure/Non-secure level, or any context of a higher Secure/Non-secure level.
bits : 0 - 0 (1 bit)
access : read-write
S : Secure channel. If 1, this channel performs Secure bus accesses. If 0, it performs Non-secure bus accesses.
If 1, this channel is controllable only from a Secure context.
bits : 1 - 1 (1 bit)
access : read-write
LOCK : LOCK is 0 at reset, and is set to 1 automatically upon a successful write to this channel's control registers. That is, a write to CTRL, READ_ADDR, WRITE_ADDR, TRANS_COUNT and their aliases.
Once its LOCK bit is set, this register becomes read-only.
A failed write, for example due to the write's privilege being lower than that specified in the channel's SECCFG register, will not set the LOCK bit.
bits : 2 - 2 (1 bit)
access : read-write
Security configuration for channel 3. Control whether this channel performs Secure/Non-secure and Privileged/Unprivileged bus accesses.
If this channel generates bus accesses of some security level, an access of at least that level (in the order S+P > S+U > NS+P > NS+U) is required to program, trigger, abort, check the status of, interrupt on or acknowledge the interrupt of this channel.
This register automatically locks down (becomes read-only) once software starts to configure the channel.
This register is world-readable, but is writable only from a Secure, Privileged context.
address_offset : 0x48C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
P : Privileged channel. If 1, this channel performs Privileged bus accesses. If 0, it performs Unprivileged bus accesses.
If 1, this channel is controllable only from a Privileged context of the same Secure/Non-secure level, or any context of a higher Secure/Non-secure level.
bits : 0 - 0 (1 bit)
access : read-write
S : Secure channel. If 1, this channel performs Secure bus accesses. If 0, it performs Non-secure bus accesses.
If 1, this channel is controllable only from a Secure context.
bits : 1 - 1 (1 bit)
access : read-write
LOCK : LOCK is 0 at reset, and is set to 1 automatically upon a successful write to this channel's control registers. That is, a write to CTRL, READ_ADDR, WRITE_ADDR, TRANS_COUNT and their aliases.
Once its LOCK bit is set, this register becomes read-only.
A failed write, for example due to the write's privilege being lower than that specified in the channel's SECCFG register, will not set the LOCK bit.
bits : 2 - 2 (1 bit)
access : read-write
Security configuration for channel 4. Control whether this channel performs Secure/Non-secure and Privileged/Unprivileged bus accesses.
If this channel generates bus accesses of some security level, an access of at least that level (in the order S+P > S+U > NS+P > NS+U) is required to program, trigger, abort, check the status of, interrupt on or acknowledge the interrupt of this channel.
This register automatically locks down (becomes read-only) once software starts to configure the channel.
This register is world-readable, but is writable only from a Secure, Privileged context.
address_offset : 0x490 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
P : Privileged channel. If 1, this channel performs Privileged bus accesses. If 0, it performs Unprivileged bus accesses.
If 1, this channel is controllable only from a Privileged context of the same Secure/Non-secure level, or any context of a higher Secure/Non-secure level.
bits : 0 - 0 (1 bit)
access : read-write
S : Secure channel. If 1, this channel performs Secure bus accesses. If 0, it performs Non-secure bus accesses.
If 1, this channel is controllable only from a Secure context.
bits : 1 - 1 (1 bit)
access : read-write
LOCK : LOCK is 0 at reset, and is set to 1 automatically upon a successful write to this channel's control registers. That is, a write to CTRL, READ_ADDR, WRITE_ADDR, TRANS_COUNT and their aliases.
Once its LOCK bit is set, this register becomes read-only.
A failed write, for example due to the write's privilege being lower than that specified in the channel's SECCFG register, will not set the LOCK bit.
bits : 2 - 2 (1 bit)
access : read-write
Security configuration for channel 5. Control whether this channel performs Secure/Non-secure and Privileged/Unprivileged bus accesses.
If this channel generates bus accesses of some security level, an access of at least that level (in the order S+P > S+U > NS+P > NS+U) is required to program, trigger, abort, check the status of, interrupt on or acknowledge the interrupt of this channel.
This register automatically locks down (becomes read-only) once software starts to configure the channel.
This register is world-readable, but is writable only from a Secure, Privileged context.
address_offset : 0x494 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
P : Privileged channel. If 1, this channel performs Privileged bus accesses. If 0, it performs Unprivileged bus accesses.
If 1, this channel is controllable only from a Privileged context of the same Secure/Non-secure level, or any context of a higher Secure/Non-secure level.
bits : 0 - 0 (1 bit)
access : read-write
S : Secure channel. If 1, this channel performs Secure bus accesses. If 0, it performs Non-secure bus accesses.
If 1, this channel is controllable only from a Secure context.
bits : 1 - 1 (1 bit)
access : read-write
LOCK : LOCK is 0 at reset, and is set to 1 automatically upon a successful write to this channel's control registers. That is, a write to CTRL, READ_ADDR, WRITE_ADDR, TRANS_COUNT and their aliases.
Once its LOCK bit is set, this register becomes read-only.
A failed write, for example due to the write's privilege being lower than that specified in the channel's SECCFG register, will not set the LOCK bit.
bits : 2 - 2 (1 bit)
access : read-write
Security configuration for channel 6. Control whether this channel performs Secure/Non-secure and Privileged/Unprivileged bus accesses.
If this channel generates bus accesses of some security level, an access of at least that level (in the order S+P > S+U > NS+P > NS+U) is required to program, trigger, abort, check the status of, interrupt on or acknowledge the interrupt of this channel.
This register automatically locks down (becomes read-only) once software starts to configure the channel.
This register is world-readable, but is writable only from a Secure, Privileged context.
address_offset : 0x498 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
P : Privileged channel. If 1, this channel performs Privileged bus accesses. If 0, it performs Unprivileged bus accesses.
If 1, this channel is controllable only from a Privileged context of the same Secure/Non-secure level, or any context of a higher Secure/Non-secure level.
bits : 0 - 0 (1 bit)
access : read-write
S : Secure channel. If 1, this channel performs Secure bus accesses. If 0, it performs Non-secure bus accesses.
If 1, this channel is controllable only from a Secure context.
bits : 1 - 1 (1 bit)
access : read-write
LOCK : LOCK is 0 at reset, and is set to 1 automatically upon a successful write to this channel's control registers. That is, a write to CTRL, READ_ADDR, WRITE_ADDR, TRANS_COUNT and their aliases.
Once its LOCK bit is set, this register becomes read-only.
A failed write, for example due to the write's privilege being lower than that specified in the channel's SECCFG register, will not set the LOCK bit.
bits : 2 - 2 (1 bit)
access : read-write
Security configuration for channel 7. Control whether this channel performs Secure/Non-secure and Privileged/Unprivileged bus accesses.
If this channel generates bus accesses of some security level, an access of at least that level (in the order S+P > S+U > NS+P > NS+U) is required to program, trigger, abort, check the status of, interrupt on or acknowledge the interrupt of this channel.
This register automatically locks down (becomes read-only) once software starts to configure the channel.
This register is world-readable, but is writable only from a Secure, Privileged context.
address_offset : 0x49C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
P : Privileged channel. If 1, this channel performs Privileged bus accesses. If 0, it performs Unprivileged bus accesses.
If 1, this channel is controllable only from a Privileged context of the same Secure/Non-secure level, or any context of a higher Secure/Non-secure level.
bits : 0 - 0 (1 bit)
access : read-write
S : Secure channel. If 1, this channel performs Secure bus accesses. If 0, it performs Non-secure bus accesses.
If 1, this channel is controllable only from a Secure context.
bits : 1 - 1 (1 bit)
access : read-write
LOCK : LOCK is 0 at reset, and is set to 1 automatically upon a successful write to this channel's control registers. That is, a write to CTRL, READ_ADDR, WRITE_ADDR, TRANS_COUNT and their aliases.
Once its LOCK bit is set, this register becomes read-only.
A failed write, for example due to the write's privilege being lower than that specified in the channel's SECCFG register, will not set the LOCK bit.
bits : 2 - 2 (1 bit)
access : read-write
Security configuration for channel 8. Control whether this channel performs Secure/Non-secure and Privileged/Unprivileged bus accesses.
If this channel generates bus accesses of some security level, an access of at least that level (in the order S+P > S+U > NS+P > NS+U) is required to program, trigger, abort, check the status of, interrupt on or acknowledge the interrupt of this channel.
This register automatically locks down (becomes read-only) once software starts to configure the channel.
This register is world-readable, but is writable only from a Secure, Privileged context.
address_offset : 0x4A0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
P : Privileged channel. If 1, this channel performs Privileged bus accesses. If 0, it performs Unprivileged bus accesses.
If 1, this channel is controllable only from a Privileged context of the same Secure/Non-secure level, or any context of a higher Secure/Non-secure level.
bits : 0 - 0 (1 bit)
access : read-write
S : Secure channel. If 1, this channel performs Secure bus accesses. If 0, it performs Non-secure bus accesses.
If 1, this channel is controllable only from a Secure context.
bits : 1 - 1 (1 bit)
access : read-write
LOCK : LOCK is 0 at reset, and is set to 1 automatically upon a successful write to this channel's control registers. That is, a write to CTRL, READ_ADDR, WRITE_ADDR, TRANS_COUNT and their aliases.
Once its LOCK bit is set, this register becomes read-only.
A failed write, for example due to the write's privilege being lower than that specified in the channel's SECCFG register, will not set the LOCK bit.
bits : 2 - 2 (1 bit)
access : read-write
Security configuration for channel 9. Control whether this channel performs Secure/Non-secure and Privileged/Unprivileged bus accesses.
If this channel generates bus accesses of some security level, an access of at least that level (in the order S+P > S+U > NS+P > NS+U) is required to program, trigger, abort, check the status of, interrupt on or acknowledge the interrupt of this channel.
This register automatically locks down (becomes read-only) once software starts to configure the channel.
This register is world-readable, but is writable only from a Secure, Privileged context.
address_offset : 0x4A4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
P : Privileged channel. If 1, this channel performs Privileged bus accesses. If 0, it performs Unprivileged bus accesses.
If 1, this channel is controllable only from a Privileged context of the same Secure/Non-secure level, or any context of a higher Secure/Non-secure level.
bits : 0 - 0 (1 bit)
access : read-write
S : Secure channel. If 1, this channel performs Secure bus accesses. If 0, it performs Non-secure bus accesses.
If 1, this channel is controllable only from a Secure context.
bits : 1 - 1 (1 bit)
access : read-write
LOCK : LOCK is 0 at reset, and is set to 1 automatically upon a successful write to this channel's control registers. That is, a write to CTRL, READ_ADDR, WRITE_ADDR, TRANS_COUNT and their aliases.
Once its LOCK bit is set, this register becomes read-only.
A failed write, for example due to the write's privilege being lower than that specified in the channel's SECCFG register, will not set the LOCK bit.
bits : 2 - 2 (1 bit)
access : read-write
Security configuration for channel 10. Control whether this channel performs Secure/Non-secure and Privileged/Unprivileged bus accesses.
If this channel generates bus accesses of some security level, an access of at least that level (in the order S+P > S+U > NS+P > NS+U) is required to program, trigger, abort, check the status of, interrupt on or acknowledge the interrupt of this channel.
This register automatically locks down (becomes read-only) once software starts to configure the channel.
This register is world-readable, but is writable only from a Secure, Privileged context.
address_offset : 0x4A8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
P : Privileged channel. If 1, this channel performs Privileged bus accesses. If 0, it performs Unprivileged bus accesses.
If 1, this channel is controllable only from a Privileged context of the same Secure/Non-secure level, or any context of a higher Secure/Non-secure level.
bits : 0 - 0 (1 bit)
access : read-write
S : Secure channel. If 1, this channel performs Secure bus accesses. If 0, it performs Non-secure bus accesses.
If 1, this channel is controllable only from a Secure context.
bits : 1 - 1 (1 bit)
access : read-write
LOCK : LOCK is 0 at reset, and is set to 1 automatically upon a successful write to this channel's control registers. That is, a write to CTRL, READ_ADDR, WRITE_ADDR, TRANS_COUNT and their aliases.
Once its LOCK bit is set, this register becomes read-only.
A failed write, for example due to the write's privilege being lower than that specified in the channel's SECCFG register, will not set the LOCK bit.
bits : 2 - 2 (1 bit)
access : read-write
Security configuration for channel 11. Control whether this channel performs Secure/Non-secure and Privileged/Unprivileged bus accesses.
If this channel generates bus accesses of some security level, an access of at least that level (in the order S+P > S+U > NS+P > NS+U) is required to program, trigger, abort, check the status of, interrupt on or acknowledge the interrupt of this channel.
This register automatically locks down (becomes read-only) once software starts to configure the channel.
This register is world-readable, but is writable only from a Secure, Privileged context.
address_offset : 0x4AC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
P : Privileged channel. If 1, this channel performs Privileged bus accesses. If 0, it performs Unprivileged bus accesses.
If 1, this channel is controllable only from a Privileged context of the same Secure/Non-secure level, or any context of a higher Secure/Non-secure level.
bits : 0 - 0 (1 bit)
access : read-write
S : Secure channel. If 1, this channel performs Secure bus accesses. If 0, it performs Non-secure bus accesses.
If 1, this channel is controllable only from a Secure context.
bits : 1 - 1 (1 bit)
access : read-write
LOCK : LOCK is 0 at reset, and is set to 1 automatically upon a successful write to this channel's control registers. That is, a write to CTRL, READ_ADDR, WRITE_ADDR, TRANS_COUNT and their aliases.
Once its LOCK bit is set, this register becomes read-only.
A failed write, for example due to the write's privilege being lower than that specified in the channel's SECCFG register, will not set the LOCK bit.
bits : 2 - 2 (1 bit)
access : read-write
Security configuration for channel 12. Control whether this channel performs Secure/Non-secure and Privileged/Unprivileged bus accesses.
If this channel generates bus accesses of some security level, an access of at least that level (in the order S+P > S+U > NS+P > NS+U) is required to program, trigger, abort, check the status of, interrupt on or acknowledge the interrupt of this channel.
This register automatically locks down (becomes read-only) once software starts to configure the channel.
This register is world-readable, but is writable only from a Secure, Privileged context.
address_offset : 0x4B0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
P : Privileged channel. If 1, this channel performs Privileged bus accesses. If 0, it performs Unprivileged bus accesses.
If 1, this channel is controllable only from a Privileged context of the same Secure/Non-secure level, or any context of a higher Secure/Non-secure level.
bits : 0 - 0 (1 bit)
access : read-write
S : Secure channel. If 1, this channel performs Secure bus accesses. If 0, it performs Non-secure bus accesses.
If 1, this channel is controllable only from a Secure context.
bits : 1 - 1 (1 bit)
access : read-write
LOCK : LOCK is 0 at reset, and is set to 1 automatically upon a successful write to this channel's control registers. That is, a write to CTRL, READ_ADDR, WRITE_ADDR, TRANS_COUNT and their aliases.
Once its LOCK bit is set, this register becomes read-only.
A failed write, for example due to the write's privilege being lower than that specified in the channel's SECCFG register, will not set the LOCK bit.
bits : 2 - 2 (1 bit)
access : read-write
Security configuration for channel 13. Control whether this channel performs Secure/Non-secure and Privileged/Unprivileged bus accesses.
If this channel generates bus accesses of some security level, an access of at least that level (in the order S+P > S+U > NS+P > NS+U) is required to program, trigger, abort, check the status of, interrupt on or acknowledge the interrupt of this channel.
This register automatically locks down (becomes read-only) once software starts to configure the channel.
This register is world-readable, but is writable only from a Secure, Privileged context.
address_offset : 0x4B4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
P : Privileged channel. If 1, this channel performs Privileged bus accesses. If 0, it performs Unprivileged bus accesses.
If 1, this channel is controllable only from a Privileged context of the same Secure/Non-secure level, or any context of a higher Secure/Non-secure level.
bits : 0 - 0 (1 bit)
access : read-write
S : Secure channel. If 1, this channel performs Secure bus accesses. If 0, it performs Non-secure bus accesses.
If 1, this channel is controllable only from a Secure context.
bits : 1 - 1 (1 bit)
access : read-write
LOCK : LOCK is 0 at reset, and is set to 1 automatically upon a successful write to this channel's control registers. That is, a write to CTRL, READ_ADDR, WRITE_ADDR, TRANS_COUNT and their aliases.
Once its LOCK bit is set, this register becomes read-only.
A failed write, for example due to the write's privilege being lower than that specified in the channel's SECCFG register, will not set the LOCK bit.
bits : 2 - 2 (1 bit)
access : read-write
Security configuration for channel 14. Control whether this channel performs Secure/Non-secure and Privileged/Unprivileged bus accesses.
If this channel generates bus accesses of some security level, an access of at least that level (in the order S+P > S+U > NS+P > NS+U) is required to program, trigger, abort, check the status of, interrupt on or acknowledge the interrupt of this channel.
This register automatically locks down (becomes read-only) once software starts to configure the channel.
This register is world-readable, but is writable only from a Secure, Privileged context.
address_offset : 0x4B8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
P : Privileged channel. If 1, this channel performs Privileged bus accesses. If 0, it performs Unprivileged bus accesses.
If 1, this channel is controllable only from a Privileged context of the same Secure/Non-secure level, or any context of a higher Secure/Non-secure level.
bits : 0 - 0 (1 bit)
access : read-write
S : Secure channel. If 1, this channel performs Secure bus accesses. If 0, it performs Non-secure bus accesses.
If 1, this channel is controllable only from a Secure context.
bits : 1 - 1 (1 bit)
access : read-write
LOCK : LOCK is 0 at reset, and is set to 1 automatically upon a successful write to this channel's control registers. That is, a write to CTRL, READ_ADDR, WRITE_ADDR, TRANS_COUNT and their aliases.
Once its LOCK bit is set, this register becomes read-only.
A failed write, for example due to the write's privilege being lower than that specified in the channel's SECCFG register, will not set the LOCK bit.
bits : 2 - 2 (1 bit)
access : read-write
Security configuration for channel 15. Control whether this channel performs Secure/Non-secure and Privileged/Unprivileged bus accesses.
If this channel generates bus accesses of some security level, an access of at least that level (in the order S+P > S+U > NS+P > NS+U) is required to program, trigger, abort, check the status of, interrupt on or acknowledge the interrupt of this channel.
This register automatically locks down (becomes read-only) once software starts to configure the channel.
This register is world-readable, but is writable only from a Secure, Privileged context.
address_offset : 0x4BC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
P : Privileged channel. If 1, this channel performs Privileged bus accesses. If 0, it performs Unprivileged bus accesses.
If 1, this channel is controllable only from a Privileged context of the same Secure/Non-secure level, or any context of a higher Secure/Non-secure level.
bits : 0 - 0 (1 bit)
access : read-write
S : Secure channel. If 1, this channel performs Secure bus accesses. If 0, it performs Non-secure bus accesses.
If 1, this channel is controllable only from a Secure context.
bits : 1 - 1 (1 bit)
access : read-write
LOCK : LOCK is 0 at reset, and is set to 1 automatically upon a successful write to this channel's control registers. That is, a write to CTRL, READ_ADDR, WRITE_ADDR, TRANS_COUNT and their aliases.
Once its LOCK bit is set, this register becomes read-only.
A failed write, for example due to the write's privilege being lower than that specified in the channel's SECCFG register, will not set the LOCK bit.
bits : 2 - 2 (1 bit)
access : read-write
DMA Channel 1 Control and Status
address_offset : 0x4C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : DMA Channel Enable.
When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high)
bits : 0 - 0 (1 bit)
access : read-write
HIGH_PRIORITY : HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels.
This only affects the order in which the DMA schedules channels. The DMA's bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput.
bits : 1 - 1 (1 bit)
access : read-write
DATA_SIZE : Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer.
bits : 2 - 3 (2 bit)
access : read-write
Enumeration:
0 : SIZE_BYTE
1 : SIZE_HALFWORD
2 : SIZE_WORD
End of enumeration elements list.
INCR_READ : If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address.
Generally this should be disabled for peripheral-to-memory transfers.
bits : 4 - 4 (1 bit)
access : read-write
INCR_READ_REV : If 1, and INCR_READ is 1, the read address is decremented rather than incremented with each transfer.
If 1, and INCR_READ is 0, this otherwise-unused combination causes the read address to be incremented by twice the transfer size, i.e. skipping over alternate addresses.
bits : 5 - 5 (1 bit)
access : read-write
INCR_WRITE : If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address.
Generally this should be disabled for memory-to-peripheral transfers.
bits : 6 - 6 (1 bit)
access : read-write
INCR_WRITE_REV : If 1, and INCR_WRITE is 1, the write address is decremented rather than incremented with each transfer.
If 1, and INCR_WRITE is 0, this otherwise-unused combination causes the write address to be incremented by twice the transfer size, i.e. skipping over alternate addresses.
bits : 7 - 7 (1 bit)
access : read-write
RING_SIZE : Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned ring buffers.
Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL.
bits : 8 - 11 (4 bit)
access : read-write
Enumeration:
0 : RING_NONE
End of enumeration elements list.
RING_SEL : Select whether RING_SIZE applies to read or write addresses.
If 0, read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, write addresses are wrapped.
bits : 12 - 12 (1 bit)
access : read-write
CHAIN_TO : When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_.
Note this field resets to 0, so channels 1 and above will chain to channel 0 by default. Set this field to avoid this behaviour.
bits : 13 - 16 (4 bit)
access : read-write
TREQ_SEL : Select a Transfer Request signal.
The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system).
0x0 to 0x3a -> select DREQ n as TREQ
bits : 17 - 22 (6 bit)
access : read-write
Enumeration:
0 : PIO0_TX0
Select PIO0's TX FIFO 0 as TREQ
1 : PIO0_TX1
Select PIO0's TX FIFO 1 as TREQ
2 : PIO0_TX2
Select PIO0's TX FIFO 2 as TREQ
3 : PIO0_TX3
Select PIO0's TX FIFO 3 as TREQ
4 : PIO0_RX0
Select PIO0's RX FIFO 0 as TREQ
5 : PIO0_RX1
Select PIO0's RX FIFO 1 as TREQ
6 : PIO0_RX2
Select PIO0's RX FIFO 2 as TREQ
7 : PIO0_RX3
Select PIO0's RX FIFO 3 as TREQ
8 : PIO1_TX0
Select PIO1's TX FIFO 0 as TREQ
9 : PIO1_TX1
Select PIO1's TX FIFO 1 as TREQ
10 : PIO1_TX2
Select PIO1's TX FIFO 2 as TREQ
11 : PIO1_TX3
Select PIO1's TX FIFO 3 as TREQ
12 : PIO1_RX0
Select PIO1's RX FIFO 0 as TREQ
13 : PIO1_RX1
Select PIO1's RX FIFO 1 as TREQ
14 : PIO1_RX2
Select PIO1's RX FIFO 2 as TREQ
15 : PIO1_RX3
Select PIO1's RX FIFO 3 as TREQ
16 : PIO2_TX0
Select PIO2's TX FIFO 0 as TREQ
17 : PIO2_TX1
Select PIO2's TX FIFO 1 as TREQ
18 : PIO2_TX2
Select PIO2's TX FIFO 2 as TREQ
19 : PIO2_TX3
Select PIO2's TX FIFO 3 as TREQ
20 : PIO2_RX0
Select PIO2's RX FIFO 0 as TREQ
21 : PIO2_RX1
Select PIO2's RX FIFO 1 as TREQ
22 : PIO2_RX2
Select PIO2's RX FIFO 2 as TREQ
23 : PIO2_RX3
Select PIO2's RX FIFO 3 as TREQ
24 : SPI0_TX
Select SPI0's TX FIFO as TREQ
25 : SPI0_RX
Select SPI0's RX FIFO as TREQ
26 : SPI1_TX
Select SPI1's TX FIFO as TREQ
27 : SPI1_RX
Select SPI1's RX FIFO as TREQ
28 : UART0_TX
Select UART0's TX FIFO as TREQ
29 : UART0_RX
Select UART0's RX FIFO as TREQ
30 : UART1_TX
Select UART1's TX FIFO as TREQ
31 : UART1_RX
Select UART1's RX FIFO as TREQ
32 : PWM_WRAP0
Select PWM Counter 0's Wrap Value as TREQ
33 : PWM_WRAP1
Select PWM Counter 1's Wrap Value as TREQ
34 : PWM_WRAP2
Select PWM Counter 2's Wrap Value as TREQ
35 : PWM_WRAP3
Select PWM Counter 3's Wrap Value as TREQ
36 : PWM_WRAP4
Select PWM Counter 4's Wrap Value as TREQ
37 : PWM_WRAP5
Select PWM Counter 5's Wrap Value as TREQ
38 : PWM_WRAP6
Select PWM Counter 6's Wrap Value as TREQ
39 : PWM_WRAP7
Select PWM Counter 7's Wrap Value as TREQ
40 : PWM_WRAP8
Select PWM Counter 8's Wrap Value as TREQ
41 : PWM_WRAP9
Select PWM Counter 9's Wrap Value as TREQ
42 : PWM_WRAP10
Select PWM Counter 0's Wrap Value as TREQ
43 : PWM_WRAP11
Select PWM Counter 1's Wrap Value as TREQ
44 : I2C0_TX
Select I2C0's TX FIFO as TREQ
45 : I2C0_RX
Select I2C0's RX FIFO as TREQ
46 : I2C1_TX
Select I2C1's TX FIFO as TREQ
47 : I2C1_RX
Select I2C1's RX FIFO as TREQ
48 : ADC
Select the ADC as TREQ
49 : XIP_STREAM
Select the XIP Streaming FIFO as TREQ
50 : XIP_QMITX
Select XIP_QMITX as TREQ
51 : XIP_QMIRX
Select XIP_QMIRX as TREQ
52 : HSTX
Select HSTX as TREQ
53 : CORESIGHT
Select CORESIGHT as TREQ
54 : SHA256
Select SHA256 as TREQ
59 : TIMER0
Select Timer 0 as TREQ
60 : TIMER1
Select Timer 1 as TREQ
61 : TIMER2
Select Timer 2 as TREQ (Optional)
62 : TIMER3
Select Timer 3 as TREQ (Optional)
63 : PERMANENT
Permanent request, for unpaced transfers.
End of enumeration elements list.
IRQ_QUIET : In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain.
This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks.
bits : 23 - 23 (1 bit)
access : read-write
BSWAP : Apply byte-swap transformation to DMA data.
For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order.
bits : 24 - 24 (1 bit)
access : read-write
SNIFF_EN : If 1, this channel's data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected.
This allows checksum to be enabled or disabled on a per-control- block basis.
bits : 25 - 25 (1 bit)
access : read-write
BUSY : This flag goes high when the channel starts a new transfer sequence, and low when the last transfer of that sequence completes. Clearing EN while BUSY is high pauses the channel, and BUSY will stay high while paused.
To terminate a sequence early (and clear the BUSY flag), see CHAN_ABORT.
bits : 26 - 26 (1 bit)
access : read-only
WRITE_ERROR : If 1, the channel received a write bus error. Write one to clear.
WRITE_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 5 transfers later)
bits : 29 - 29 (1 bit)
access : read-write
READ_ERROR : If 1, the channel received a read bus error. Write one to clear.
READ_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 3 transfers later)
bits : 30 - 30 (1 bit)
access : read-write
AHB_ERROR : Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel halts when it encounters any bus error, and always raises its channel IRQ flag.
bits : 31 - 31 (1 bit)
access : read-only
Security configuration for IRQ 0. Control whether the IRQ permits configuration by Non-secure/Unprivileged contexts, and whether it can observe Secure/Privileged channel interrupt flags.
address_offset : 0x4C0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
P : Privileged IRQ. If 1, this IRQ's control registers can only be accessed from a Privileged context.
If 0, this IRQ's control registers can be accessed from an Unprivileged context, but Privileged channels (as per SECCFG_CHx) are masked from the IRQ status, and this IRQ's registers can not be used to acknowledge the channel interrupts of Privileged channels.
bits : 0 - 0 (1 bit)
access : read-write
S : Secure IRQ. If 1, this IRQ's control registers can only be accessed from a Secure context.
If 0, this IRQ's control registers can be accessed from a Non-secure context, but Secure channels (as per SECCFG_CHx) are masked from the IRQ status, and this IRQ's registers can not be used to acknowledge the channel interrupts of Secure channels.
bits : 1 - 1 (1 bit)
access : read-write
Security configuration for IRQ 1. Control whether the IRQ permits configuration by Non-secure/Unprivileged contexts, and whether it can observe Secure/Privileged channel interrupt flags.
address_offset : 0x4C4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
P : Privileged IRQ. If 1, this IRQ's control registers can only be accessed from a Privileged context.
If 0, this IRQ's control registers can be accessed from an Unprivileged context, but Privileged channels (as per SECCFG_CHx) are masked from the IRQ status, and this IRQ's registers can not be used to acknowledge the channel interrupts of Privileged channels.
bits : 0 - 0 (1 bit)
access : read-write
S : Secure IRQ. If 1, this IRQ's control registers can only be accessed from a Secure context.
If 0, this IRQ's control registers can be accessed from a Non-secure context, but Secure channels (as per SECCFG_CHx) are masked from the IRQ status, and this IRQ's registers can not be used to acknowledge the channel interrupts of Secure channels.
bits : 1 - 1 (1 bit)
access : read-write
Security configuration for IRQ 2. Control whether the IRQ permits configuration by Non-secure/Unprivileged contexts, and whether it can observe Secure/Privileged channel interrupt flags.
address_offset : 0x4C8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
P : Privileged IRQ. If 1, this IRQ's control registers can only be accessed from a Privileged context.
If 0, this IRQ's control registers can be accessed from an Unprivileged context, but Privileged channels (as per SECCFG_CHx) are masked from the IRQ status, and this IRQ's registers can not be used to acknowledge the channel interrupts of Privileged channels.
bits : 0 - 0 (1 bit)
access : read-write
S : Secure IRQ. If 1, this IRQ's control registers can only be accessed from a Secure context.
If 0, this IRQ's control registers can be accessed from a Non-secure context, but Secure channels (as per SECCFG_CHx) are masked from the IRQ status, and this IRQ's registers can not be used to acknowledge the channel interrupts of Secure channels.
bits : 1 - 1 (1 bit)
access : read-write
Security configuration for IRQ 3. Control whether the IRQ permits configuration by Non-secure/Unprivileged contexts, and whether it can observe Secure/Privileged channel interrupt flags.
address_offset : 0x4CC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
P : Privileged IRQ. If 1, this IRQ's control registers can only be accessed from a Privileged context.
If 0, this IRQ's control registers can be accessed from an Unprivileged context, but Privileged channels (as per SECCFG_CHx) are masked from the IRQ status, and this IRQ's registers can not be used to acknowledge the channel interrupts of Privileged channels.
bits : 0 - 0 (1 bit)
access : read-write
S : Secure IRQ. If 1, this IRQ's control registers can only be accessed from a Secure context.
If 0, this IRQ's control registers can be accessed from a Non-secure context, but Secure channels (as per SECCFG_CHx) are masked from the IRQ status, and this IRQ's registers can not be used to acknowledge the channel interrupts of Secure channels.
bits : 1 - 1 (1 bit)
access : read-write
Miscellaneous security configuration
address_offset : 0x4D0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SNIFF_P : If 1, the sniffer can see data transfers from Privileged channels, and can itself only be accessed from a privileged context, or from a Secure context when SNIFF_S is 0.
If 0, the sniffer can be accessed from either a Privileged or Unprivileged context (with sufficient security level) but can not see transfers from Privileged channels.
bits : 0 - 0 (1 bit)
access : read-write
SNIFF_S : If 1, the sniffer can see data transfers from Secure channels, and can itself only be accessed from a Secure context.
If 0, the sniffer can be accessed from either a Secure or Non-secure context, but can not see data transfers of Secure channels.
bits : 1 - 1 (1 bit)
access : read-write
TIMER0_P : If 1, the TIMER0 register is only accessible from a Privileged (or more Secure) context, and timer DREQ 0 is only visible to Privileged (or more Secure) channels.
bits : 2 - 2 (1 bit)
access : read-write
TIMER0_S : If 1, the TIMER0 register is only accessible from a Secure context, and timer DREQ 0 is only visible to Secure channels.
bits : 3 - 3 (1 bit)
access : read-write
TIMER1_P : If 1, the TIMER1 register is only accessible from a Privileged (or more Secure) context, and timer DREQ 1 is only visible to Privileged (or more Secure) channels.
bits : 4 - 4 (1 bit)
access : read-write
TIMER1_S : If 1, the TIMER1 register is only accessible from a Secure context, and timer DREQ 1 is only visible to Secure channels.
bits : 5 - 5 (1 bit)
access : read-write
TIMER2_P : If 1, the TIMER2 register is only accessible from a Privileged (or more Secure) context, and timer DREQ 2 is only visible to Privileged (or more Secure) channels.
bits : 6 - 6 (1 bit)
access : read-write
TIMER2_S : If 1, the TIMER2 register is only accessible from a Secure context, and timer DREQ 2 is only visible to Secure channels.
bits : 7 - 7 (1 bit)
access : read-write
TIMER3_P : If 1, the TIMER3 register is only accessible from a Privileged (or more Secure) context, and timer DREQ 3 is only visible to Privileged (or more Secure) channels.
bits : 8 - 8 (1 bit)
access : read-write
TIMER3_S : If 1, the TIMER3 register is only accessible from a Secure context, and timer DREQ 3 is only visible to Secure channels.
bits : 9 - 9 (1 bit)
access : read-write
Alias for channel 1 CTRL register
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH1_AL1_CTRL :
bits : 0 - 31 (32 bit)
access : read-write
Control register for DMA MPU. Accessible only from a Privileged context.
address_offset : 0x500 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
P : Determine whether an address not covered by an active MPU region is Privileged (1) or Unprivileged (0)
bits : 1 - 1 (1 bit)
access : read-write
S : Determine whether an address not covered by an active MPU region is Secure (1) or Non-secure (0)
bits : 2 - 2 (1 bit)
access : read-write
NS_HIDE_ADDR : By default, when a region's S bit is clear, Non-secure-Privileged reads can see the region's base address and limit address. Set this bit to make the addresses appear as 0 to Non-secure reads, even when the region is Non-secure, to avoid leaking information about the processor SAU map.
bits : 3 - 3 (1 bit)
access : read-write
Base address register for MPU region 0. Writable only from a Secure, Privileged context.
address_offset : 0x504 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADDR : This MPU region matches addresses where addr[31:5] (the 27 most significant bits) are greater than or equal to BAR_ADDR, and less than or equal to LAR_ADDR.
Readable from any Privileged context, if and only if this region's S bit is clear, and MPU_CTRL_NS_HIDE_ADDR is clear. Otherwise readable only from a Secure, Privileged context.
bits : 5 - 31 (27 bit)
access : read-write
Limit address register for MPU region 0. Writable only from a Secure, Privileged context, with the exception of the P bit.
address_offset : 0x508 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : Region enable. If 1, any address within range specified by the base address (BAR_ADDR) and limit address (LAR_ADDR) has the attributes specified by S and P.
bits : 0 - 0 (1 bit)
access : read-write
P : Determines the Privileged/Unprivileged (=1/0) status of addresses matching this region, if this region is enabled. Writable from any Privileged context, if and only if the S bit is clear. Otherwise, writable only from a Secure, Privileged context.
bits : 1 - 1 (1 bit)
access : read-write
S : Determines the Secure/Non-secure (=1/0) status of addresses matching this region, if this region is enabled.
bits : 2 - 2 (1 bit)
access : read-write
ADDR : Limit address bits 31:5. Readable from any Privileged context, if and only if this region's S bit is clear, and MPU_CTRL_NS_HIDE_ADDR is clear. Otherwise readable only from a Secure, Privileged context.
bits : 5 - 31 (27 bit)
access : read-write
Base address register for MPU region 1. Writable only from a Secure, Privileged context.
address_offset : 0x50C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADDR : This MPU region matches addresses where addr[31:5] (the 27 most significant bits) are greater than or equal to BAR_ADDR, and less than or equal to LAR_ADDR.
Readable from any Privileged context, if and only if this region's S bit is clear, and MPU_CTRL_NS_HIDE_ADDR is clear. Otherwise readable only from a Secure, Privileged context.
bits : 5 - 31 (27 bit)
access : read-write
Limit address register for MPU region 1. Writable only from a Secure, Privileged context, with the exception of the P bit.
address_offset : 0x510 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : Region enable. If 1, any address within range specified by the base address (BAR_ADDR) and limit address (LAR_ADDR) has the attributes specified by S and P.
bits : 0 - 0 (1 bit)
access : read-write
P : Determines the Privileged/Unprivileged (=1/0) status of addresses matching this region, if this region is enabled. Writable from any Privileged context, if and only if the S bit is clear. Otherwise, writable only from a Secure, Privileged context.
bits : 1 - 1 (1 bit)
access : read-write
S : Determines the Secure/Non-secure (=1/0) status of addresses matching this region, if this region is enabled.
bits : 2 - 2 (1 bit)
access : read-write
ADDR : Limit address bits 31:5. Readable from any Privileged context, if and only if this region's S bit is clear, and MPU_CTRL_NS_HIDE_ADDR is clear. Otherwise readable only from a Secure, Privileged context.
bits : 5 - 31 (27 bit)
access : read-write
Base address register for MPU region 2. Writable only from a Secure, Privileged context.
address_offset : 0x514 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADDR : This MPU region matches addresses where addr[31:5] (the 27 most significant bits) are greater than or equal to BAR_ADDR, and less than or equal to LAR_ADDR.
Readable from any Privileged context, if and only if this region's S bit is clear, and MPU_CTRL_NS_HIDE_ADDR is clear. Otherwise readable only from a Secure, Privileged context.
bits : 5 - 31 (27 bit)
access : read-write
Limit address register for MPU region 2. Writable only from a Secure, Privileged context, with the exception of the P bit.
address_offset : 0x518 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : Region enable. If 1, any address within range specified by the base address (BAR_ADDR) and limit address (LAR_ADDR) has the attributes specified by S and P.
bits : 0 - 0 (1 bit)
access : read-write
P : Determines the Privileged/Unprivileged (=1/0) status of addresses matching this region, if this region is enabled. Writable from any Privileged context, if and only if the S bit is clear. Otherwise, writable only from a Secure, Privileged context.
bits : 1 - 1 (1 bit)
access : read-write
S : Determines the Secure/Non-secure (=1/0) status of addresses matching this region, if this region is enabled.
bits : 2 - 2 (1 bit)
access : read-write
ADDR : Limit address bits 31:5. Readable from any Privileged context, if and only if this region's S bit is clear, and MPU_CTRL_NS_HIDE_ADDR is clear. Otherwise readable only from a Secure, Privileged context.
bits : 5 - 31 (27 bit)
access : read-write
Base address register for MPU region 3. Writable only from a Secure, Privileged context.
address_offset : 0x51C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADDR : This MPU region matches addresses where addr[31:5] (the 27 most significant bits) are greater than or equal to BAR_ADDR, and less than or equal to LAR_ADDR.
Readable from any Privileged context, if and only if this region's S bit is clear, and MPU_CTRL_NS_HIDE_ADDR is clear. Otherwise readable only from a Secure, Privileged context.
bits : 5 - 31 (27 bit)
access : read-write
Limit address register for MPU region 3. Writable only from a Secure, Privileged context, with the exception of the P bit.
address_offset : 0x520 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : Region enable. If 1, any address within range specified by the base address (BAR_ADDR) and limit address (LAR_ADDR) has the attributes specified by S and P.
bits : 0 - 0 (1 bit)
access : read-write
P : Determines the Privileged/Unprivileged (=1/0) status of addresses matching this region, if this region is enabled. Writable from any Privileged context, if and only if the S bit is clear. Otherwise, writable only from a Secure, Privileged context.
bits : 1 - 1 (1 bit)
access : read-write
S : Determines the Secure/Non-secure (=1/0) status of addresses matching this region, if this region is enabled.
bits : 2 - 2 (1 bit)
access : read-write
ADDR : Limit address bits 31:5. Readable from any Privileged context, if and only if this region's S bit is clear, and MPU_CTRL_NS_HIDE_ADDR is clear. Otherwise readable only from a Secure, Privileged context.
bits : 5 - 31 (27 bit)
access : read-write
Base address register for MPU region 4. Writable only from a Secure, Privileged context.
address_offset : 0x524 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADDR : This MPU region matches addresses where addr[31:5] (the 27 most significant bits) are greater than or equal to BAR_ADDR, and less than or equal to LAR_ADDR.
Readable from any Privileged context, if and only if this region's S bit is clear, and MPU_CTRL_NS_HIDE_ADDR is clear. Otherwise readable only from a Secure, Privileged context.
bits : 5 - 31 (27 bit)
access : read-write
Limit address register for MPU region 4. Writable only from a Secure, Privileged context, with the exception of the P bit.
address_offset : 0x528 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : Region enable. If 1, any address within range specified by the base address (BAR_ADDR) and limit address (LAR_ADDR) has the attributes specified by S and P.
bits : 0 - 0 (1 bit)
access : read-write
P : Determines the Privileged/Unprivileged (=1/0) status of addresses matching this region, if this region is enabled. Writable from any Privileged context, if and only if the S bit is clear. Otherwise, writable only from a Secure, Privileged context.
bits : 1 - 1 (1 bit)
access : read-write
S : Determines the Secure/Non-secure (=1/0) status of addresses matching this region, if this region is enabled.
bits : 2 - 2 (1 bit)
access : read-write
ADDR : Limit address bits 31:5. Readable from any Privileged context, if and only if this region's S bit is clear, and MPU_CTRL_NS_HIDE_ADDR is clear. Otherwise readable only from a Secure, Privileged context.
bits : 5 - 31 (27 bit)
access : read-write
Base address register for MPU region 5. Writable only from a Secure, Privileged context.
address_offset : 0x52C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADDR : This MPU region matches addresses where addr[31:5] (the 27 most significant bits) are greater than or equal to BAR_ADDR, and less than or equal to LAR_ADDR.
Readable from any Privileged context, if and only if this region's S bit is clear, and MPU_CTRL_NS_HIDE_ADDR is clear. Otherwise readable only from a Secure, Privileged context.
bits : 5 - 31 (27 bit)
access : read-write
Limit address register for MPU region 5. Writable only from a Secure, Privileged context, with the exception of the P bit.
address_offset : 0x530 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : Region enable. If 1, any address within range specified by the base address (BAR_ADDR) and limit address (LAR_ADDR) has the attributes specified by S and P.
bits : 0 - 0 (1 bit)
access : read-write
P : Determines the Privileged/Unprivileged (=1/0) status of addresses matching this region, if this region is enabled. Writable from any Privileged context, if and only if the S bit is clear. Otherwise, writable only from a Secure, Privileged context.
bits : 1 - 1 (1 bit)
access : read-write
S : Determines the Secure/Non-secure (=1/0) status of addresses matching this region, if this region is enabled.
bits : 2 - 2 (1 bit)
access : read-write
ADDR : Limit address bits 31:5. Readable from any Privileged context, if and only if this region's S bit is clear, and MPU_CTRL_NS_HIDE_ADDR is clear. Otherwise readable only from a Secure, Privileged context.
bits : 5 - 31 (27 bit)
access : read-write
Base address register for MPU region 6. Writable only from a Secure, Privileged context.
address_offset : 0x534 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADDR : This MPU region matches addresses where addr[31:5] (the 27 most significant bits) are greater than or equal to BAR_ADDR, and less than or equal to LAR_ADDR.
Readable from any Privileged context, if and only if this region's S bit is clear, and MPU_CTRL_NS_HIDE_ADDR is clear. Otherwise readable only from a Secure, Privileged context.
bits : 5 - 31 (27 bit)
access : read-write
Limit address register for MPU region 6. Writable only from a Secure, Privileged context, with the exception of the P bit.
address_offset : 0x538 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : Region enable. If 1, any address within range specified by the base address (BAR_ADDR) and limit address (LAR_ADDR) has the attributes specified by S and P.
bits : 0 - 0 (1 bit)
access : read-write
P : Determines the Privileged/Unprivileged (=1/0) status of addresses matching this region, if this region is enabled. Writable from any Privileged context, if and only if the S bit is clear. Otherwise, writable only from a Secure, Privileged context.
bits : 1 - 1 (1 bit)
access : read-write
S : Determines the Secure/Non-secure (=1/0) status of addresses matching this region, if this region is enabled.
bits : 2 - 2 (1 bit)
access : read-write
ADDR : Limit address bits 31:5. Readable from any Privileged context, if and only if this region's S bit is clear, and MPU_CTRL_NS_HIDE_ADDR is clear. Otherwise readable only from a Secure, Privileged context.
bits : 5 - 31 (27 bit)
access : read-write
Base address register for MPU region 7. Writable only from a Secure, Privileged context.
address_offset : 0x53C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADDR : This MPU region matches addresses where addr[31:5] (the 27 most significant bits) are greater than or equal to BAR_ADDR, and less than or equal to LAR_ADDR.
Readable from any Privileged context, if and only if this region's S bit is clear, and MPU_CTRL_NS_HIDE_ADDR is clear. Otherwise readable only from a Secure, Privileged context.
bits : 5 - 31 (27 bit)
access : read-write
Alias for channel 1 READ_ADDR register
address_offset : 0x54 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH1_AL1_READ_ADDR :
bits : 0 - 31 (32 bit)
access : read-write
Limit address register for MPU region 7. Writable only from a Secure, Privileged context, with the exception of the P bit.
address_offset : 0x540 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : Region enable. If 1, any address within range specified by the base address (BAR_ADDR) and limit address (LAR_ADDR) has the attributes specified by S and P.
bits : 0 - 0 (1 bit)
access : read-write
P : Determines the Privileged/Unprivileged (=1/0) status of addresses matching this region, if this region is enabled. Writable from any Privileged context, if and only if the S bit is clear. Otherwise, writable only from a Secure, Privileged context.
bits : 1 - 1 (1 bit)
access : read-write
S : Determines the Secure/Non-secure (=1/0) status of addresses matching this region, if this region is enabled.
bits : 2 - 2 (1 bit)
access : read-write
ADDR : Limit address bits 31:5. Readable from any Privileged context, if and only if this region's S bit is clear, and MPU_CTRL_NS_HIDE_ADDR is clear. Otherwise readable only from a Secure, Privileged context.
bits : 5 - 31 (27 bit)
access : read-write
Alias for channel 1 WRITE_ADDR register
address_offset : 0x58 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH1_AL1_WRITE_ADDR :
bits : 0 - 31 (32 bit)
access : read-write
Alias for channel 1 TRANS_COUNT register
This is a trigger register (0xc). Writing a nonzero value will
reload the channel counter and start the channel.
address_offset : 0x5C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH1_AL1_TRANS_COUNT_TRIG :
bits : 0 - 31 (32 bit)
access : read-write
Alias for channel 1 CTRL register
address_offset : 0x60 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH1_AL2_CTRL :
bits : 0 - 31 (32 bit)
access : read-write
Alias for channel 1 TRANS_COUNT register
address_offset : 0x64 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH1_AL2_TRANS_COUNT :
bits : 0 - 31 (32 bit)
access : read-write
Alias for channel 1 READ_ADDR register
address_offset : 0x68 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH1_AL2_READ_ADDR :
bits : 0 - 31 (32 bit)
access : read-write
Alias for channel 1 WRITE_ADDR register
This is a trigger register (0xc). Writing a nonzero value will
reload the channel counter and start the channel.
address_offset : 0x6C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH1_AL2_WRITE_ADDR_TRIG :
bits : 0 - 31 (32 bit)
access : read-write
Alias for channel 1 CTRL register
address_offset : 0x70 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH1_AL3_CTRL :
bits : 0 - 31 (32 bit)
access : read-write
Alias for channel 1 WRITE_ADDR register
address_offset : 0x74 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH1_AL3_WRITE_ADDR :
bits : 0 - 31 (32 bit)
access : read-write
Alias for channel 1 TRANS_COUNT register
address_offset : 0x78 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH1_AL3_TRANS_COUNT :
bits : 0 - 31 (32 bit)
access : read-write
Alias for channel 1 READ_ADDR register
This is a trigger register (0xc). Writing a nonzero value will
reload the channel counter and start the channel.
address_offset : 0x7C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH1_AL3_READ_ADDR_TRIG :
bits : 0 - 31 (32 bit)
access : read-write
DMA Channel 0 Transfer Count
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
COUNT : 28-bit transfer count (256 million transfers maximum).
Program the number of bus transfers a channel will perform before halting. Note that, if transfers are larger than one byte in size, this is not equal to the number of bytes transferred (see CTRL_DATA_SIZE).
When the channel is active, reading this register shows the number of transfers remaining, updating automatically each time a write transfer completes.
Writing this register sets the RELOAD value for the transfer counter. Each time this channel is triggered, the RELOAD value is copied into the live transfer counter. The channel can be started multiple times, and will perform the same number of transfers each time, as programmed by most recent write.
The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a trigger, the written value is used immediately as the length of the new transfer sequence, as well as being written to RELOAD.
bits : 0 - 27 (28 bit)
access : read-write
MODE : When MODE is 0x0, the transfer count decrements with each transfer until 0, and then the channel triggers the next channel indicated by CTRL_CHAIN_TO.
When MODE is 0x1, the transfer count decrements with each transfer until 0, and then the channel re-triggers itself, in addition to the trigger indicated by CTRL_CHAIN_TO. This is useful for e.g. an endless ring-buffer DMA with periodic interrupts.
When MODE is 0xf, the transfer count does not decrement. The DMA channel performs an endless sequence of transfers, never triggering other channels or raising interrupts, until an ABORT is raised.
All other values are reserved.
bits : 28 - 31 (4 bit)
access : read-write
Enumeration:
0 : NORMAL
1 : TRIGGER_SELF
15 : ENDLESS
End of enumeration elements list.
DMA Channel 2 Read Address pointer
address_offset : 0x80 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH2_READ_ADDR : This register updates automatically each time a read completes. The current value is the next address to be read by this channel.
bits : 0 - 31 (32 bit)
access : read-write
Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake.
address_offset : 0x800 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH0_DBG_CTDREQ :
bits : 0 - 5 (6 bit)
access : read-write
Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer
address_offset : 0x804 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH0_DBG_TCR :
bits : 0 - 31 (32 bit)
access : read-only
DMA Channel 2 Write Address pointer
address_offset : 0x84 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH2_WRITE_ADDR : This register updates automatically each time a write completes. The current value is the next address to be written by this channel.
bits : 0 - 31 (32 bit)
access : read-write
Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake.
address_offset : 0x840 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH1_DBG_CTDREQ :
bits : 0 - 5 (6 bit)
access : read-write
Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer
address_offset : 0x844 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH1_DBG_TCR :
bits : 0 - 31 (32 bit)
access : read-only
DMA Channel 2 Transfer Count
address_offset : 0x88 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
COUNT : 28-bit transfer count (256 million transfers maximum).
Program the number of bus transfers a channel will perform before halting. Note that, if transfers are larger than one byte in size, this is not equal to the number of bytes transferred (see CTRL_DATA_SIZE).
When the channel is active, reading this register shows the number of transfers remaining, updating automatically each time a write transfer completes.
Writing this register sets the RELOAD value for the transfer counter. Each time this channel is triggered, the RELOAD value is copied into the live transfer counter. The channel can be started multiple times, and will perform the same number of transfers each time, as programmed by most recent write.
The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a trigger, the written value is used immediately as the length of the new transfer sequence, as well as being written to RELOAD.
bits : 0 - 27 (28 bit)
access : read-write
MODE : When MODE is 0x0, the transfer count decrements with each transfer until 0, and then the channel triggers the next channel indicated by CTRL_CHAIN_TO.
When MODE is 0x1, the transfer count decrements with each transfer until 0, and then the channel re-triggers itself, in addition to the trigger indicated by CTRL_CHAIN_TO. This is useful for e.g. an endless ring-buffer DMA with periodic interrupts.
When MODE is 0xf, the transfer count does not decrement. The DMA channel performs an endless sequence of transfers, never triggering other channels or raising interrupts, until an ABORT is raised.
All other values are reserved.
bits : 28 - 31 (4 bit)
access : read-write
Enumeration:
0 : NORMAL
1 : TRIGGER_SELF
15 : ENDLESS
End of enumeration elements list.
Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake.
address_offset : 0x880 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH2_DBG_CTDREQ :
bits : 0 - 5 (6 bit)
access : read-write
Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer
address_offset : 0x884 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH2_DBG_TCR :
bits : 0 - 31 (32 bit)
access : read-only
DMA Channel 2 Control and Status
address_offset : 0x8C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : DMA Channel Enable.
When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high)
bits : 0 - 0 (1 bit)
access : read-write
HIGH_PRIORITY : HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels.
This only affects the order in which the DMA schedules channels. The DMA's bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput.
bits : 1 - 1 (1 bit)
access : read-write
DATA_SIZE : Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer.
bits : 2 - 3 (2 bit)
access : read-write
Enumeration:
0 : SIZE_BYTE
1 : SIZE_HALFWORD
2 : SIZE_WORD
End of enumeration elements list.
INCR_READ : If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address.
Generally this should be disabled for peripheral-to-memory transfers.
bits : 4 - 4 (1 bit)
access : read-write
INCR_READ_REV : If 1, and INCR_READ is 1, the read address is decremented rather than incremented with each transfer.
If 1, and INCR_READ is 0, this otherwise-unused combination causes the read address to be incremented by twice the transfer size, i.e. skipping over alternate addresses.
bits : 5 - 5 (1 bit)
access : read-write
INCR_WRITE : If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address.
Generally this should be disabled for memory-to-peripheral transfers.
bits : 6 - 6 (1 bit)
access : read-write
INCR_WRITE_REV : If 1, and INCR_WRITE is 1, the write address is decremented rather than incremented with each transfer.
If 1, and INCR_WRITE is 0, this otherwise-unused combination causes the write address to be incremented by twice the transfer size, i.e. skipping over alternate addresses.
bits : 7 - 7 (1 bit)
access : read-write
RING_SIZE : Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned ring buffers.
Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL.
bits : 8 - 11 (4 bit)
access : read-write
Enumeration:
0 : RING_NONE
End of enumeration elements list.
RING_SEL : Select whether RING_SIZE applies to read or write addresses.
If 0, read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, write addresses are wrapped.
bits : 12 - 12 (1 bit)
access : read-write
CHAIN_TO : When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_.
Note this field resets to 0, so channels 1 and above will chain to channel 0 by default. Set this field to avoid this behaviour.
bits : 13 - 16 (4 bit)
access : read-write
TREQ_SEL : Select a Transfer Request signal.
The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system).
0x0 to 0x3a -> select DREQ n as TREQ
bits : 17 - 22 (6 bit)
access : read-write
Enumeration:
0 : PIO0_TX0
Select PIO0's TX FIFO 0 as TREQ
1 : PIO0_TX1
Select PIO0's TX FIFO 1 as TREQ
2 : PIO0_TX2
Select PIO0's TX FIFO 2 as TREQ
3 : PIO0_TX3
Select PIO0's TX FIFO 3 as TREQ
4 : PIO0_RX0
Select PIO0's RX FIFO 0 as TREQ
5 : PIO0_RX1
Select PIO0's RX FIFO 1 as TREQ
6 : PIO0_RX2
Select PIO0's RX FIFO 2 as TREQ
7 : PIO0_RX3
Select PIO0's RX FIFO 3 as TREQ
8 : PIO1_TX0
Select PIO1's TX FIFO 0 as TREQ
9 : PIO1_TX1
Select PIO1's TX FIFO 1 as TREQ
10 : PIO1_TX2
Select PIO1's TX FIFO 2 as TREQ
11 : PIO1_TX3
Select PIO1's TX FIFO 3 as TREQ
12 : PIO1_RX0
Select PIO1's RX FIFO 0 as TREQ
13 : PIO1_RX1
Select PIO1's RX FIFO 1 as TREQ
14 : PIO1_RX2
Select PIO1's RX FIFO 2 as TREQ
15 : PIO1_RX3
Select PIO1's RX FIFO 3 as TREQ
16 : PIO2_TX0
Select PIO2's TX FIFO 0 as TREQ
17 : PIO2_TX1
Select PIO2's TX FIFO 1 as TREQ
18 : PIO2_TX2
Select PIO2's TX FIFO 2 as TREQ
19 : PIO2_TX3
Select PIO2's TX FIFO 3 as TREQ
20 : PIO2_RX0
Select PIO2's RX FIFO 0 as TREQ
21 : PIO2_RX1
Select PIO2's RX FIFO 1 as TREQ
22 : PIO2_RX2
Select PIO2's RX FIFO 2 as TREQ
23 : PIO2_RX3
Select PIO2's RX FIFO 3 as TREQ
24 : SPI0_TX
Select SPI0's TX FIFO as TREQ
25 : SPI0_RX
Select SPI0's RX FIFO as TREQ
26 : SPI1_TX
Select SPI1's TX FIFO as TREQ
27 : SPI1_RX
Select SPI1's RX FIFO as TREQ
28 : UART0_TX
Select UART0's TX FIFO as TREQ
29 : UART0_RX
Select UART0's RX FIFO as TREQ
30 : UART1_TX
Select UART1's TX FIFO as TREQ
31 : UART1_RX
Select UART1's RX FIFO as TREQ
32 : PWM_WRAP0
Select PWM Counter 0's Wrap Value as TREQ
33 : PWM_WRAP1
Select PWM Counter 1's Wrap Value as TREQ
34 : PWM_WRAP2
Select PWM Counter 2's Wrap Value as TREQ
35 : PWM_WRAP3
Select PWM Counter 3's Wrap Value as TREQ
36 : PWM_WRAP4
Select PWM Counter 4's Wrap Value as TREQ
37 : PWM_WRAP5
Select PWM Counter 5's Wrap Value as TREQ
38 : PWM_WRAP6
Select PWM Counter 6's Wrap Value as TREQ
39 : PWM_WRAP7
Select PWM Counter 7's Wrap Value as TREQ
40 : PWM_WRAP8
Select PWM Counter 8's Wrap Value as TREQ
41 : PWM_WRAP9
Select PWM Counter 9's Wrap Value as TREQ
42 : PWM_WRAP10
Select PWM Counter 0's Wrap Value as TREQ
43 : PWM_WRAP11
Select PWM Counter 1's Wrap Value as TREQ
44 : I2C0_TX
Select I2C0's TX FIFO as TREQ
45 : I2C0_RX
Select I2C0's RX FIFO as TREQ
46 : I2C1_TX
Select I2C1's TX FIFO as TREQ
47 : I2C1_RX
Select I2C1's RX FIFO as TREQ
48 : ADC
Select the ADC as TREQ
49 : XIP_STREAM
Select the XIP Streaming FIFO as TREQ
50 : XIP_QMITX
Select XIP_QMITX as TREQ
51 : XIP_QMIRX
Select XIP_QMIRX as TREQ
52 : HSTX
Select HSTX as TREQ
53 : CORESIGHT
Select CORESIGHT as TREQ
54 : SHA256
Select SHA256 as TREQ
59 : TIMER0
Select Timer 0 as TREQ
60 : TIMER1
Select Timer 1 as TREQ
61 : TIMER2
Select Timer 2 as TREQ (Optional)
62 : TIMER3
Select Timer 3 as TREQ (Optional)
63 : PERMANENT
Permanent request, for unpaced transfers.
End of enumeration elements list.
IRQ_QUIET : In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain.
This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks.
bits : 23 - 23 (1 bit)
access : read-write
BSWAP : Apply byte-swap transformation to DMA data.
For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order.
bits : 24 - 24 (1 bit)
access : read-write
SNIFF_EN : If 1, this channel's data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected.
This allows checksum to be enabled or disabled on a per-control- block basis.
bits : 25 - 25 (1 bit)
access : read-write
BUSY : This flag goes high when the channel starts a new transfer sequence, and low when the last transfer of that sequence completes. Clearing EN while BUSY is high pauses the channel, and BUSY will stay high while paused.
To terminate a sequence early (and clear the BUSY flag), see CHAN_ABORT.
bits : 26 - 26 (1 bit)
access : read-only
WRITE_ERROR : If 1, the channel received a write bus error. Write one to clear.
WRITE_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 5 transfers later)
bits : 29 - 29 (1 bit)
access : read-write
READ_ERROR : If 1, the channel received a read bus error. Write one to clear.
READ_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 3 transfers later)
bits : 30 - 30 (1 bit)
access : read-write
AHB_ERROR : Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel halts when it encounters any bus error, and always raises its channel IRQ flag.
bits : 31 - 31 (1 bit)
access : read-only
Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake.
address_offset : 0x8C0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH3_DBG_CTDREQ :
bits : 0 - 5 (6 bit)
access : read-write
Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer
address_offset : 0x8C4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH3_DBG_TCR :
bits : 0 - 31 (32 bit)
access : read-only
Alias for channel 2 CTRL register
address_offset : 0x90 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH2_AL1_CTRL :
bits : 0 - 31 (32 bit)
access : read-write
Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake.
address_offset : 0x900 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH4_DBG_CTDREQ :
bits : 0 - 5 (6 bit)
access : read-write
Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer
address_offset : 0x904 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH4_DBG_TCR :
bits : 0 - 31 (32 bit)
access : read-only
Alias for channel 2 READ_ADDR register
address_offset : 0x94 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH2_AL1_READ_ADDR :
bits : 0 - 31 (32 bit)
access : read-write
Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake.
address_offset : 0x940 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH5_DBG_CTDREQ :
bits : 0 - 5 (6 bit)
access : read-write
Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer
address_offset : 0x944 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH5_DBG_TCR :
bits : 0 - 31 (32 bit)
access : read-only
Alias for channel 2 WRITE_ADDR register
address_offset : 0x98 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH2_AL1_WRITE_ADDR :
bits : 0 - 31 (32 bit)
access : read-write
Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake.
address_offset : 0x980 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH6_DBG_CTDREQ :
bits : 0 - 5 (6 bit)
access : read-write
Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer
address_offset : 0x984 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH6_DBG_TCR :
bits : 0 - 31 (32 bit)
access : read-only
Alias for channel 2 TRANS_COUNT register
This is a trigger register (0xc). Writing a nonzero value will
reload the channel counter and start the channel.
address_offset : 0x9C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH2_AL1_TRANS_COUNT_TRIG :
bits : 0 - 31 (32 bit)
access : read-write
Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake.
address_offset : 0x9C0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH7_DBG_CTDREQ :
bits : 0 - 5 (6 bit)
access : read-write
Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer
address_offset : 0x9C4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH7_DBG_TCR :
bits : 0 - 31 (32 bit)
access : read-only
Alias for channel 2 CTRL register
address_offset : 0xA0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH2_AL2_CTRL :
bits : 0 - 31 (32 bit)
access : read-write
Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake.
address_offset : 0xA00 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH8_DBG_CTDREQ :
bits : 0 - 5 (6 bit)
access : read-write
Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer
address_offset : 0xA04 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH8_DBG_TCR :
bits : 0 - 31 (32 bit)
access : read-only
Alias for channel 2 TRANS_COUNT register
address_offset : 0xA4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH2_AL2_TRANS_COUNT :
bits : 0 - 31 (32 bit)
access : read-write
Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake.
address_offset : 0xA40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH9_DBG_CTDREQ :
bits : 0 - 5 (6 bit)
access : read-write
Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer
address_offset : 0xA44 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH9_DBG_TCR :
bits : 0 - 31 (32 bit)
access : read-only
Alias for channel 2 READ_ADDR register
address_offset : 0xA8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH2_AL2_READ_ADDR :
bits : 0 - 31 (32 bit)
access : read-write
Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake.
address_offset : 0xA80 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH10_DBG_CTDREQ :
bits : 0 - 5 (6 bit)
access : read-write
Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer
address_offset : 0xA84 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH10_DBG_TCR :
bits : 0 - 31 (32 bit)
access : read-only
Alias for channel 2 WRITE_ADDR register
This is a trigger register (0xc). Writing a nonzero value will
reload the channel counter and start the channel.
address_offset : 0xAC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH2_AL2_WRITE_ADDR_TRIG :
bits : 0 - 31 (32 bit)
access : read-write
Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake.
address_offset : 0xAC0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH11_DBG_CTDREQ :
bits : 0 - 5 (6 bit)
access : read-write
Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer
address_offset : 0xAC4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH11_DBG_TCR :
bits : 0 - 31 (32 bit)
access : read-only
Alias for channel 2 CTRL register
address_offset : 0xB0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH2_AL3_CTRL :
bits : 0 - 31 (32 bit)
access : read-write
Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake.
address_offset : 0xB00 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH12_DBG_CTDREQ :
bits : 0 - 5 (6 bit)
access : read-write
Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer
address_offset : 0xB04 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH12_DBG_TCR :
bits : 0 - 31 (32 bit)
access : read-only
Alias for channel 2 WRITE_ADDR register
address_offset : 0xB4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH2_AL3_WRITE_ADDR :
bits : 0 - 31 (32 bit)
access : read-write
Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake.
address_offset : 0xB40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH13_DBG_CTDREQ :
bits : 0 - 5 (6 bit)
access : read-write
Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer
address_offset : 0xB44 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH13_DBG_TCR :
bits : 0 - 31 (32 bit)
access : read-only
Alias for channel 2 TRANS_COUNT register
address_offset : 0xB8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH2_AL3_TRANS_COUNT :
bits : 0 - 31 (32 bit)
access : read-write
Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake.
address_offset : 0xB80 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH14_DBG_CTDREQ :
bits : 0 - 5 (6 bit)
access : read-write
Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer
address_offset : 0xB84 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH14_DBG_TCR :
bits : 0 - 31 (32 bit)
access : read-only
Alias for channel 2 READ_ADDR register
This is a trigger register (0xc). Writing a nonzero value will
reload the channel counter and start the channel.
address_offset : 0xBC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH2_AL3_READ_ADDR_TRIG :
bits : 0 - 31 (32 bit)
access : read-write
Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake.
address_offset : 0xBC0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH15_DBG_CTDREQ :
bits : 0 - 5 (6 bit)
access : read-write
Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer
address_offset : 0xBC4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH15_DBG_TCR :
bits : 0 - 31 (32 bit)
access : read-only
DMA Channel 0 Control and Status
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : DMA Channel Enable.
When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high)
bits : 0 - 0 (1 bit)
access : read-write
HIGH_PRIORITY : HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels.
This only affects the order in which the DMA schedules channels. The DMA's bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput.
bits : 1 - 1 (1 bit)
access : read-write
DATA_SIZE : Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer.
bits : 2 - 3 (2 bit)
access : read-write
Enumeration:
0 : SIZE_BYTE
1 : SIZE_HALFWORD
2 : SIZE_WORD
End of enumeration elements list.
INCR_READ : If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address.
Generally this should be disabled for peripheral-to-memory transfers.
bits : 4 - 4 (1 bit)
access : read-write
INCR_READ_REV : If 1, and INCR_READ is 1, the read address is decremented rather than incremented with each transfer.
If 1, and INCR_READ is 0, this otherwise-unused combination causes the read address to be incremented by twice the transfer size, i.e. skipping over alternate addresses.
bits : 5 - 5 (1 bit)
access : read-write
INCR_WRITE : If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address.
Generally this should be disabled for memory-to-peripheral transfers.
bits : 6 - 6 (1 bit)
access : read-write
INCR_WRITE_REV : If 1, and INCR_WRITE is 1, the write address is decremented rather than incremented with each transfer.
If 1, and INCR_WRITE is 0, this otherwise-unused combination causes the write address to be incremented by twice the transfer size, i.e. skipping over alternate addresses.
bits : 7 - 7 (1 bit)
access : read-write
RING_SIZE : Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned ring buffers.
Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL.
bits : 8 - 11 (4 bit)
access : read-write
Enumeration:
0 : RING_NONE
End of enumeration elements list.
RING_SEL : Select whether RING_SIZE applies to read or write addresses.
If 0, read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, write addresses are wrapped.
bits : 12 - 12 (1 bit)
access : read-write
CHAIN_TO : When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_.
Note this field resets to 0, so channels 1 and above will chain to channel 0 by default. Set this field to avoid this behaviour.
bits : 13 - 16 (4 bit)
access : read-write
TREQ_SEL : Select a Transfer Request signal.
The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system).
0x0 to 0x3a -> select DREQ n as TREQ
bits : 17 - 22 (6 bit)
access : read-write
Enumeration:
0 : PIO0_TX0
Select PIO0's TX FIFO 0 as TREQ
1 : PIO0_TX1
Select PIO0's TX FIFO 1 as TREQ
2 : PIO0_TX2
Select PIO0's TX FIFO 2 as TREQ
3 : PIO0_TX3
Select PIO0's TX FIFO 3 as TREQ
4 : PIO0_RX0
Select PIO0's RX FIFO 0 as TREQ
5 : PIO0_RX1
Select PIO0's RX FIFO 1 as TREQ
6 : PIO0_RX2
Select PIO0's RX FIFO 2 as TREQ
7 : PIO0_RX3
Select PIO0's RX FIFO 3 as TREQ
8 : PIO1_TX0
Select PIO1's TX FIFO 0 as TREQ
9 : PIO1_TX1
Select PIO1's TX FIFO 1 as TREQ
10 : PIO1_TX2
Select PIO1's TX FIFO 2 as TREQ
11 : PIO1_TX3
Select PIO1's TX FIFO 3 as TREQ
12 : PIO1_RX0
Select PIO1's RX FIFO 0 as TREQ
13 : PIO1_RX1
Select PIO1's RX FIFO 1 as TREQ
14 : PIO1_RX2
Select PIO1's RX FIFO 2 as TREQ
15 : PIO1_RX3
Select PIO1's RX FIFO 3 as TREQ
16 : PIO2_TX0
Select PIO2's TX FIFO 0 as TREQ
17 : PIO2_TX1
Select PIO2's TX FIFO 1 as TREQ
18 : PIO2_TX2
Select PIO2's TX FIFO 2 as TREQ
19 : PIO2_TX3
Select PIO2's TX FIFO 3 as TREQ
20 : PIO2_RX0
Select PIO2's RX FIFO 0 as TREQ
21 : PIO2_RX1
Select PIO2's RX FIFO 1 as TREQ
22 : PIO2_RX2
Select PIO2's RX FIFO 2 as TREQ
23 : PIO2_RX3
Select PIO2's RX FIFO 3 as TREQ
24 : SPI0_TX
Select SPI0's TX FIFO as TREQ
25 : SPI0_RX
Select SPI0's RX FIFO as TREQ
26 : SPI1_TX
Select SPI1's TX FIFO as TREQ
27 : SPI1_RX
Select SPI1's RX FIFO as TREQ
28 : UART0_TX
Select UART0's TX FIFO as TREQ
29 : UART0_RX
Select UART0's RX FIFO as TREQ
30 : UART1_TX
Select UART1's TX FIFO as TREQ
31 : UART1_RX
Select UART1's RX FIFO as TREQ
32 : PWM_WRAP0
Select PWM Counter 0's Wrap Value as TREQ
33 : PWM_WRAP1
Select PWM Counter 1's Wrap Value as TREQ
34 : PWM_WRAP2
Select PWM Counter 2's Wrap Value as TREQ
35 : PWM_WRAP3
Select PWM Counter 3's Wrap Value as TREQ
36 : PWM_WRAP4
Select PWM Counter 4's Wrap Value as TREQ
37 : PWM_WRAP5
Select PWM Counter 5's Wrap Value as TREQ
38 : PWM_WRAP6
Select PWM Counter 6's Wrap Value as TREQ
39 : PWM_WRAP7
Select PWM Counter 7's Wrap Value as TREQ
40 : PWM_WRAP8
Select PWM Counter 8's Wrap Value as TREQ
41 : PWM_WRAP9
Select PWM Counter 9's Wrap Value as TREQ
42 : PWM_WRAP10
Select PWM Counter 0's Wrap Value as TREQ
43 : PWM_WRAP11
Select PWM Counter 1's Wrap Value as TREQ
44 : I2C0_TX
Select I2C0's TX FIFO as TREQ
45 : I2C0_RX
Select I2C0's RX FIFO as TREQ
46 : I2C1_TX
Select I2C1's TX FIFO as TREQ
47 : I2C1_RX
Select I2C1's RX FIFO as TREQ
48 : ADC
Select the ADC as TREQ
49 : XIP_STREAM
Select the XIP Streaming FIFO as TREQ
50 : XIP_QMITX
Select XIP_QMITX as TREQ
51 : XIP_QMIRX
Select XIP_QMIRX as TREQ
52 : HSTX
Select HSTX as TREQ
53 : CORESIGHT
Select CORESIGHT as TREQ
54 : SHA256
Select SHA256 as TREQ
59 : TIMER0
Select Timer 0 as TREQ
60 : TIMER1
Select Timer 1 as TREQ
61 : TIMER2
Select Timer 2 as TREQ (Optional)
62 : TIMER3
Select Timer 3 as TREQ (Optional)
63 : PERMANENT
Permanent request, for unpaced transfers.
End of enumeration elements list.
IRQ_QUIET : In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain.
This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks.
bits : 23 - 23 (1 bit)
access : read-write
BSWAP : Apply byte-swap transformation to DMA data.
For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order.
bits : 24 - 24 (1 bit)
access : read-write
SNIFF_EN : If 1, this channel's data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected.
This allows checksum to be enabled or disabled on a per-control- block basis.
bits : 25 - 25 (1 bit)
access : read-write
BUSY : This flag goes high when the channel starts a new transfer sequence, and low when the last transfer of that sequence completes. Clearing EN while BUSY is high pauses the channel, and BUSY will stay high while paused.
To terminate a sequence early (and clear the BUSY flag), see CHAN_ABORT.
bits : 26 - 26 (1 bit)
access : read-only
WRITE_ERROR : If 1, the channel received a write bus error. Write one to clear.
WRITE_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 5 transfers later)
bits : 29 - 29 (1 bit)
access : read-write
READ_ERROR : If 1, the channel received a read bus error. Write one to clear.
READ_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 3 transfers later)
bits : 30 - 30 (1 bit)
access : read-write
AHB_ERROR : Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel halts when it encounters any bus error, and always raises its channel IRQ flag.
bits : 31 - 31 (1 bit)
access : read-only
DMA Channel 3 Read Address pointer
address_offset : 0xC0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH3_READ_ADDR : This register updates automatically each time a read completes. The current value is the next address to be read by this channel.
bits : 0 - 31 (32 bit)
access : read-write
DMA Channel 3 Write Address pointer
address_offset : 0xC4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH3_WRITE_ADDR : This register updates automatically each time a write completes. The current value is the next address to be written by this channel.
bits : 0 - 31 (32 bit)
access : read-write
DMA Channel 3 Transfer Count
address_offset : 0xC8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
COUNT : 28-bit transfer count (256 million transfers maximum).
Program the number of bus transfers a channel will perform before halting. Note that, if transfers are larger than one byte in size, this is not equal to the number of bytes transferred (see CTRL_DATA_SIZE).
When the channel is active, reading this register shows the number of transfers remaining, updating automatically each time a write transfer completes.
Writing this register sets the RELOAD value for the transfer counter. Each time this channel is triggered, the RELOAD value is copied into the live transfer counter. The channel can be started multiple times, and will perform the same number of transfers each time, as programmed by most recent write.
The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a trigger, the written value is used immediately as the length of the new transfer sequence, as well as being written to RELOAD.
bits : 0 - 27 (28 bit)
access : read-write
MODE : When MODE is 0x0, the transfer count decrements with each transfer until 0, and then the channel triggers the next channel indicated by CTRL_CHAIN_TO.
When MODE is 0x1, the transfer count decrements with each transfer until 0, and then the channel re-triggers itself, in addition to the trigger indicated by CTRL_CHAIN_TO. This is useful for e.g. an endless ring-buffer DMA with periodic interrupts.
When MODE is 0xf, the transfer count does not decrement. The DMA channel performs an endless sequence of transfers, never triggering other channels or raising interrupts, until an ABORT is raised.
All other values are reserved.
bits : 28 - 31 (4 bit)
access : read-write
Enumeration:
0 : NORMAL
1 : TRIGGER_SELF
15 : ENDLESS
End of enumeration elements list.
DMA Channel 3 Control and Status
address_offset : 0xCC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : DMA Channel Enable.
When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high)
bits : 0 - 0 (1 bit)
access : read-write
HIGH_PRIORITY : HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels.
This only affects the order in which the DMA schedules channels. The DMA's bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput.
bits : 1 - 1 (1 bit)
access : read-write
DATA_SIZE : Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer.
bits : 2 - 3 (2 bit)
access : read-write
Enumeration:
0 : SIZE_BYTE
1 : SIZE_HALFWORD
2 : SIZE_WORD
End of enumeration elements list.
INCR_READ : If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address.
Generally this should be disabled for peripheral-to-memory transfers.
bits : 4 - 4 (1 bit)
access : read-write
INCR_READ_REV : If 1, and INCR_READ is 1, the read address is decremented rather than incremented with each transfer.
If 1, and INCR_READ is 0, this otherwise-unused combination causes the read address to be incremented by twice the transfer size, i.e. skipping over alternate addresses.
bits : 5 - 5 (1 bit)
access : read-write
INCR_WRITE : If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address.
Generally this should be disabled for memory-to-peripheral transfers.
bits : 6 - 6 (1 bit)
access : read-write
INCR_WRITE_REV : If 1, and INCR_WRITE is 1, the write address is decremented rather than incremented with each transfer.
If 1, and INCR_WRITE is 0, this otherwise-unused combination causes the write address to be incremented by twice the transfer size, i.e. skipping over alternate addresses.
bits : 7 - 7 (1 bit)
access : read-write
RING_SIZE : Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned ring buffers.
Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL.
bits : 8 - 11 (4 bit)
access : read-write
Enumeration:
0 : RING_NONE
End of enumeration elements list.
RING_SEL : Select whether RING_SIZE applies to read or write addresses.
If 0, read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, write addresses are wrapped.
bits : 12 - 12 (1 bit)
access : read-write
CHAIN_TO : When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_.
Note this field resets to 0, so channels 1 and above will chain to channel 0 by default. Set this field to avoid this behaviour.
bits : 13 - 16 (4 bit)
access : read-write
TREQ_SEL : Select a Transfer Request signal.
The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system).
0x0 to 0x3a -> select DREQ n as TREQ
bits : 17 - 22 (6 bit)
access : read-write
Enumeration:
0 : PIO0_TX0
Select PIO0's TX FIFO 0 as TREQ
1 : PIO0_TX1
Select PIO0's TX FIFO 1 as TREQ
2 : PIO0_TX2
Select PIO0's TX FIFO 2 as TREQ
3 : PIO0_TX3
Select PIO0's TX FIFO 3 as TREQ
4 : PIO0_RX0
Select PIO0's RX FIFO 0 as TREQ
5 : PIO0_RX1
Select PIO0's RX FIFO 1 as TREQ
6 : PIO0_RX2
Select PIO0's RX FIFO 2 as TREQ
7 : PIO0_RX3
Select PIO0's RX FIFO 3 as TREQ
8 : PIO1_TX0
Select PIO1's TX FIFO 0 as TREQ
9 : PIO1_TX1
Select PIO1's TX FIFO 1 as TREQ
10 : PIO1_TX2
Select PIO1's TX FIFO 2 as TREQ
11 : PIO1_TX3
Select PIO1's TX FIFO 3 as TREQ
12 : PIO1_RX0
Select PIO1's RX FIFO 0 as TREQ
13 : PIO1_RX1
Select PIO1's RX FIFO 1 as TREQ
14 : PIO1_RX2
Select PIO1's RX FIFO 2 as TREQ
15 : PIO1_RX3
Select PIO1's RX FIFO 3 as TREQ
16 : PIO2_TX0
Select PIO2's TX FIFO 0 as TREQ
17 : PIO2_TX1
Select PIO2's TX FIFO 1 as TREQ
18 : PIO2_TX2
Select PIO2's TX FIFO 2 as TREQ
19 : PIO2_TX3
Select PIO2's TX FIFO 3 as TREQ
20 : PIO2_RX0
Select PIO2's RX FIFO 0 as TREQ
21 : PIO2_RX1
Select PIO2's RX FIFO 1 as TREQ
22 : PIO2_RX2
Select PIO2's RX FIFO 2 as TREQ
23 : PIO2_RX3
Select PIO2's RX FIFO 3 as TREQ
24 : SPI0_TX
Select SPI0's TX FIFO as TREQ
25 : SPI0_RX
Select SPI0's RX FIFO as TREQ
26 : SPI1_TX
Select SPI1's TX FIFO as TREQ
27 : SPI1_RX
Select SPI1's RX FIFO as TREQ
28 : UART0_TX
Select UART0's TX FIFO as TREQ
29 : UART0_RX
Select UART0's RX FIFO as TREQ
30 : UART1_TX
Select UART1's TX FIFO as TREQ
31 : UART1_RX
Select UART1's RX FIFO as TREQ
32 : PWM_WRAP0
Select PWM Counter 0's Wrap Value as TREQ
33 : PWM_WRAP1
Select PWM Counter 1's Wrap Value as TREQ
34 : PWM_WRAP2
Select PWM Counter 2's Wrap Value as TREQ
35 : PWM_WRAP3
Select PWM Counter 3's Wrap Value as TREQ
36 : PWM_WRAP4
Select PWM Counter 4's Wrap Value as TREQ
37 : PWM_WRAP5
Select PWM Counter 5's Wrap Value as TREQ
38 : PWM_WRAP6
Select PWM Counter 6's Wrap Value as TREQ
39 : PWM_WRAP7
Select PWM Counter 7's Wrap Value as TREQ
40 : PWM_WRAP8
Select PWM Counter 8's Wrap Value as TREQ
41 : PWM_WRAP9
Select PWM Counter 9's Wrap Value as TREQ
42 : PWM_WRAP10
Select PWM Counter 0's Wrap Value as TREQ
43 : PWM_WRAP11
Select PWM Counter 1's Wrap Value as TREQ
44 : I2C0_TX
Select I2C0's TX FIFO as TREQ
45 : I2C0_RX
Select I2C0's RX FIFO as TREQ
46 : I2C1_TX
Select I2C1's TX FIFO as TREQ
47 : I2C1_RX
Select I2C1's RX FIFO as TREQ
48 : ADC
Select the ADC as TREQ
49 : XIP_STREAM
Select the XIP Streaming FIFO as TREQ
50 : XIP_QMITX
Select XIP_QMITX as TREQ
51 : XIP_QMIRX
Select XIP_QMIRX as TREQ
52 : HSTX
Select HSTX as TREQ
53 : CORESIGHT
Select CORESIGHT as TREQ
54 : SHA256
Select SHA256 as TREQ
59 : TIMER0
Select Timer 0 as TREQ
60 : TIMER1
Select Timer 1 as TREQ
61 : TIMER2
Select Timer 2 as TREQ (Optional)
62 : TIMER3
Select Timer 3 as TREQ (Optional)
63 : PERMANENT
Permanent request, for unpaced transfers.
End of enumeration elements list.
IRQ_QUIET : In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain.
This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks.
bits : 23 - 23 (1 bit)
access : read-write
BSWAP : Apply byte-swap transformation to DMA data.
For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order.
bits : 24 - 24 (1 bit)
access : read-write
SNIFF_EN : If 1, this channel's data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected.
This allows checksum to be enabled or disabled on a per-control- block basis.
bits : 25 - 25 (1 bit)
access : read-write
BUSY : This flag goes high when the channel starts a new transfer sequence, and low when the last transfer of that sequence completes. Clearing EN while BUSY is high pauses the channel, and BUSY will stay high while paused.
To terminate a sequence early (and clear the BUSY flag), see CHAN_ABORT.
bits : 26 - 26 (1 bit)
access : read-only
WRITE_ERROR : If 1, the channel received a write bus error. Write one to clear.
WRITE_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 5 transfers later)
bits : 29 - 29 (1 bit)
access : read-write
READ_ERROR : If 1, the channel received a read bus error. Write one to clear.
READ_ADDR shows the approximate address where the bus error was encountered (will not be earlier, or more than 3 transfers later)
bits : 30 - 30 (1 bit)
access : read-write
AHB_ERROR : Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel halts when it encounters any bus error, and always raises its channel IRQ flag.
bits : 31 - 31 (1 bit)
access : read-only
Alias for channel 3 CTRL register
address_offset : 0xD0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH3_AL1_CTRL :
bits : 0 - 31 (32 bit)
access : read-write
Alias for channel 3 READ_ADDR register
address_offset : 0xD4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH3_AL1_READ_ADDR :
bits : 0 - 31 (32 bit)
access : read-write
Alias for channel 3 WRITE_ADDR register
address_offset : 0xD8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH3_AL1_WRITE_ADDR :
bits : 0 - 31 (32 bit)
access : read-write
Alias for channel 3 TRANS_COUNT register
This is a trigger register (0xc). Writing a nonzero value will
reload the channel counter and start the channel.
address_offset : 0xDC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH3_AL1_TRANS_COUNT_TRIG :
bits : 0 - 31 (32 bit)
access : read-write
Alias for channel 3 CTRL register
address_offset : 0xE0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH3_AL2_CTRL :
bits : 0 - 31 (32 bit)
access : read-write
Alias for channel 3 TRANS_COUNT register
address_offset : 0xE4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH3_AL2_TRANS_COUNT :
bits : 0 - 31 (32 bit)
access : read-write
Alias for channel 3 READ_ADDR register
address_offset : 0xE8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH3_AL2_READ_ADDR :
bits : 0 - 31 (32 bit)
access : read-write
Alias for channel 3 WRITE_ADDR register
This is a trigger register (0xc). Writing a nonzero value will
reload the channel counter and start the channel.
address_offset : 0xEC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH3_AL2_WRITE_ADDR_TRIG :
bits : 0 - 31 (32 bit)
access : read-write
Alias for channel 3 CTRL register
address_offset : 0xF0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH3_AL3_CTRL :
bits : 0 - 31 (32 bit)
access : read-write
Alias for channel 3 WRITE_ADDR register
address_offset : 0xF4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH3_AL3_WRITE_ADDR :
bits : 0 - 31 (32 bit)
access : read-write
Alias for channel 3 TRANS_COUNT register
address_offset : 0xF8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH3_AL3_TRANS_COUNT :
bits : 0 - 31 (32 bit)
access : read-write
Alias for channel 3 READ_ADDR register
This is a trigger register (0xc). Writing a nonzero value will
reload the channel counter and start the channel.
address_offset : 0xFC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CH3_AL3_READ_ADDR_TRIG :
bits : 0 - 31 (32 bit)
access : read-write
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