PWM

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x110 byte (0x0)
mem_usage : registers
protection :

Registers

CH0_CSR

CH0_TOP

IRQ0_INTS

IRQ1_INTE

IRQ1_INTF

IRQ1_INTS

CH1_CSR

CH1_DIV

CH1_CTR

CH1_CC

CH1_TOP

CH2_CSR

CH2_DIV

CH2_CTR

CH2_CC

CH2_TOP

CH3_CSR

CH0_DIV

CH3_DIV

CH3_CTR

CH3_CC

CH3_TOP

CH4_CSR

CH4_DIV

CH4_CTR

CH4_CC

CH4_TOP

CH5_CSR

CH5_DIV

CH5_CTR

CH5_CC

CH5_TOP

CH6_CSR

CH6_DIV

CH0_CTR

CH6_CTR

CH6_CC

CH6_TOP

CH7_CSR

CH7_DIV

CH7_CTR

CH7_CC

CH7_TOP

CH8_CSR

CH8_DIV

CH8_CTR

CH8_CC

CH8_TOP

CH9_CSR

CH9_DIV

CH9_CTR

CH0_CC

CH9_CC

CH9_TOP

CH10_CSR

CH10_DIV

CH10_CTR

CH10_CC

CH10_TOP

CH11_CSR

CH11_DIV

CH11_CTR

CH11_CC

CH11_TOP

EN

INTR

IRQ0_INTE

IRQ0_INTF


CH0_CSR

Control and status register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH0_CSR CH0_CSR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EN PH_CORRECT A_INV B_INV DIVMODE PH_RET PH_ADV

EN : Enable the PWM channel.
bits : 0 - 0 (1 bit)
access : read-write

PH_CORRECT : 1: Enable phase-correct modulation. 0: Trailing-edge
bits : 1 - 1 (1 bit)
access : read-write

A_INV : Invert output A
bits : 2 - 2 (1 bit)
access : read-write

B_INV : Invert output B
bits : 3 - 3 (1 bit)
access : read-write

DIVMODE :
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : div

Free-running counting at rate dictated by fractional divider

1 : level

Fractional divider operation is gated by the PWM B pin.

2 : rise

Counter advances with each rising edge of the PWM B pin.

3 : fall

Counter advances with each falling edge of the PWM B pin.

End of enumeration elements list.

PH_RET : Retard the phase of the counter by 1 count, while it is running. Self-clearing. Write a 1, and poll until low. Counter must be running.
bits : 6 - 6 (1 bit)
access : write-only

PH_ADV : Advance the phase of the counter by 1 count, while it is running. Self-clearing. Write a 1, and poll until low. Counter must be running at less than full speed (div_int + div_frac / 16 > 1)
bits : 7 - 7 (1 bit)
access : write-only


CH0_TOP

Counter wrap value
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH0_TOP CH0_TOP read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CH0_TOP

CH0_TOP :
bits : 0 - 15 (16 bit)
access : read-write


IRQ0_INTS

Interrupt status after masking & forcing for irq0
address_offset : 0x100 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IRQ0_INTS IRQ0_INTS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CH0 CH1 CH2 CH3 CH4 CH5 CH6 CH7 CH8 CH9 CH10 CH11

CH0 :
bits : 0 - 0 (1 bit)
access : read-only

CH1 :
bits : 1 - 1 (1 bit)
access : read-only

CH2 :
bits : 2 - 2 (1 bit)
access : read-only

CH3 :
bits : 3 - 3 (1 bit)
access : read-only

CH4 :
bits : 4 - 4 (1 bit)
access : read-only

CH5 :
bits : 5 - 5 (1 bit)
access : read-only

CH6 :
bits : 6 - 6 (1 bit)
access : read-only

CH7 :
bits : 7 - 7 (1 bit)
access : read-only

CH8 :
bits : 8 - 8 (1 bit)
access : read-only

CH9 :
bits : 9 - 9 (1 bit)
access : read-only

CH10 :
bits : 10 - 10 (1 bit)
access : read-only

CH11 :
bits : 11 - 11 (1 bit)
access : read-only


IRQ1_INTE

Interrupt Enable for irq1
address_offset : 0x104 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IRQ1_INTE IRQ1_INTE read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CH0 CH1 CH2 CH3 CH4 CH5 CH6 CH7 CH8 CH9 CH10 CH11

CH0 :
bits : 0 - 0 (1 bit)
access : read-write

CH1 :
bits : 1 - 1 (1 bit)
access : read-write

CH2 :
bits : 2 - 2 (1 bit)
access : read-write

CH3 :
bits : 3 - 3 (1 bit)
access : read-write

CH4 :
bits : 4 - 4 (1 bit)
access : read-write

CH5 :
bits : 5 - 5 (1 bit)
access : read-write

CH6 :
bits : 6 - 6 (1 bit)
access : read-write

CH7 :
bits : 7 - 7 (1 bit)
access : read-write

CH8 :
bits : 8 - 8 (1 bit)
access : read-write

CH9 :
bits : 9 - 9 (1 bit)
access : read-write

CH10 :
bits : 10 - 10 (1 bit)
access : read-write

CH11 :
bits : 11 - 11 (1 bit)
access : read-write


IRQ1_INTF

Interrupt Force for irq1
address_offset : 0x108 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IRQ1_INTF IRQ1_INTF read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CH0 CH1 CH2 CH3 CH4 CH5 CH6 CH7 CH8 CH9 CH10 CH11

CH0 :
bits : 0 - 0 (1 bit)
access : read-write

CH1 :
bits : 1 - 1 (1 bit)
access : read-write

CH2 :
bits : 2 - 2 (1 bit)
access : read-write

CH3 :
bits : 3 - 3 (1 bit)
access : read-write

CH4 :
bits : 4 - 4 (1 bit)
access : read-write

CH5 :
bits : 5 - 5 (1 bit)
access : read-write

CH6 :
bits : 6 - 6 (1 bit)
access : read-write

CH7 :
bits : 7 - 7 (1 bit)
access : read-write

CH8 :
bits : 8 - 8 (1 bit)
access : read-write

CH9 :
bits : 9 - 9 (1 bit)
access : read-write

CH10 :
bits : 10 - 10 (1 bit)
access : read-write

CH11 :
bits : 11 - 11 (1 bit)
access : read-write


IRQ1_INTS

Interrupt status after masking & forcing for irq1
address_offset : 0x10C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IRQ1_INTS IRQ1_INTS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CH0 CH1 CH2 CH3 CH4 CH5 CH6 CH7 CH8 CH9 CH10 CH11

CH0 :
bits : 0 - 0 (1 bit)
access : read-only

CH1 :
bits : 1 - 1 (1 bit)
access : read-only

CH2 :
bits : 2 - 2 (1 bit)
access : read-only

CH3 :
bits : 3 - 3 (1 bit)
access : read-only

CH4 :
bits : 4 - 4 (1 bit)
access : read-only

CH5 :
bits : 5 - 5 (1 bit)
access : read-only

CH6 :
bits : 6 - 6 (1 bit)
access : read-only

CH7 :
bits : 7 - 7 (1 bit)
access : read-only

CH8 :
bits : 8 - 8 (1 bit)
access : read-only

CH9 :
bits : 9 - 9 (1 bit)
access : read-only

CH10 :
bits : 10 - 10 (1 bit)
access : read-only

CH11 :
bits : 11 - 11 (1 bit)
access : read-only


CH1_CSR

Control and status register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH1_CSR CH1_CSR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EN PH_CORRECT A_INV B_INV DIVMODE PH_RET PH_ADV

EN : Enable the PWM channel.
bits : 0 - 0 (1 bit)
access : read-write

PH_CORRECT : 1: Enable phase-correct modulation. 0: Trailing-edge
bits : 1 - 1 (1 bit)
access : read-write

A_INV : Invert output A
bits : 2 - 2 (1 bit)
access : read-write

B_INV : Invert output B
bits : 3 - 3 (1 bit)
access : read-write

DIVMODE :
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : div

Free-running counting at rate dictated by fractional divider

1 : level

Fractional divider operation is gated by the PWM B pin.

2 : rise

Counter advances with each rising edge of the PWM B pin.

3 : fall

Counter advances with each falling edge of the PWM B pin.

End of enumeration elements list.

PH_RET : Retard the phase of the counter by 1 count, while it is running. Self-clearing. Write a 1, and poll until low. Counter must be running.
bits : 6 - 6 (1 bit)
access : write-only

PH_ADV : Advance the phase of the counter by 1 count, while it is running. Self-clearing. Write a 1, and poll until low. Counter must be running at less than full speed (div_int + div_frac / 16 > 1)
bits : 7 - 7 (1 bit)
access : write-only


CH1_DIV

INT and FRAC form a fixed-point fractional number. Counting rate is system clock frequency divided by this number. Fractional division uses simple 1st-order sigma-delta.
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH1_DIV CH1_DIV read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FRAC INT

FRAC :
bits : 0 - 3 (4 bit)
access : read-write

INT :
bits : 4 - 11 (8 bit)
access : read-write


CH1_CTR

Direct access to the PWM counter
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH1_CTR CH1_CTR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CH1_CTR

CH1_CTR :
bits : 0 - 15 (16 bit)
access : read-write


CH1_CC

Counter compare values
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH1_CC CH1_CC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 A B

A :
bits : 0 - 15 (16 bit)
access : read-write

B :
bits : 16 - 31 (16 bit)
access : read-write


CH1_TOP

Counter wrap value
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH1_TOP CH1_TOP read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CH1_TOP

CH1_TOP :
bits : 0 - 15 (16 bit)
access : read-write


CH2_CSR

Control and status register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH2_CSR CH2_CSR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EN PH_CORRECT A_INV B_INV DIVMODE PH_RET PH_ADV

EN : Enable the PWM channel.
bits : 0 - 0 (1 bit)
access : read-write

PH_CORRECT : 1: Enable phase-correct modulation. 0: Trailing-edge
bits : 1 - 1 (1 bit)
access : read-write

A_INV : Invert output A
bits : 2 - 2 (1 bit)
access : read-write

B_INV : Invert output B
bits : 3 - 3 (1 bit)
access : read-write

DIVMODE :
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : div

Free-running counting at rate dictated by fractional divider

1 : level

Fractional divider operation is gated by the PWM B pin.

2 : rise

Counter advances with each rising edge of the PWM B pin.

3 : fall

Counter advances with each falling edge of the PWM B pin.

End of enumeration elements list.

PH_RET : Retard the phase of the counter by 1 count, while it is running. Self-clearing. Write a 1, and poll until low. Counter must be running.
bits : 6 - 6 (1 bit)
access : write-only

PH_ADV : Advance the phase of the counter by 1 count, while it is running. Self-clearing. Write a 1, and poll until low. Counter must be running at less than full speed (div_int + div_frac / 16 > 1)
bits : 7 - 7 (1 bit)
access : write-only


CH2_DIV

INT and FRAC form a fixed-point fractional number. Counting rate is system clock frequency divided by this number. Fractional division uses simple 1st-order sigma-delta.
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH2_DIV CH2_DIV read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FRAC INT

FRAC :
bits : 0 - 3 (4 bit)
access : read-write

INT :
bits : 4 - 11 (8 bit)
access : read-write


CH2_CTR

Direct access to the PWM counter
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH2_CTR CH2_CTR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CH2_CTR

CH2_CTR :
bits : 0 - 15 (16 bit)
access : read-write


CH2_CC

Counter compare values
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH2_CC CH2_CC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 A B

A :
bits : 0 - 15 (16 bit)
access : read-write

B :
bits : 16 - 31 (16 bit)
access : read-write


CH2_TOP

Counter wrap value
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH2_TOP CH2_TOP read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CH2_TOP

CH2_TOP :
bits : 0 - 15 (16 bit)
access : read-write


CH3_CSR

Control and status register
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH3_CSR CH3_CSR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EN PH_CORRECT A_INV B_INV DIVMODE PH_RET PH_ADV

EN : Enable the PWM channel.
bits : 0 - 0 (1 bit)
access : read-write

PH_CORRECT : 1: Enable phase-correct modulation. 0: Trailing-edge
bits : 1 - 1 (1 bit)
access : read-write

A_INV : Invert output A
bits : 2 - 2 (1 bit)
access : read-write

B_INV : Invert output B
bits : 3 - 3 (1 bit)
access : read-write

DIVMODE :
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : div

Free-running counting at rate dictated by fractional divider

1 : level

Fractional divider operation is gated by the PWM B pin.

2 : rise

Counter advances with each rising edge of the PWM B pin.

3 : fall

Counter advances with each falling edge of the PWM B pin.

End of enumeration elements list.

PH_RET : Retard the phase of the counter by 1 count, while it is running. Self-clearing. Write a 1, and poll until low. Counter must be running.
bits : 6 - 6 (1 bit)
access : write-only

PH_ADV : Advance the phase of the counter by 1 count, while it is running. Self-clearing. Write a 1, and poll until low. Counter must be running at less than full speed (div_int + div_frac / 16 > 1)
bits : 7 - 7 (1 bit)
access : write-only


CH0_DIV

INT and FRAC form a fixed-point fractional number. Counting rate is system clock frequency divided by this number. Fractional division uses simple 1st-order sigma-delta.
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH0_DIV CH0_DIV read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FRAC INT

FRAC :
bits : 0 - 3 (4 bit)
access : read-write

INT :
bits : 4 - 11 (8 bit)
access : read-write


CH3_DIV

INT and FRAC form a fixed-point fractional number. Counting rate is system clock frequency divided by this number. Fractional division uses simple 1st-order sigma-delta.
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH3_DIV CH3_DIV read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FRAC INT

FRAC :
bits : 0 - 3 (4 bit)
access : read-write

INT :
bits : 4 - 11 (8 bit)
access : read-write


CH3_CTR

Direct access to the PWM counter
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH3_CTR CH3_CTR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CH3_CTR

CH3_CTR :
bits : 0 - 15 (16 bit)
access : read-write


CH3_CC

Counter compare values
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH3_CC CH3_CC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 A B

A :
bits : 0 - 15 (16 bit)
access : read-write

B :
bits : 16 - 31 (16 bit)
access : read-write


CH3_TOP

Counter wrap value
address_offset : 0x4C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH3_TOP CH3_TOP read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CH3_TOP

CH3_TOP :
bits : 0 - 15 (16 bit)
access : read-write


CH4_CSR

Control and status register
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH4_CSR CH4_CSR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EN PH_CORRECT A_INV B_INV DIVMODE PH_RET PH_ADV

EN : Enable the PWM channel.
bits : 0 - 0 (1 bit)
access : read-write

PH_CORRECT : 1: Enable phase-correct modulation. 0: Trailing-edge
bits : 1 - 1 (1 bit)
access : read-write

A_INV : Invert output A
bits : 2 - 2 (1 bit)
access : read-write

B_INV : Invert output B
bits : 3 - 3 (1 bit)
access : read-write

DIVMODE :
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : div

Free-running counting at rate dictated by fractional divider

1 : level

Fractional divider operation is gated by the PWM B pin.

2 : rise

Counter advances with each rising edge of the PWM B pin.

3 : fall

Counter advances with each falling edge of the PWM B pin.

End of enumeration elements list.

PH_RET : Retard the phase of the counter by 1 count, while it is running. Self-clearing. Write a 1, and poll until low. Counter must be running.
bits : 6 - 6 (1 bit)
access : write-only

PH_ADV : Advance the phase of the counter by 1 count, while it is running. Self-clearing. Write a 1, and poll until low. Counter must be running at less than full speed (div_int + div_frac / 16 > 1)
bits : 7 - 7 (1 bit)
access : write-only


CH4_DIV

INT and FRAC form a fixed-point fractional number. Counting rate is system clock frequency divided by this number. Fractional division uses simple 1st-order sigma-delta.
address_offset : 0x54 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH4_DIV CH4_DIV read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FRAC INT

FRAC :
bits : 0 - 3 (4 bit)
access : read-write

INT :
bits : 4 - 11 (8 bit)
access : read-write


CH4_CTR

Direct access to the PWM counter
address_offset : 0x58 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH4_CTR CH4_CTR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CH4_CTR

CH4_CTR :
bits : 0 - 15 (16 bit)
access : read-write


CH4_CC

Counter compare values
address_offset : 0x5C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH4_CC CH4_CC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 A B

A :
bits : 0 - 15 (16 bit)
access : read-write

B :
bits : 16 - 31 (16 bit)
access : read-write


CH4_TOP

Counter wrap value
address_offset : 0x60 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH4_TOP CH4_TOP read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CH4_TOP

CH4_TOP :
bits : 0 - 15 (16 bit)
access : read-write


CH5_CSR

Control and status register
address_offset : 0x64 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH5_CSR CH5_CSR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EN PH_CORRECT A_INV B_INV DIVMODE PH_RET PH_ADV

EN : Enable the PWM channel.
bits : 0 - 0 (1 bit)
access : read-write

PH_CORRECT : 1: Enable phase-correct modulation. 0: Trailing-edge
bits : 1 - 1 (1 bit)
access : read-write

A_INV : Invert output A
bits : 2 - 2 (1 bit)
access : read-write

B_INV : Invert output B
bits : 3 - 3 (1 bit)
access : read-write

DIVMODE :
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : div

Free-running counting at rate dictated by fractional divider

1 : level

Fractional divider operation is gated by the PWM B pin.

2 : rise

Counter advances with each rising edge of the PWM B pin.

3 : fall

Counter advances with each falling edge of the PWM B pin.

End of enumeration elements list.

PH_RET : Retard the phase of the counter by 1 count, while it is running. Self-clearing. Write a 1, and poll until low. Counter must be running.
bits : 6 - 6 (1 bit)
access : write-only

PH_ADV : Advance the phase of the counter by 1 count, while it is running. Self-clearing. Write a 1, and poll until low. Counter must be running at less than full speed (div_int + div_frac / 16 > 1)
bits : 7 - 7 (1 bit)
access : write-only


CH5_DIV

INT and FRAC form a fixed-point fractional number. Counting rate is system clock frequency divided by this number. Fractional division uses simple 1st-order sigma-delta.
address_offset : 0x68 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH5_DIV CH5_DIV read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FRAC INT

FRAC :
bits : 0 - 3 (4 bit)
access : read-write

INT :
bits : 4 - 11 (8 bit)
access : read-write


CH5_CTR

Direct access to the PWM counter
address_offset : 0x6C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH5_CTR CH5_CTR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CH5_CTR

CH5_CTR :
bits : 0 - 15 (16 bit)
access : read-write


CH5_CC

Counter compare values
address_offset : 0x70 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH5_CC CH5_CC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 A B

A :
bits : 0 - 15 (16 bit)
access : read-write

B :
bits : 16 - 31 (16 bit)
access : read-write


CH5_TOP

Counter wrap value
address_offset : 0x74 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH5_TOP CH5_TOP read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CH5_TOP

CH5_TOP :
bits : 0 - 15 (16 bit)
access : read-write


CH6_CSR

Control and status register
address_offset : 0x78 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH6_CSR CH6_CSR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EN PH_CORRECT A_INV B_INV DIVMODE PH_RET PH_ADV

EN : Enable the PWM channel.
bits : 0 - 0 (1 bit)
access : read-write

PH_CORRECT : 1: Enable phase-correct modulation. 0: Trailing-edge
bits : 1 - 1 (1 bit)
access : read-write

A_INV : Invert output A
bits : 2 - 2 (1 bit)
access : read-write

B_INV : Invert output B
bits : 3 - 3 (1 bit)
access : read-write

DIVMODE :
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : div

Free-running counting at rate dictated by fractional divider

1 : level

Fractional divider operation is gated by the PWM B pin.

2 : rise

Counter advances with each rising edge of the PWM B pin.

3 : fall

Counter advances with each falling edge of the PWM B pin.

End of enumeration elements list.

PH_RET : Retard the phase of the counter by 1 count, while it is running. Self-clearing. Write a 1, and poll until low. Counter must be running.
bits : 6 - 6 (1 bit)
access : write-only

PH_ADV : Advance the phase of the counter by 1 count, while it is running. Self-clearing. Write a 1, and poll until low. Counter must be running at less than full speed (div_int + div_frac / 16 > 1)
bits : 7 - 7 (1 bit)
access : write-only


CH6_DIV

INT and FRAC form a fixed-point fractional number. Counting rate is system clock frequency divided by this number. Fractional division uses simple 1st-order sigma-delta.
address_offset : 0x7C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH6_DIV CH6_DIV read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FRAC INT

FRAC :
bits : 0 - 3 (4 bit)
access : read-write

INT :
bits : 4 - 11 (8 bit)
access : read-write


CH0_CTR

Direct access to the PWM counter
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH0_CTR CH0_CTR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CH0_CTR

CH0_CTR :
bits : 0 - 15 (16 bit)
access : read-write


CH6_CTR

Direct access to the PWM counter
address_offset : 0x80 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH6_CTR CH6_CTR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CH6_CTR

CH6_CTR :
bits : 0 - 15 (16 bit)
access : read-write


CH6_CC

Counter compare values
address_offset : 0x84 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH6_CC CH6_CC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 A B

A :
bits : 0 - 15 (16 bit)
access : read-write

B :
bits : 16 - 31 (16 bit)
access : read-write


CH6_TOP

Counter wrap value
address_offset : 0x88 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH6_TOP CH6_TOP read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CH6_TOP

CH6_TOP :
bits : 0 - 15 (16 bit)
access : read-write


CH7_CSR

Control and status register
address_offset : 0x8C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH7_CSR CH7_CSR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EN PH_CORRECT A_INV B_INV DIVMODE PH_RET PH_ADV

EN : Enable the PWM channel.
bits : 0 - 0 (1 bit)
access : read-write

PH_CORRECT : 1: Enable phase-correct modulation. 0: Trailing-edge
bits : 1 - 1 (1 bit)
access : read-write

A_INV : Invert output A
bits : 2 - 2 (1 bit)
access : read-write

B_INV : Invert output B
bits : 3 - 3 (1 bit)
access : read-write

DIVMODE :
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : div

Free-running counting at rate dictated by fractional divider

1 : level

Fractional divider operation is gated by the PWM B pin.

2 : rise

Counter advances with each rising edge of the PWM B pin.

3 : fall

Counter advances with each falling edge of the PWM B pin.

End of enumeration elements list.

PH_RET : Retard the phase of the counter by 1 count, while it is running. Self-clearing. Write a 1, and poll until low. Counter must be running.
bits : 6 - 6 (1 bit)
access : write-only

PH_ADV : Advance the phase of the counter by 1 count, while it is running. Self-clearing. Write a 1, and poll until low. Counter must be running at less than full speed (div_int + div_frac / 16 > 1)
bits : 7 - 7 (1 bit)
access : write-only


CH7_DIV

INT and FRAC form a fixed-point fractional number. Counting rate is system clock frequency divided by this number. Fractional division uses simple 1st-order sigma-delta.
address_offset : 0x90 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH7_DIV CH7_DIV read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FRAC INT

FRAC :
bits : 0 - 3 (4 bit)
access : read-write

INT :
bits : 4 - 11 (8 bit)
access : read-write


CH7_CTR

Direct access to the PWM counter
address_offset : 0x94 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH7_CTR CH7_CTR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CH7_CTR

CH7_CTR :
bits : 0 - 15 (16 bit)
access : read-write


CH7_CC

Counter compare values
address_offset : 0x98 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH7_CC CH7_CC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 A B

A :
bits : 0 - 15 (16 bit)
access : read-write

B :
bits : 16 - 31 (16 bit)
access : read-write


CH7_TOP

Counter wrap value
address_offset : 0x9C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH7_TOP CH7_TOP read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CH7_TOP

CH7_TOP :
bits : 0 - 15 (16 bit)
access : read-write


CH8_CSR

Control and status register
address_offset : 0xA0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH8_CSR CH8_CSR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EN PH_CORRECT A_INV B_INV DIVMODE PH_RET PH_ADV

EN : Enable the PWM channel.
bits : 0 - 0 (1 bit)
access : read-write

PH_CORRECT : 1: Enable phase-correct modulation. 0: Trailing-edge
bits : 1 - 1 (1 bit)
access : read-write

A_INV : Invert output A
bits : 2 - 2 (1 bit)
access : read-write

B_INV : Invert output B
bits : 3 - 3 (1 bit)
access : read-write

DIVMODE :
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : div

Free-running counting at rate dictated by fractional divider

1 : level

Fractional divider operation is gated by the PWM B pin.

2 : rise

Counter advances with each rising edge of the PWM B pin.

3 : fall

Counter advances with each falling edge of the PWM B pin.

End of enumeration elements list.

PH_RET : Retard the phase of the counter by 1 count, while it is running. Self-clearing. Write a 1, and poll until low. Counter must be running.
bits : 6 - 6 (1 bit)
access : write-only

PH_ADV : Advance the phase of the counter by 1 count, while it is running. Self-clearing. Write a 1, and poll until low. Counter must be running at less than full speed (div_int + div_frac / 16 > 1)
bits : 7 - 7 (1 bit)
access : write-only


CH8_DIV

INT and FRAC form a fixed-point fractional number. Counting rate is system clock frequency divided by this number. Fractional division uses simple 1st-order sigma-delta.
address_offset : 0xA4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH8_DIV CH8_DIV read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FRAC INT

FRAC :
bits : 0 - 3 (4 bit)
access : read-write

INT :
bits : 4 - 11 (8 bit)
access : read-write


CH8_CTR

Direct access to the PWM counter
address_offset : 0xA8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH8_CTR CH8_CTR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CH8_CTR

CH8_CTR :
bits : 0 - 15 (16 bit)
access : read-write


CH8_CC

Counter compare values
address_offset : 0xAC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH8_CC CH8_CC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 A B

A :
bits : 0 - 15 (16 bit)
access : read-write

B :
bits : 16 - 31 (16 bit)
access : read-write


CH8_TOP

Counter wrap value
address_offset : 0xB0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH8_TOP CH8_TOP read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CH8_TOP

CH8_TOP :
bits : 0 - 15 (16 bit)
access : read-write


CH9_CSR

Control and status register
address_offset : 0xB4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH9_CSR CH9_CSR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EN PH_CORRECT A_INV B_INV DIVMODE PH_RET PH_ADV

EN : Enable the PWM channel.
bits : 0 - 0 (1 bit)
access : read-write

PH_CORRECT : 1: Enable phase-correct modulation. 0: Trailing-edge
bits : 1 - 1 (1 bit)
access : read-write

A_INV : Invert output A
bits : 2 - 2 (1 bit)
access : read-write

B_INV : Invert output B
bits : 3 - 3 (1 bit)
access : read-write

DIVMODE :
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : div

Free-running counting at rate dictated by fractional divider

1 : level

Fractional divider operation is gated by the PWM B pin.

2 : rise

Counter advances with each rising edge of the PWM B pin.

3 : fall

Counter advances with each falling edge of the PWM B pin.

End of enumeration elements list.

PH_RET : Retard the phase of the counter by 1 count, while it is running. Self-clearing. Write a 1, and poll until low. Counter must be running.
bits : 6 - 6 (1 bit)
access : write-only

PH_ADV : Advance the phase of the counter by 1 count, while it is running. Self-clearing. Write a 1, and poll until low. Counter must be running at less than full speed (div_int + div_frac / 16 > 1)
bits : 7 - 7 (1 bit)
access : write-only


CH9_DIV

INT and FRAC form a fixed-point fractional number. Counting rate is system clock frequency divided by this number. Fractional division uses simple 1st-order sigma-delta.
address_offset : 0xB8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH9_DIV CH9_DIV read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FRAC INT

FRAC :
bits : 0 - 3 (4 bit)
access : read-write

INT :
bits : 4 - 11 (8 bit)
access : read-write


CH9_CTR

Direct access to the PWM counter
address_offset : 0xBC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH9_CTR CH9_CTR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CH9_CTR

CH9_CTR :
bits : 0 - 15 (16 bit)
access : read-write


CH0_CC

Counter compare values
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH0_CC CH0_CC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 A B

A :
bits : 0 - 15 (16 bit)
access : read-write

B :
bits : 16 - 31 (16 bit)
access : read-write


CH9_CC

Counter compare values
address_offset : 0xC0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH9_CC CH9_CC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 A B

A :
bits : 0 - 15 (16 bit)
access : read-write

B :
bits : 16 - 31 (16 bit)
access : read-write


CH9_TOP

Counter wrap value
address_offset : 0xC4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH9_TOP CH9_TOP read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CH9_TOP

CH9_TOP :
bits : 0 - 15 (16 bit)
access : read-write


CH10_CSR

Control and status register
address_offset : 0xC8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH10_CSR CH10_CSR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EN PH_CORRECT A_INV B_INV DIVMODE PH_RET PH_ADV

EN : Enable the PWM channel.
bits : 0 - 0 (1 bit)
access : read-write

PH_CORRECT : 1: Enable phase-correct modulation. 0: Trailing-edge
bits : 1 - 1 (1 bit)
access : read-write

A_INV : Invert output A
bits : 2 - 2 (1 bit)
access : read-write

B_INV : Invert output B
bits : 3 - 3 (1 bit)
access : read-write

DIVMODE :
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : div

Free-running counting at rate dictated by fractional divider

1 : level

Fractional divider operation is gated by the PWM B pin.

2 : rise

Counter advances with each rising edge of the PWM B pin.

3 : fall

Counter advances with each falling edge of the PWM B pin.

End of enumeration elements list.

PH_RET : Retard the phase of the counter by 1 count, while it is running. Self-clearing. Write a 1, and poll until low. Counter must be running.
bits : 6 - 6 (1 bit)
access : write-only

PH_ADV : Advance the phase of the counter by 1 count, while it is running. Self-clearing. Write a 1, and poll until low. Counter must be running at less than full speed (div_int + div_frac / 16 > 1)
bits : 7 - 7 (1 bit)
access : write-only


CH10_DIV

INT and FRAC form a fixed-point fractional number. Counting rate is system clock frequency divided by this number. Fractional division uses simple 1st-order sigma-delta.
address_offset : 0xCC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH10_DIV CH10_DIV read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FRAC INT

FRAC :
bits : 0 - 3 (4 bit)
access : read-write

INT :
bits : 4 - 11 (8 bit)
access : read-write


CH10_CTR

Direct access to the PWM counter
address_offset : 0xD0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH10_CTR CH10_CTR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CH10_CTR

CH10_CTR :
bits : 0 - 15 (16 bit)
access : read-write


CH10_CC

Counter compare values
address_offset : 0xD4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH10_CC CH10_CC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 A B

A :
bits : 0 - 15 (16 bit)
access : read-write

B :
bits : 16 - 31 (16 bit)
access : read-write


CH10_TOP

Counter wrap value
address_offset : 0xD8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH10_TOP CH10_TOP read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CH10_TOP

CH10_TOP :
bits : 0 - 15 (16 bit)
access : read-write


CH11_CSR

Control and status register
address_offset : 0xDC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH11_CSR CH11_CSR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EN PH_CORRECT A_INV B_INV DIVMODE PH_RET PH_ADV

EN : Enable the PWM channel.
bits : 0 - 0 (1 bit)
access : read-write

PH_CORRECT : 1: Enable phase-correct modulation. 0: Trailing-edge
bits : 1 - 1 (1 bit)
access : read-write

A_INV : Invert output A
bits : 2 - 2 (1 bit)
access : read-write

B_INV : Invert output B
bits : 3 - 3 (1 bit)
access : read-write

DIVMODE :
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0 : div

Free-running counting at rate dictated by fractional divider

1 : level

Fractional divider operation is gated by the PWM B pin.

2 : rise

Counter advances with each rising edge of the PWM B pin.

3 : fall

Counter advances with each falling edge of the PWM B pin.

End of enumeration elements list.

PH_RET : Retard the phase of the counter by 1 count, while it is running. Self-clearing. Write a 1, and poll until low. Counter must be running.
bits : 6 - 6 (1 bit)
access : write-only

PH_ADV : Advance the phase of the counter by 1 count, while it is running. Self-clearing. Write a 1, and poll until low. Counter must be running at less than full speed (div_int + div_frac / 16 > 1)
bits : 7 - 7 (1 bit)
access : write-only


CH11_DIV

INT and FRAC form a fixed-point fractional number. Counting rate is system clock frequency divided by this number. Fractional division uses simple 1st-order sigma-delta.
address_offset : 0xE0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH11_DIV CH11_DIV read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FRAC INT

FRAC :
bits : 0 - 3 (4 bit)
access : read-write

INT :
bits : 4 - 11 (8 bit)
access : read-write


CH11_CTR

Direct access to the PWM counter
address_offset : 0xE4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH11_CTR CH11_CTR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CH11_CTR

CH11_CTR :
bits : 0 - 15 (16 bit)
access : read-write


CH11_CC

Counter compare values
address_offset : 0xE8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH11_CC CH11_CC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 A B

A :
bits : 0 - 15 (16 bit)
access : read-write

B :
bits : 16 - 31 (16 bit)
access : read-write


CH11_TOP

Counter wrap value
address_offset : 0xEC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CH11_TOP CH11_TOP read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CH11_TOP

CH11_TOP :
bits : 0 - 15 (16 bit)
access : read-write


EN

This register aliases the CSR_EN bits for all channels. Writing to this register allows multiple channels to be enabled or disabled simultaneously, so they can run in perfect sync. For each channel, there is only one physical EN register bit, which can be accessed through here or CHx_CSR.
address_offset : 0xF0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EN EN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CH0 CH1 CH2 CH3 CH4 CH5 CH6 CH7 CH8 CH9 CH10 CH11

CH0 :
bits : 0 - 0 (1 bit)
access : read-write

CH1 :
bits : 1 - 1 (1 bit)
access : read-write

CH2 :
bits : 2 - 2 (1 bit)
access : read-write

CH3 :
bits : 3 - 3 (1 bit)
access : read-write

CH4 :
bits : 4 - 4 (1 bit)
access : read-write

CH5 :
bits : 5 - 5 (1 bit)
access : read-write

CH6 :
bits : 6 - 6 (1 bit)
access : read-write

CH7 :
bits : 7 - 7 (1 bit)
access : read-write

CH8 :
bits : 8 - 8 (1 bit)
access : read-write

CH9 :
bits : 9 - 9 (1 bit)
access : read-write

CH10 :
bits : 10 - 10 (1 bit)
access : read-write

CH11 :
bits : 11 - 11 (1 bit)
access : read-write


INTR

Raw Interrupts
address_offset : 0xF4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

INTR INTR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CH0 CH1 CH2 CH3 CH4 CH5 CH6 CH7 CH8 CH9 CH10 CH11

CH0 :
bits : 0 - 0 (1 bit)
access : read-write

CH1 :
bits : 1 - 1 (1 bit)
access : read-write

CH2 :
bits : 2 - 2 (1 bit)
access : read-write

CH3 :
bits : 3 - 3 (1 bit)
access : read-write

CH4 :
bits : 4 - 4 (1 bit)
access : read-write

CH5 :
bits : 5 - 5 (1 bit)
access : read-write

CH6 :
bits : 6 - 6 (1 bit)
access : read-write

CH7 :
bits : 7 - 7 (1 bit)
access : read-write

CH8 :
bits : 8 - 8 (1 bit)
access : read-write

CH9 :
bits : 9 - 9 (1 bit)
access : read-write

CH10 :
bits : 10 - 10 (1 bit)
access : read-write

CH11 :
bits : 11 - 11 (1 bit)
access : read-write


IRQ0_INTE

Interrupt Enable for irq0
address_offset : 0xF8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IRQ0_INTE IRQ0_INTE read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CH0 CH1 CH2 CH3 CH4 CH5 CH6 CH7 CH8 CH9 CH10 CH11

CH0 :
bits : 0 - 0 (1 bit)
access : read-write

CH1 :
bits : 1 - 1 (1 bit)
access : read-write

CH2 :
bits : 2 - 2 (1 bit)
access : read-write

CH3 :
bits : 3 - 3 (1 bit)
access : read-write

CH4 :
bits : 4 - 4 (1 bit)
access : read-write

CH5 :
bits : 5 - 5 (1 bit)
access : read-write

CH6 :
bits : 6 - 6 (1 bit)
access : read-write

CH7 :
bits : 7 - 7 (1 bit)
access : read-write

CH8 :
bits : 8 - 8 (1 bit)
access : read-write

CH9 :
bits : 9 - 9 (1 bit)
access : read-write

CH10 :
bits : 10 - 10 (1 bit)
access : read-write

CH11 :
bits : 11 - 11 (1 bit)
access : read-write


IRQ0_INTF

Interrupt Force for irq0
address_offset : 0xFC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IRQ0_INTF IRQ0_INTF read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CH0 CH1 CH2 CH3 CH4 CH5 CH6 CH7 CH8 CH9 CH10 CH11

CH0 :
bits : 0 - 0 (1 bit)
access : read-write

CH1 :
bits : 1 - 1 (1 bit)
access : read-write

CH2 :
bits : 2 - 2 (1 bit)
access : read-write

CH3 :
bits : 3 - 3 (1 bit)
access : read-write

CH4 :
bits : 4 - 4 (1 bit)
access : read-write

CH5 :
bits : 5 - 5 (1 bit)
access : read-write

CH6 :
bits : 6 - 6 (1 bit)
access : read-write

CH7 :
bits : 7 - 7 (1 bit)
access : read-write

CH8 :
bits : 8 - 8 (1 bit)
access : read-write

CH9 :
bits : 9 - 9 (1 bit)
access : read-write

CH10 :
bits : 10 - 10 (1 bit)
access : read-write

CH11 :
bits : 11 - 11 (1 bit)
access : read-write



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