Embeetle, an IDE designed from scratch for embedded software developers.address_offset : 0x0 Bytes (0x0)
size : 0x2C byte (0x0)
mem_usage : registers
protection :
Set the priority of each master for bus arbitration.
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PROC0 : 0 - low priority, 1 - high priority
bits : 0 - 0 (1 bit)
access : read-write
PROC1 : 0 - low priority, 1 - high priority
bits : 4 - 4 (1 bit)
access : read-write
DMA_R : 0 - low priority, 1 - high priority
bits : 8 - 8 (1 bit)
access : read-write
DMA_W : 0 - low priority, 1 - high priority
bits : 12 - 12 (1 bit)
access : read-write
Bus fabric performance event select for PERFCTR0
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PERFSEL0 : Select an event for PERFCTR0. For each downstream port of the main crossbar, four events are available: ACCESS, an access took place ACCESS_CONTESTED, an access took place that previously stalled due to contention from other masters STALL_DOWNSTREAM, count cycles where any master stalled due to a stall on the downstream bus STALL_UPSTREAM, count cycles where any master stalled for any reason, including contention from other masters.
bits : 0 - 6 (7 bit)
access : read-write
Enumeration:
0 : siob_proc1_stall_upstream
1 : siob_proc1_stall_downstream
2 : siob_proc1_access_contested
3 : siob_proc1_access
4 : siob_proc0_stall_upstream
5 : siob_proc0_stall_downstream
6 : siob_proc0_access_contested
7 : siob_proc0_access
8 : apb_stall_upstream
9 : apb_stall_downstream
10 : apb_access_contested
11 : apb_access
12 : fastperi_stall_upstream
13 : fastperi_stall_downstream
14 : fastperi_access_contested
15 : fastperi_access
16 : sram9_stall_upstream
17 : sram9_stall_downstream
18 : sram9_access_contested
19 : sram9_access
20 : sram8_stall_upstream
21 : sram8_stall_downstream
22 : sram8_access_contested
23 : sram8_access
24 : sram7_stall_upstream
25 : sram7_stall_downstream
26 : sram7_access_contested
27 : sram7_access
28 : sram6_stall_upstream
29 : sram6_stall_downstream
30 : sram6_access_contested
31 : sram6_access
32 : sram5_stall_upstream
33 : sram5_stall_downstream
34 : sram5_access_contested
35 : sram5_access
36 : sram4_stall_upstream
37 : sram4_stall_downstream
38 : sram4_access_contested
39 : sram4_access
40 : sram3_stall_upstream
41 : sram3_stall_downstream
42 : sram3_access_contested
43 : sram3_access
44 : sram2_stall_upstream
45 : sram2_stall_downstream
46 : sram2_access_contested
47 : sram2_access
48 : sram1_stall_upstream
49 : sram1_stall_downstream
50 : sram1_access_contested
51 : sram1_access
52 : sram0_stall_upstream
53 : sram0_stall_downstream
54 : sram0_access_contested
55 : sram0_access
56 : xip_main1_stall_upstream
57 : xip_main1_stall_downstream
58 : xip_main1_access_contested
59 : xip_main1_access
60 : xip_main0_stall_upstream
61 : xip_main0_stall_downstream
62 : xip_main0_access_contested
63 : xip_main0_access
64 : rom_stall_upstream
65 : rom_stall_downstream
66 : rom_access_contested
67 : rom_access
End of enumeration elements list.
Bus fabric performance counter 1
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PERFCTR1 : Busfabric saturating performance counter 1
Count some event signal from the busfabric arbiters, if PERFCTR_EN is set.
Write any value to clear. Select an event to count using PERFSEL1
bits : 0 - 23 (24 bit)
access : read-write
Bus fabric performance event select for PERFCTR1
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PERFSEL1 : Select an event for PERFCTR1. For each downstream port of the main crossbar, four events are available: ACCESS, an access took place ACCESS_CONTESTED, an access took place that previously stalled due to contention from other masters STALL_DOWNSTREAM, count cycles where any master stalled due to a stall on the downstream bus STALL_UPSTREAM, count cycles where any master stalled for any reason, including contention from other masters.
bits : 0 - 6 (7 bit)
access : read-write
Enumeration:
0 : siob_proc1_stall_upstream
1 : siob_proc1_stall_downstream
2 : siob_proc1_access_contested
3 : siob_proc1_access
4 : siob_proc0_stall_upstream
5 : siob_proc0_stall_downstream
6 : siob_proc0_access_contested
7 : siob_proc0_access
8 : apb_stall_upstream
9 : apb_stall_downstream
10 : apb_access_contested
11 : apb_access
12 : fastperi_stall_upstream
13 : fastperi_stall_downstream
14 : fastperi_access_contested
15 : fastperi_access
16 : sram9_stall_upstream
17 : sram9_stall_downstream
18 : sram9_access_contested
19 : sram9_access
20 : sram8_stall_upstream
21 : sram8_stall_downstream
22 : sram8_access_contested
23 : sram8_access
24 : sram7_stall_upstream
25 : sram7_stall_downstream
26 : sram7_access_contested
27 : sram7_access
28 : sram6_stall_upstream
29 : sram6_stall_downstream
30 : sram6_access_contested
31 : sram6_access
32 : sram5_stall_upstream
33 : sram5_stall_downstream
34 : sram5_access_contested
35 : sram5_access
36 : sram4_stall_upstream
37 : sram4_stall_downstream
38 : sram4_access_contested
39 : sram4_access
40 : sram3_stall_upstream
41 : sram3_stall_downstream
42 : sram3_access_contested
43 : sram3_access
44 : sram2_stall_upstream
45 : sram2_stall_downstream
46 : sram2_access_contested
47 : sram2_access
48 : sram1_stall_upstream
49 : sram1_stall_downstream
50 : sram1_access_contested
51 : sram1_access
52 : sram0_stall_upstream
53 : sram0_stall_downstream
54 : sram0_access_contested
55 : sram0_access
56 : xip_main1_stall_upstream
57 : xip_main1_stall_downstream
58 : xip_main1_access_contested
59 : xip_main1_access
60 : xip_main0_stall_upstream
61 : xip_main0_stall_downstream
62 : xip_main0_access_contested
63 : xip_main0_access
64 : rom_stall_upstream
65 : rom_stall_downstream
66 : rom_access_contested
67 : rom_access
End of enumeration elements list.
Bus fabric performance counter 2
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PERFCTR2 : Busfabric saturating performance counter 2
Count some event signal from the busfabric arbiters, if PERFCTR_EN is set.
Write any value to clear. Select an event to count using PERFSEL2
bits : 0 - 23 (24 bit)
access : read-write
Bus fabric performance event select for PERFCTR2
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PERFSEL2 : Select an event for PERFCTR2. For each downstream port of the main crossbar, four events are available: ACCESS, an access took place ACCESS_CONTESTED, an access took place that previously stalled due to contention from other masters STALL_DOWNSTREAM, count cycles where any master stalled due to a stall on the downstream bus STALL_UPSTREAM, count cycles where any master stalled for any reason, including contention from other masters.
bits : 0 - 6 (7 bit)
access : read-write
Enumeration:
0 : siob_proc1_stall_upstream
1 : siob_proc1_stall_downstream
2 : siob_proc1_access_contested
3 : siob_proc1_access
4 : siob_proc0_stall_upstream
5 : siob_proc0_stall_downstream
6 : siob_proc0_access_contested
7 : siob_proc0_access
8 : apb_stall_upstream
9 : apb_stall_downstream
10 : apb_access_contested
11 : apb_access
12 : fastperi_stall_upstream
13 : fastperi_stall_downstream
14 : fastperi_access_contested
15 : fastperi_access
16 : sram9_stall_upstream
17 : sram9_stall_downstream
18 : sram9_access_contested
19 : sram9_access
20 : sram8_stall_upstream
21 : sram8_stall_downstream
22 : sram8_access_contested
23 : sram8_access
24 : sram7_stall_upstream
25 : sram7_stall_downstream
26 : sram7_access_contested
27 : sram7_access
28 : sram6_stall_upstream
29 : sram6_stall_downstream
30 : sram6_access_contested
31 : sram6_access
32 : sram5_stall_upstream
33 : sram5_stall_downstream
34 : sram5_access_contested
35 : sram5_access
36 : sram4_stall_upstream
37 : sram4_stall_downstream
38 : sram4_access_contested
39 : sram4_access
40 : sram3_stall_upstream
41 : sram3_stall_downstream
42 : sram3_access_contested
43 : sram3_access
44 : sram2_stall_upstream
45 : sram2_stall_downstream
46 : sram2_access_contested
47 : sram2_access
48 : sram1_stall_upstream
49 : sram1_stall_downstream
50 : sram1_access_contested
51 : sram1_access
52 : sram0_stall_upstream
53 : sram0_stall_downstream
54 : sram0_access_contested
55 : sram0_access
56 : xip_main1_stall_upstream
57 : xip_main1_stall_downstream
58 : xip_main1_access_contested
59 : xip_main1_access
60 : xip_main0_stall_upstream
61 : xip_main0_stall_downstream
62 : xip_main0_access_contested
63 : xip_main0_access
64 : rom_stall_upstream
65 : rom_stall_downstream
66 : rom_access_contested
67 : rom_access
End of enumeration elements list.
Bus fabric performance counter 3
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PERFCTR3 : Busfabric saturating performance counter 3
Count some event signal from the busfabric arbiters, if PERFCTR_EN is set.
Write any value to clear. Select an event to count using PERFSEL3
bits : 0 - 23 (24 bit)
access : read-write
Bus fabric performance event select for PERFCTR3
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PERFSEL3 : Select an event for PERFCTR3. For each downstream port of the main crossbar, four events are available: ACCESS, an access took place ACCESS_CONTESTED, an access took place that previously stalled due to contention from other masters STALL_DOWNSTREAM, count cycles where any master stalled due to a stall on the downstream bus STALL_UPSTREAM, count cycles where any master stalled for any reason, including contention from other masters.
bits : 0 - 6 (7 bit)
access : read-write
Enumeration:
0 : siob_proc1_stall_upstream
1 : siob_proc1_stall_downstream
2 : siob_proc1_access_contested
3 : siob_proc1_access
4 : siob_proc0_stall_upstream
5 : siob_proc0_stall_downstream
6 : siob_proc0_access_contested
7 : siob_proc0_access
8 : apb_stall_upstream
9 : apb_stall_downstream
10 : apb_access_contested
11 : apb_access
12 : fastperi_stall_upstream
13 : fastperi_stall_downstream
14 : fastperi_access_contested
15 : fastperi_access
16 : sram9_stall_upstream
17 : sram9_stall_downstream
18 : sram9_access_contested
19 : sram9_access
20 : sram8_stall_upstream
21 : sram8_stall_downstream
22 : sram8_access_contested
23 : sram8_access
24 : sram7_stall_upstream
25 : sram7_stall_downstream
26 : sram7_access_contested
27 : sram7_access
28 : sram6_stall_upstream
29 : sram6_stall_downstream
30 : sram6_access_contested
31 : sram6_access
32 : sram5_stall_upstream
33 : sram5_stall_downstream
34 : sram5_access_contested
35 : sram5_access
36 : sram4_stall_upstream
37 : sram4_stall_downstream
38 : sram4_access_contested
39 : sram4_access
40 : sram3_stall_upstream
41 : sram3_stall_downstream
42 : sram3_access_contested
43 : sram3_access
44 : sram2_stall_upstream
45 : sram2_stall_downstream
46 : sram2_access_contested
47 : sram2_access
48 : sram1_stall_upstream
49 : sram1_stall_downstream
50 : sram1_access_contested
51 : sram1_access
52 : sram0_stall_upstream
53 : sram0_stall_downstream
54 : sram0_access_contested
55 : sram0_access
56 : xip_main1_stall_upstream
57 : xip_main1_stall_downstream
58 : xip_main1_access_contested
59 : xip_main1_access
60 : xip_main0_stall_upstream
61 : xip_main0_stall_downstream
62 : xip_main0_access_contested
63 : xip_main0_access
64 : rom_stall_upstream
65 : rom_stall_downstream
66 : rom_access_contested
67 : rom_access
End of enumeration elements list.
Bus priority acknowledge
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BUS_PRIORITY_ACK : Goes to 1 once all arbiters have registered the new global priority levels.
Arbiters update their local priority when servicing a new nonsequential access.
In normal circumstances this will happen almost immediately.
bits : 0 - 0 (1 bit)
access : read-only
Enable the performance counters. If 0, the performance counters do not increment. This can be used to precisely start/stop event sampling around the profiled section of code.
The performance counters are initially disabled, to save energy.
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PERFCTR_EN :
bits : 0 - 0 (1 bit)
access : read-write
Bus fabric performance counter 0
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PERFCTR0 : Busfabric saturating performance counter 0
Count some event signal from the busfabric arbiters, if PERFCTR_EN is set.
Write any value to clear. Select an event to count using PERFSEL0
bits : 0 - 23 (24 bit)
access : read-write
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