SIO

GPIO_OUT : Set output level (1/0 -> high/low) for GPIO0...31. Reading back gives the last value written, NOT the input value from the pins. If core 0 and core 1 both write to GPIO_OUT simultaneously (or to a SET/CLR/XOR alias), the result is as though the write from core 0 took place first, and the write from core 1 was then applied to that intermediate result. In the Non-secure SIO, Secure-only GPIOs (as per ACCESSCTRL) ignore writes, and their output status reads back as zero. This is also true for SET/CLR/XOR aliases of this register.
bits : 0 - 31 (32 bit)
access : read-write

SPINLOCK0

Reading from a spinlock address will: - Return 0 if lock is already locked - Otherwise return nonzero, and simultaneously claim the lock Writing (any value) releases the lock. If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins. The value returned on success is 0x1 << lock number.
address_offset : 0x100 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SPINLOCK0 :
bits : 0 - 31 (32 bit)
access : read-write

SPINLOCK1

Reading from a spinlock address will: - Return 0 if lock is already locked - Otherwise return nonzero, and simultaneously claim the lock Writing (any value) releases the lock. If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins. The value returned on success is 0x1 << lock number.
address_offset : 0x104 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SPINLOCK1 :
bits : 0 - 31 (32 bit)
access : read-write

SPINLOCK2

Reading from a spinlock address will: - Return 0 if lock is already locked - Otherwise return nonzero, and simultaneously claim the lock Writing (any value) releases the lock. If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins. The value returned on success is 0x1 << lock number.
address_offset : 0x108 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SPINLOCK2 :
bits : 0 - 31 (32 bit)
access : read-write

SPINLOCK3

Reading from a spinlock address will: - Return 0 if lock is already locked - Otherwise return nonzero, and simultaneously claim the lock Writing (any value) releases the lock. If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins. The value returned on success is 0x1 << lock number.
address_offset : 0x10C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SPINLOCK3 :
bits : 0 - 31 (32 bit)
access : read-write

SPINLOCK4

Reading from a spinlock address will: - Return 0 if lock is already locked - Otherwise return nonzero, and simultaneously claim the lock Writing (any value) releases the lock. If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins. The value returned on success is 0x1 << lock number.
address_offset : 0x110 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SPINLOCK4 :
bits : 0 - 31 (32 bit)
access : read-write

SPINLOCK5

Reading from a spinlock address will: - Return 0 if lock is already locked - Otherwise return nonzero, and simultaneously claim the lock Writing (any value) releases the lock. If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins. The value returned on success is 0x1 << lock number.
address_offset : 0x114 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SPINLOCK5 :
bits : 0 - 31 (32 bit)
access : read-write

SPINLOCK6

Reading from a spinlock address will: - Return 0 if lock is already locked - Otherwise return nonzero, and simultaneously claim the lock Writing (any value) releases the lock. If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins. The value returned on success is 0x1 << lock number.
address_offset : 0x118 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SPINLOCK6 :
bits : 0 - 31 (32 bit)
access : read-write

SPINLOCK7

Reading from a spinlock address will: - Return 0 if lock is already locked - Otherwise return nonzero, and simultaneously claim the lock Writing (any value) releases the lock. If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins. The value returned on success is 0x1 << lock number.
address_offset : 0x11C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SPINLOCK7 :
bits : 0 - 31 (32 bit)
access : read-write

SPINLOCK8

Reading from a spinlock address will: - Return 0 if lock is already locked - Otherwise return nonzero, and simultaneously claim the lock Writing (any value) releases the lock. If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins. The value returned on success is 0x1 << lock number.
address_offset : 0x120 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SPINLOCK8 :
bits : 0 - 31 (32 bit)
access : read-write

SPINLOCK9

Reading from a spinlock address will: - Return 0 if lock is already locked - Otherwise return nonzero, and simultaneously claim the lock Writing (any value) releases the lock. If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins. The value returned on success is 0x1 << lock number.
address_offset : 0x124 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SPINLOCK9 :
bits : 0 - 31 (32 bit)
access : read-write

SPINLOCK10

Reading from a spinlock address will: - Return 0 if lock is already locked - Otherwise return nonzero, and simultaneously claim the lock Writing (any value) releases the lock. If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins. The value returned on success is 0x1 << lock number.
address_offset : 0x128 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SPINLOCK10 :
bits : 0 - 31 (32 bit)
access : read-write

SPINLOCK11

Reading from a spinlock address will: - Return 0 if lock is already locked - Otherwise return nonzero, and simultaneously claim the lock Writing (any value) releases the lock. If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins. The value returned on success is 0x1 << lock number.
address_offset : 0x12C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SPINLOCK11 :
bits : 0 - 31 (32 bit)
access : read-write

SPINLOCK12

Reading from a spinlock address will: - Return 0 if lock is already locked - Otherwise return nonzero, and simultaneously claim the lock Writing (any value) releases the lock. If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins. The value returned on success is 0x1 << lock number.
address_offset : 0x130 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SPINLOCK12 :
bits : 0 - 31 (32 bit)
access : read-write

SPINLOCK13

Reading from a spinlock address will: - Return 0 if lock is already locked - Otherwise return nonzero, and simultaneously claim the lock Writing (any value) releases the lock. If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins. The value returned on success is 0x1 << lock number.
address_offset : 0x134 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SPINLOCK13 :
bits : 0 - 31 (32 bit)
access : read-write

SPINLOCK14

Reading from a spinlock address will: - Return 0 if lock is already locked - Otherwise return nonzero, and simultaneously claim the lock Writing (any value) releases the lock. If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins. The value returned on success is 0x1 << lock number.
address_offset : 0x138 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SPINLOCK14 :
bits : 0 - 31 (32 bit)
access : read-write

SPINLOCK15

Reading from a spinlock address will: - Return 0 if lock is already locked - Otherwise return nonzero, and simultaneously claim the lock Writing (any value) releases the lock. If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins. The value returned on success is 0x1 << lock number.
address_offset : 0x13C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SPINLOCK15 :
bits : 0 - 31 (32 bit)
access : read-write

GPIO_HI_OUT

Output value for GPIO32...47, QSPI IOs and USB pins. Write to set output level (1/0 -> high/low). Reading back gives the last value written, NOT the input value from the pins. If core 0 and core 1 both write to GPIO_HI_OUT simultaneously (or to a SET/CLR/XOR alias), the result is as though the write from core 0 took place first, and the write from core 1 was then applied to that intermediate result. In the Non-secure SIO, Secure-only GPIOs (as per ACCESSCTRL) ignore writes, and their output status reads back as zero. This is also true for SET/CLR/XOR aliases of this register.
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GPIO : Output value for GPIO32...47
bits : 0 - 15 (16 bit)
access : read-write

USB_DP : Output value for USB D+ pin
bits : 24 - 24 (1 bit)
access : read-write

USB_DM : Output value for USB D- pin
bits : 25 - 25 (1 bit)
access : read-write

QSPI_SCK : Output value for QSPI SCK pin
bits : 26 - 26 (1 bit)
access : read-write

QSPI_CSN : Output value for QSPI CSn pin
bits : 27 - 27 (1 bit)
access : read-write

QSPI_SD : Output value for QSPI SD0 (MOSI), SD1 (MISO), SD2 and SD3 pins
bits : 28 - 31 (4 bit)
access : read-write

SPINLOCK16

Reading from a spinlock address will: - Return 0 if lock is already locked - Otherwise return nonzero, and simultaneously claim the lock Writing (any value) releases the lock. If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins. The value returned on success is 0x1 << lock number.
address_offset : 0x140 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SPINLOCK16 :
bits : 0 - 31 (32 bit)
access : read-write

SPINLOCK17

Reading from a spinlock address will: - Return 0 if lock is already locked - Otherwise return nonzero, and simultaneously claim the lock Writing (any value) releases the lock. If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins. The value returned on success is 0x1 << lock number.
address_offset : 0x144 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SPINLOCK17 :
bits : 0 - 31 (32 bit)
access : read-write

SPINLOCK18

Reading from a spinlock address will: - Return 0 if lock is already locked - Otherwise return nonzero, and simultaneously claim the lock Writing (any value) releases the lock. If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins. The value returned on success is 0x1 << lock number.
address_offset : 0x148 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SPINLOCK18 :
bits : 0 - 31 (32 bit)
access : read-write

SPINLOCK19

Reading from a spinlock address will: - Return 0 if lock is already locked - Otherwise return nonzero, and simultaneously claim the lock Writing (any value) releases the lock. If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins. The value returned on success is 0x1 << lock number.
address_offset : 0x14C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SPINLOCK19 :
bits : 0 - 31 (32 bit)
access : read-write

SPINLOCK20

Reading from a spinlock address will: - Return 0 if lock is already locked - Otherwise return nonzero, and simultaneously claim the lock Writing (any value) releases the lock. If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins. The value returned on success is 0x1 << lock number.
address_offset : 0x150 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SPINLOCK20 :
bits : 0 - 31 (32 bit)
access : read-write

SPINLOCK21

Reading from a spinlock address will: - Return 0 if lock is already locked - Otherwise return nonzero, and simultaneously claim the lock Writing (any value) releases the lock. If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins. The value returned on success is 0x1 << lock number.
address_offset : 0x154 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SPINLOCK21 :
bits : 0 - 31 (32 bit)
access : read-write

SPINLOCK22

Reading from a spinlock address will: - Return 0 if lock is already locked - Otherwise return nonzero, and simultaneously claim the lock Writing (any value) releases the lock. If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins. The value returned on success is 0x1 << lock number.
address_offset : 0x158 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SPINLOCK22 :
bits : 0 - 31 (32 bit)
access : read-write

SPINLOCK23

Reading from a spinlock address will: - Return 0 if lock is already locked - Otherwise return nonzero, and simultaneously claim the lock Writing (any value) releases the lock. If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins. The value returned on success is 0x1 << lock number.
address_offset : 0x15C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SPINLOCK23 :
bits : 0 - 31 (32 bit)
access : read-write

SPINLOCK24

Reading from a spinlock address will: - Return 0 if lock is already locked - Otherwise return nonzero, and simultaneously claim the lock Writing (any value) releases the lock. If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins. The value returned on success is 0x1 << lock number.
address_offset : 0x160 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SPINLOCK24 :
bits : 0 - 31 (32 bit)
access : read-write

SPINLOCK25

Reading from a spinlock address will: - Return 0 if lock is already locked - Otherwise return nonzero, and simultaneously claim the lock Writing (any value) releases the lock. If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins. The value returned on success is 0x1 << lock number.
address_offset : 0x164 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SPINLOCK25 :
bits : 0 - 31 (32 bit)
access : read-write

SPINLOCK26

Reading from a spinlock address will: - Return 0 if lock is already locked - Otherwise return nonzero, and simultaneously claim the lock Writing (any value) releases the lock. If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins. The value returned on success is 0x1 << lock number.
address_offset : 0x168 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SPINLOCK26 :
bits : 0 - 31 (32 bit)
access : read-write

SPINLOCK27

Reading from a spinlock address will: - Return 0 if lock is already locked - Otherwise return nonzero, and simultaneously claim the lock Writing (any value) releases the lock. If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins. The value returned on success is 0x1 << lock number.
address_offset : 0x16C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SPINLOCK27 :
bits : 0 - 31 (32 bit)
access : read-write

SPINLOCK28

Reading from a spinlock address will: - Return 0 if lock is already locked - Otherwise return nonzero, and simultaneously claim the lock Writing (any value) releases the lock. If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins. The value returned on success is 0x1 << lock number.
address_offset : 0x170 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SPINLOCK28 :
bits : 0 - 31 (32 bit)
access : read-write

SPINLOCK29

Reading from a spinlock address will: - Return 0 if lock is already locked - Otherwise return nonzero, and simultaneously claim the lock Writing (any value) releases the lock. If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins. The value returned on success is 0x1 << lock number.
address_offset : 0x174 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SPINLOCK29 :
bits : 0 - 31 (32 bit)
access : read-write

SPINLOCK30

Reading from a spinlock address will: - Return 0 if lock is already locked - Otherwise return nonzero, and simultaneously claim the lock Writing (any value) releases the lock. If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins. The value returned on success is 0x1 << lock number.
address_offset : 0x178 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SPINLOCK30 :
bits : 0 - 31 (32 bit)
access : read-write

SPINLOCK31

Reading from a spinlock address will: - Return 0 if lock is already locked - Otherwise return nonzero, and simultaneously claim the lock Writing (any value) releases the lock. If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins. The value returned on success is 0x1 << lock number.
address_offset : 0x17C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SPINLOCK31 :
bits : 0 - 31 (32 bit)
access : read-write

GPIO_OUT_SET

GPIO0...31 output value set
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GPIO_OUT_SET : Perform an atomic bit-set on GPIO_OUT, i.e. `GPIO_OUT |= wdata`
bits : 0 - 31 (32 bit)
access : write-only

DOORBELL_OUT_SET

Trigger a doorbell interrupt on the opposite core. Write 1 to a bit to set the corresponding bit in DOORBELL_IN on the opposite core. This raises the opposite core's doorbell interrupt. Read to get the status of the doorbells currently asserted on the opposite core. This is equivalent to that core reading its own DOORBELL_IN status.
address_offset : 0x180 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOORBELL_OUT_SET :
bits : 0 - 7 (8 bit)
access : read-write

DOORBELL_OUT_CLR

Clear doorbells which have been posted to the opposite core. This register is intended for debugging and initialisation purposes. Writing 1 to a bit in DOORBELL_OUT_CLR clears the corresponding bit in DOORBELL_IN on the opposite core. Clearing all bits will cause that core's doorbell interrupt to deassert. Since the usual order of events is for software to send events using DOORBELL_OUT_SET, and acknowledge incoming events by writing to DOORBELL_IN_CLR, this register should be used with caution to avoid race conditions. Reading returns the status of the doorbells currently asserted on the other core, i.e. is equivalent to that core reading its own DOORBELL_IN status.
address_offset : 0x184 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOORBELL_OUT_CLR :
bits : 0 - 7 (8 bit)
access : read-write

DOORBELL_IN_SET

Write 1s to trigger doorbell interrupts on this core. Read to get status of doorbells currently asserted on this core.
address_offset : 0x188 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOORBELL_IN_SET :
bits : 0 - 7 (8 bit)
access : read-write

DOORBELL_IN_CLR

Check and acknowledge doorbells posted to this core. This core's doorbell interrupt is asserted when any bit in this register is 1. Write 1 to each bit to clear that bit. The doorbell interrupt deasserts once all bits are cleared. Read to get status of doorbells currently asserted on this core.
address_offset : 0x18C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOORBELL_IN_CLR :
bits : 0 - 7 (8 bit)
access : read-write

PERI_NONSEC

Detach certain core-local peripherals from Secure SIO, and attach them to Non-secure SIO, so that Non-secure software can use them. Attempting to access one of these peripherals from the Secure SIO when it is attached to the Non-secure SIO, or vice versa, will generate a bus error. This register is per-core, and is only present on the Secure SIO. Most SIO hardware is duplicated across the Secure and Non-secure SIO, so is not listed in this register.
address_offset : 0x190 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

INTERP0 : If 1, detach interpolator 0 (of this core) from the Secure SIO, and attach to the Non-secure SIO.
bits : 0 - 0 (1 bit)
access : read-write

INTERP1 : If 1, detach interpolator 1 (of this core) from the Secure SIO, and attach to the Non-secure SIO.
bits : 1 - 1 (1 bit)
access : read-write

TMDS : IF 1, detach TMDS encoder (of this core) from the Secure SIO, and attach to the Non-secure SIO.
bits : 5 - 5 (1 bit)
access : read-write

RISCV_SOFTIRQ

Control the assertion of the standard software interrupt (MIP.MSIP) on the RISC-V cores. Unlike the RISC-V timer, this interrupt is not routed to a normal system-level interrupt line, so can not be used by the Arm cores. It is safe for both cores to write to this register on the same cycle. The set/clear effect is accumulated across both cores, and then applied. If a flag is both set and cleared on the same cycle, only the set takes effect.
address_offset : 0x1A0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CORE0_SET : Write 1 to atomically set the core 0 software interrupt flag. Read to get the status of this flag.
bits : 0 - 0 (1 bit)
access : read-write

CORE1_SET : Write 1 to atomically set the core 1 software interrupt flag. Read to get the status of this flag.
bits : 1 - 1 (1 bit)
access : read-write

CORE0_CLR : Write 1 to atomically clear the core 0 software interrupt flag. Read to get the status of this flag.
bits : 8 - 8 (1 bit)
access : read-write

CORE1_CLR : Write 1 to atomically clear the core 1 software interrupt flag. Read to get the status of this flag.
bits : 9 - 9 (1 bit)
access : read-write

MTIME_CTRL

Control register for the RISC-V 64-bit Machine-mode timer. This timer is only present in the Secure SIO, so is only accessible to an Arm core in Secure mode or a RISC-V core in Machine mode. Note whilst this timer follows the RISC-V privileged specification, it is equally usable by the Arm cores. The interrupts are routed to normal system-level interrupt lines as well as to the MIP.MTIP inputs on the RISC-V cores.
address_offset : 0x1A4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EN : Timer enable bit. When 0, the timer will not increment automatically.
bits : 0 - 0 (1 bit)
access : read-write

FULLSPEED : If 1, increment the timer every cycle (i.e. run directly from the system clock), rather than incrementing on the system-level timer tick input.
bits : 1 - 1 (1 bit)
access : read-write

DBGPAUSE_CORE0 : If 1, the timer pauses when core 0 is in the debug halt state.
bits : 2 - 2 (1 bit)
access : read-write

DBGPAUSE_CORE1 : If 1, the timer pauses when core 1 is in the debug halt state.
bits : 3 - 3 (1 bit)
access : read-write

MTIME

Read/write access to the high half of RISC-V Machine-mode timer. This register is shared between both cores. If both cores write on the same cycle, core 1 takes precedence.
address_offset : 0x1B0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MTIME :
bits : 0 - 31 (32 bit)
access : read-write

MTIMEH

Read/write access to the high half of RISC-V Machine-mode timer. This register is shared between both cores. If both cores write on the same cycle, core 1 takes precedence.
address_offset : 0x1B4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MTIMEH :
bits : 0 - 31 (32 bit)
access : read-write

MTIMECMP

Low half of RISC-V Machine-mode timer comparator. This register is core-local, i.e., each core gets a copy of this register, with the comparison result routed to its own interrupt line. The timer interrupt is asserted whenever MTIME is greater than or equal to MTIMECMP. This comparison is unsigned, and performed on the full 64-bit values.
address_offset : 0x1B8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MTIMECMP :
bits : 0 - 31 (32 bit)
access : read-write

MTIMECMPH

High half of RISC-V Machine-mode timer comparator. This register is core-local. The timer interrupt is asserted whenever MTIME is greater than or equal to MTIMECMP. This comparison is unsigned, and performed on the full 64-bit values.
address_offset : 0x1BC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MTIMECMPH :
bits : 0 - 31 (32 bit)
access : read-write

GPIO_HI_OUT_SET

Output value set for GPIO32..47, QSPI IOs and USB pins. Perform an atomic bit-set on GPIO_HI_OUT, i.e. `GPIO_HI_OUT |= wdata`
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GPIO :
bits : 0 - 15 (16 bit)
access : write-only

USB_DP :
bits : 24 - 24 (1 bit)
access : write-only

USB_DM :
bits : 25 - 25 (1 bit)
access : write-only

QSPI_SCK :
bits : 26 - 26 (1 bit)
access : write-only

QSPI_CSN :
bits : 27 - 27 (1 bit)
access : write-only

QSPI_SD :
bits : 28 - 31 (4 bit)
access : write-only

TMDS_CTRL

Control register for TMDS encoder.
address_offset : 0x1C0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

L0_ROT : Right-rotate the 16 LSBs of the colour accumulator by 0-15 bits, in order to get the MSB of the lane 0 (blue) colour data aligned with the MSB of the 8-bit encoder input. For example, for RGB565 (red most significant), blue is bits 4:0, so should be right-rotated by 13 to align with bits 7:3 of the encoder input.
bits : 0 - 3 (4 bit)
access : read-write

L1_ROT : Right-rotate the 16 LSBs of the colour accumulator by 0-15 bits, in order to get the MSB of the lane 1 (green) colour data aligned with the MSB of the 8-bit encoder input. For example, for RGB565, green is bits 10:5, so should be right-rotated by 3 bits to align with bits 7:2 of the encoder input.
bits : 4 - 7 (4 bit)
access : read-write

L2_ROT : Right-rotate the 16 LSBs of the colour accumulator by 0-15 bits, in order to get the MSB of the lane 2 (red) colour data aligned with the MSB of the 8-bit encoder input. For example, for RGB565 (red most significant), red is bits 15:11, so should be right-rotated by 8 bits to align with bits 7:3 of the encoder input.
bits : 8 - 11 (4 bit)
access : read-write

L0_NBITS : Number of valid colour MSBs for lane 0 (1-8 bits, encoded as 0 through 7). Remaining LSBs are masked to 0 after the rotate.
bits : 12 - 14 (3 bit)
access : read-write

L1_NBITS : Number of valid colour MSBs for lane 1 (1-8 bits, encoded as 0 through 7). Remaining LSBs are masked to 0 after the rotate.
bits : 15 - 17 (3 bit)
access : read-write

L2_NBITS : Number of valid colour MSBs for lane 2 (1-8 bits, encoded as 0 through 7). Remaining LSBs are masked to 0 after the rotate.
bits : 18 - 20 (3 bit)
access : read-write

INTERLEAVE : Enable lane interleaving for reads of PEEK_SINGLE/POP_SINGLE. When interleaving is disabled, each of the 3 symbols appears as a contiguous 10-bit field, with lane 0 being the least-significant and starting at bit 0 of the register. When interleaving is enabled, the symbols are packed into 5 chunks of 3 lanes times 2 bits (30 bits total). Each chunk contains two bits of a TMDS symbol per lane, with lane 0 being the least significant.
bits : 23 - 23 (1 bit)
access : read-write

PIX_SHIFT : Shift applied to the colour data register with each read of a POP alias register. Reading from the POP_SINGLE register, or reading from the POP_DOUBLE register with PIX2_NOSHIFT set (for pixel doubling), shifts by the indicated amount. Reading from a POP_DOUBLE register when PIX2_NOSHIFT is clear will shift by double the indicated amount. (Shift by 32 means no shift.)
bits : 24 - 26 (3 bit)
access : read-write

Enumeration:

0 : 0

Do not shift the colour data register.

1 : 1

Shift the colour data register by 1 bit

2 : 2

Shift the colour data register by 2 bits

3 : 4

Shift the colour data register by 4 bits

4 : 8

Shift the colour data register by 8 bits

5 : 16

Shift the colour data register by 16 bits

End of enumeration elements list.

PIX2_NOSHIFT : When encoding two pixels's worth of symbols in one cycle (a read of a PEEK/POP_DOUBLE register), the second encoder sees a shifted version of the colour data register. This control disables that shift, so that both encoder layers see the same pixel data. This is used for pixel doubling.
bits : 27 - 27 (1 bit)
access : read-write

CLEAR_BALANCE : Clear the running DC balance state of the TMDS encoders. This bit should be written once at the beginning of each scanline.
bits : 28 - 28 (1 bit)
access : write-only

TMDS_WDATA

Write-only access to the TMDS colour data register.
address_offset : 0x1C4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TMDS_WDATA :
bits : 0 - 31 (32 bit)
access : write-only

TMDS_PEEK_SINGLE

Get the encoding of one pixel's worth of colour data, packed into a 32-bit value (3x10-bit symbols). The PEEK alias does not shift the colour register when read, but still advances the running DC balance state of each encoder. This is useful for pixel doubling.
address_offset : 0x1C8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TMDS_PEEK_SINGLE :
bits : 0 - 31 (32 bit)
access : read-only

TMDS_POP_SINGLE

Get the encoding of one pixel's worth of colour data, packed into a 32-bit value. The packing is 5 chunks of 3 lanes times 2 bits (30 bits total). Each chunk contains two bits of a TMDS symbol per lane. This format is intended for shifting out with the HSTX peripheral on RP2350. The POP alias shifts the colour register when read, as well as advancing the running DC balance state of each encoder.
address_offset : 0x1CC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TMDS_POP_SINGLE :
bits : 0 - 31 (32 bit)
access : read-only

TMDS_PEEK_DOUBLE_L0

Get lane 0 of the encoding of two pixels' worth of colour data. Two 10-bit TMDS symbols are packed at the bottom of a 32-bit word. The PEEK alias does not shift the colour register when read, but still advances the lane 0 DC balance state. This is useful if all 3 lanes' worth of encode are to be read at once, rather than processing the entire scanline for one lane before moving to the next lane.
address_offset : 0x1D0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TMDS_PEEK_DOUBLE_L0 :
bits : 0 - 31 (32 bit)
access : read-only

TMDS_POP_DOUBLE_L0

Get lane 0 of the encoding of two pixels' worth of colour data. Two 10-bit TMDS symbols are packed at the bottom of a 32-bit word. The POP alias shifts the colour register when read, according to the values of PIX_SHIFT and PIX2_NOSHIFT.
address_offset : 0x1D4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TMDS_POP_DOUBLE_L0 :
bits : 0 - 31 (32 bit)
access : read-only

TMDS_PEEK_DOUBLE_L1

Get lane 1 of the encoding of two pixels' worth of colour data. Two 10-bit TMDS symbols are packed at the bottom of a 32-bit word. The PEEK alias does not shift the colour register when read, but still advances the lane 1 DC balance state. This is useful if all 3 lanes' worth of encode are to be read at once, rather than processing the entire scanline for one lane before moving to the next lane.
address_offset : 0x1D8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TMDS_PEEK_DOUBLE_L1 :
bits : 0 - 31 (32 bit)
access : read-only

TMDS_POP_DOUBLE_L1

Get lane 1 of the encoding of two pixels' worth of colour data. Two 10-bit TMDS symbols are packed at the bottom of a 32-bit word. The POP alias shifts the colour register when read, according to the values of PIX_SHIFT and PIX2_NOSHIFT.
address_offset : 0x1DC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TMDS_POP_DOUBLE_L1 :
bits : 0 - 31 (32 bit)
access : read-only

TMDS_PEEK_DOUBLE_L2

Get lane 2 of the encoding of two pixels' worth of colour data. Two 10-bit TMDS symbols are packed at the bottom of a 32-bit word. The PEEK alias does not shift the colour register when read, but still advances the lane 2 DC balance state. This is useful if all 3 lanes' worth of encode are to be read at once, rather than processing the entire scanline for one lane before moving to the next lane.
address_offset : 0x1E0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TMDS_PEEK_DOUBLE_L2 :
bits : 0 - 31 (32 bit)
access : read-only

TMDS_POP_DOUBLE_L2

Get lane 2 of the encoding of two pixels' worth of colour data. Two 10-bit TMDS symbols are packed at the bottom of a 32-bit word. The POP alias shifts the colour register when read, according to the values of PIX_SHIFT and PIX2_NOSHIFT.
address_offset : 0x1E4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TMDS_POP_DOUBLE_L2 :
bits : 0 - 31 (32 bit)
access : read-only

GPIO_OUT_CLR

GPIO0...31 output value clear
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GPIO_OUT_CLR : Perform an atomic bit-clear on GPIO_OUT, i.e. `GPIO_OUT &= ~wdata`
bits : 0 - 31 (32 bit)
access : write-only

GPIO_HI_OUT_CLR

Output value clear for GPIO32..47, QSPI IOs and USB pins. Perform an atomic bit-clear on GPIO_HI_OUT, i.e. `GPIO_HI_OUT &= ~wdata`
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GPIO :
bits : 0 - 15 (16 bit)
access : write-only

USB_DP :
bits : 24 - 24 (1 bit)
access : write-only

USB_DM :
bits : 25 - 25 (1 bit)
access : write-only

QSPI_SCK :
bits : 26 - 26 (1 bit)
access : write-only

QSPI_CSN :
bits : 27 - 27 (1 bit)
access : write-only

QSPI_SD :
bits : 28 - 31 (4 bit)
access : write-only

GPIO_OUT_XOR

GPIO0...31 output value XOR
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GPIO_OUT_XOR : Perform an atomic bitwise XOR on GPIO_OUT, i.e. `GPIO_OUT ^= wdata`
bits : 0 - 31 (32 bit)
access : write-only

GPIO_HI_OUT_XOR

Output value XOR for GPIO32..47, QSPI IOs and USB pins. Perform an atomic bitwise XOR on GPIO_HI_OUT, i.e. `GPIO_HI_OUT ^= wdata`
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GPIO :
bits : 0 - 15 (16 bit)
access : write-only

USB_DP :
bits : 24 - 24 (1 bit)
access : write-only

USB_DM :
bits : 25 - 25 (1 bit)
access : write-only

QSPI_SCK :
bits : 26 - 26 (1 bit)
access : write-only

QSPI_CSN :
bits : 27 - 27 (1 bit)
access : write-only

QSPI_SD :
bits : 28 - 31 (4 bit)
access : write-only

GPIO_OE

GPIO0...31 output enable
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GPIO_OE : Set output enable (1/0 -> output/input) for GPIO0...31. Reading back gives the last value written. If core 0 and core 1 both write to GPIO_OE simultaneously (or to a SET/CLR/XOR alias), the result is as though the write from core 0 took place first, and the write from core 1 was then applied to that intermediate result. In the Non-secure SIO, Secure-only GPIOs (as per ACCESSCTRL) ignore writes, and their output status reads back as zero. This is also true for SET/CLR/XOR aliases of this register.
bits : 0 - 31 (32 bit)
access : read-write

GPIO_HI_OE

Output enable value for GPIO32...47, QSPI IOs and USB pins. Write output enable (1/0 -> output/input). Reading back gives the last value written. If core 0 and core 1 both write to GPIO_HI_OE simultaneously (or to a SET/CLR/XOR alias), the result is as though the write from core 0 took place first, and the write from core 1 was then applied to that intermediate result. In the Non-secure SIO, Secure-only GPIOs (as per ACCESSCTRL) ignore writes, and their output status reads back as zero. This is also true for SET/CLR/XOR aliases of this register.
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GPIO : Output enable value for GPIO32...47
bits : 0 - 15 (16 bit)
access : read-write

USB_DP : Output enable value for USB D+ pin
bits : 24 - 24 (1 bit)
access : read-write

USB_DM : Output enable value for USB D- pin
bits : 25 - 25 (1 bit)
access : read-write

QSPI_SCK : Output enable value for QSPI SCK pin
bits : 26 - 26 (1 bit)
access : read-write

QSPI_CSN : Output enable value for QSPI CSn pin
bits : 27 - 27 (1 bit)
access : read-write

QSPI_SD : Output enable value for QSPI SD0 (MOSI), SD1 (MISO), SD2 and SD3 pins
bits : 28 - 31 (4 bit)
access : read-write

GPIO_OE_SET

GPIO0...31 output enable set
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GPIO_OE_SET : Perform an atomic bit-set on GPIO_OE, i.e. `GPIO_OE |= wdata`
bits : 0 - 31 (32 bit)
access : write-only

GPIO_HI_OE_SET

Output enable set for GPIO32...47, QSPI IOs and USB pins. Perform an atomic bit-set on GPIO_HI_OE, i.e. `GPIO_HI_OE |= wdata`
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GPIO :
bits : 0 - 15 (16 bit)
access : write-only

USB_DP :
bits : 24 - 24 (1 bit)
access : write-only

USB_DM :
bits : 25 - 25 (1 bit)
access : write-only

QSPI_SCK :
bits : 26 - 26 (1 bit)
access : write-only

QSPI_CSN :
bits : 27 - 27 (1 bit)
access : write-only

QSPI_SD :
bits : 28 - 31 (4 bit)
access : write-only

GPIO_IN

Input value for GPIO0...31. In the Non-secure SIO, Secure-only GPIOs (as per ACCESSCTRL) appear as zero.
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GPIO_IN :
bits : 0 - 31 (32 bit)
access : read-only

GPIO_OE_CLR

GPIO0...31 output enable clear
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GPIO_OE_CLR : Perform an atomic bit-clear on GPIO_OE, i.e. `GPIO_OE &= ~wdata`
bits : 0 - 31 (32 bit)
access : write-only

GPIO_HI_OE_CLR

Output enable clear for GPIO32...47, QSPI IOs and USB pins. Perform an atomic bit-clear on GPIO_HI_OE, i.e. `GPIO_HI_OE &= ~wdata`
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GPIO :
bits : 0 - 15 (16 bit)
access : write-only

USB_DP :
bits : 24 - 24 (1 bit)
access : write-only

USB_DM :
bits : 25 - 25 (1 bit)
access : write-only

QSPI_SCK :
bits : 26 - 26 (1 bit)
access : write-only

QSPI_CSN :
bits : 27 - 27 (1 bit)
access : write-only

QSPI_SD :
bits : 28 - 31 (4 bit)
access : write-only

GPIO_OE_XOR

GPIO0...31 output enable XOR
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GPIO_OE_XOR : Perform an atomic bitwise XOR on GPIO_OE, i.e. `GPIO_OE ^= wdata`
bits : 0 - 31 (32 bit)
access : write-only

GPIO_HI_OE_XOR

Output enable XOR for GPIO32...47, QSPI IOs and USB pins. Perform an atomic bitwise XOR on GPIO_HI_OE, i.e. `GPIO_HI_OE ^= wdata`
address_offset : 0x4C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GPIO :
bits : 0 - 15 (16 bit)
access : write-only

USB_DP :
bits : 24 - 24 (1 bit)
access : write-only

USB_DM :
bits : 25 - 25 (1 bit)
access : write-only

QSPI_SCK :
bits : 26 - 26 (1 bit)
access : write-only

QSPI_CSN :
bits : 27 - 27 (1 bit)
access : write-only

QSPI_SD :
bits : 28 - 31 (4 bit)
access : write-only

FIFO_ST

Status register for inter-core FIFOs (mailboxes). There is one FIFO in the core 0 -> core 1 direction, and one core 1 -> core 0. Both are 32 bits wide and 8 words deep. Core 0 can see the read side of the 1->0 FIFO (RX), and the write side of 0->1 FIFO (TX). Core 1 can see the read side of the 0->1 FIFO (RX), and the write side of 1->0 FIFO (TX). The SIO IRQ for each core is the logical OR of the VLD, WOF and ROE fields of its FIFO_ST register.
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VLD : Value is 1 if this core's RX FIFO is not empty (i.e. if FIFO_RD is valid)
bits : 0 - 0 (1 bit)
access : read-only

RDY : Value is 1 if this core's TX FIFO is not full (i.e. if FIFO_WR is ready for more data)
bits : 1 - 1 (1 bit)
access : read-only

WOF : Sticky flag indicating the TX FIFO was written when full. This write was ignored by the FIFO.
bits : 2 - 2 (1 bit)
access : read-write

ROE : Sticky flag indicating the RX FIFO was read when empty. This read was ignored by the FIFO.
bits : 3 - 3 (1 bit)
access : read-write

FIFO_WR

Write access to this core's TX FIFO
address_offset : 0x54 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FIFO_WR :
bits : 0 - 31 (32 bit)
access : write-only

FIFO_RD

Read access to this core's RX FIFO
address_offset : 0x58 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FIFO_RD :
bits : 0 - 31 (32 bit)
access : read-only

SPINLOCK_ST

Spinlock state A bitmap containing the state of all 32 spinlocks (1=locked). Mainly intended for debugging.
address_offset : 0x5C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SPINLOCK_ST :
bits : 0 - 31 (32 bit)
access : read-only

GPIO_HI_IN

Input value on GPIO32...47, QSPI IOs and USB pins In the Non-secure SIO, Secure-only GPIOs (as per ACCESSCTRL) appear as zero.
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GPIO : Input value on GPIO32...47
bits : 0 - 15 (16 bit)
access : read-only

USB_DP : Input value on USB D+ pin
bits : 24 - 24 (1 bit)
access : read-only

USB_DM : Input value on USB D- pin
bits : 25 - 25 (1 bit)
access : read-only

QSPI_SCK : Input value on QSPI SCK pin
bits : 26 - 26 (1 bit)
access : read-only

QSPI_CSN : Input value on QSPI CSn pin
bits : 27 - 27 (1 bit)
access : read-only

QSPI_SD : Input value on QSPI SD0 (MOSI), SD1 (MISO), SD2 and SD3 pins
bits : 28 - 31 (4 bit)
access : read-only

INTERP0_ACCUM0

Read/write access to accumulator 0
address_offset : 0x80 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

INTERP0_ACCUM0 :
bits : 0 - 31 (32 bit)
access : read-write

INTERP0_ACCUM1

Read/write access to accumulator 1
address_offset : 0x84 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

INTERP0_ACCUM1 :
bits : 0 - 31 (32 bit)
access : read-write

INTERP0_BASE0

Read/write access to BASE0 register.
address_offset : 0x88 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

INTERP0_BASE0 :
bits : 0 - 31 (32 bit)
access : read-write

INTERP0_BASE1

Read/write access to BASE1 register.
address_offset : 0x8C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

INTERP0_BASE1 :
bits : 0 - 31 (32 bit)
access : read-write

INTERP0_BASE2

Read/write access to BASE2 register.
address_offset : 0x90 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

INTERP0_BASE2 :
bits : 0 - 31 (32 bit)
access : read-write

INTERP0_POP_LANE0

Read LANE0 result, and simultaneously write lane results to both accumulators (POP).
address_offset : 0x94 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

INTERP0_POP_LANE0 :
bits : 0 - 31 (32 bit)
access : read-only

INTERP0_POP_LANE1

Read LANE1 result, and simultaneously write lane results to both accumulators (POP).
address_offset : 0x98 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

INTERP0_POP_LANE1 :
bits : 0 - 31 (32 bit)
access : read-only

INTERP0_POP_FULL

Read FULL result, and simultaneously write lane results to both accumulators (POP).
address_offset : 0x9C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

INTERP0_POP_FULL :
bits : 0 - 31 (32 bit)
access : read-only

INTERP0_PEEK_LANE0

Read LANE0 result, without altering any internal state (PEEK).
address_offset : 0xA0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

INTERP0_PEEK_LANE0 :
bits : 0 - 31 (32 bit)
access : read-only

INTERP0_PEEK_LANE1

Read LANE1 result, without altering any internal state (PEEK).
address_offset : 0xA4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

INTERP0_PEEK_LANE1 :
bits : 0 - 31 (32 bit)
access : read-only

INTERP0_PEEK_FULL

Read FULL result, without altering any internal state (PEEK).
address_offset : 0xA8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

INTERP0_PEEK_FULL :
bits : 0 - 31 (32 bit)
access : read-only

INTERP0_CTRL_LANE0

Control register for lane 0
address_offset : 0xAC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SHIFT : Right-rotate applied to accumulator before masking. By appropriately configuring the masks, left and right shifts can be synthesised.
bits : 0 - 4 (5 bit)
access : read-write

MASK_LSB : The least-significant bit allowed to pass by the mask (inclusive)
bits : 5 - 9 (5 bit)
access : read-write

MASK_MSB : The most-significant bit allowed to pass by the mask (inclusive) Setting MSB < LSB may cause chip to turn inside-out
bits : 10 - 14 (5 bit)
access : read-write

SIGNED : If SIGNED is set, the shifted and masked accumulator value is sign-extended to 32 bits before adding to BASE0, and LANE0 PEEK/POP appear extended to 32 bits when read by processor.
bits : 15 - 15 (1 bit)
access : read-write

CROSS_INPUT : If 1, feed the opposite lane's accumulator into this lane's shift + mask hardware. Takes effect even if ADD_RAW is set (the CROSS_INPUT mux is before the shift+mask bypass)
bits : 16 - 16 (1 bit)
access : read-write

CROSS_RESULT : If 1, feed the opposite lane's result into this lane's accumulator on POP.
bits : 17 - 17 (1 bit)
access : read-write

ADD_RAW : If 1, mask + shift is bypassed for LANE0 result. This does not affect FULL result.
bits : 18 - 18 (1 bit)
access : read-write

FORCE_MSB : ORed into bits 29:28 of the lane result presented to the processor on the bus. No effect on the internal 32-bit datapath. Handy for using a lane to generate sequence of pointers into flash or SRAM.
bits : 19 - 20 (2 bit)
access : read-write

BLEND : Only present on INTERP0 on each core. If BLEND mode is enabled: - LANE1 result is a linear interpolation between BASE0 and BASE1, controlled by the 8 LSBs of lane 1 shift and mask value (a fractional number between 0 and 255/256ths) - LANE0 result does not have BASE0 added (yields only the 8 LSBs of lane 1 shift+mask value) - FULL result does not have lane 1 shift+mask value added (BASE2 + lane 0 shift+mask) LANE1 SIGNED flag controls whether the interpolation is signed or unsigned.
bits : 21 - 21 (1 bit)
access : read-write

OVERF0 : Indicates if any masked-off MSBs in ACCUM0 are set.
bits : 23 - 23 (1 bit)
access : read-only

OVERF1 : Indicates if any masked-off MSBs in ACCUM1 are set.
bits : 24 - 24 (1 bit)
access : read-only

OVERF : Set if either OVERF0 or OVERF1 is set.
bits : 25 - 25 (1 bit)
access : read-only

INTERP0_CTRL_LANE1

Control register for lane 1
address_offset : 0xB0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SHIFT : Right-rotate applied to accumulator before masking. By appropriately configuring the masks, left and right shifts can be synthesised.
bits : 0 - 4 (5 bit)
access : read-write

MASK_LSB : The least-significant bit allowed to pass by the mask (inclusive)
bits : 5 - 9 (5 bit)
access : read-write

MASK_MSB : The most-significant bit allowed to pass by the mask (inclusive) Setting MSB < LSB may cause chip to turn inside-out
bits : 10 - 14 (5 bit)
access : read-write

SIGNED : If SIGNED is set, the shifted and masked accumulator value is sign-extended to 32 bits before adding to BASE1, and LANE1 PEEK/POP appear extended to 32 bits when read by processor.
bits : 15 - 15 (1 bit)
access : read-write

CROSS_RESULT : If 1, feed the opposite lane's result into this lane's accumulator on POP.
bits : 17 - 17 (1 bit)
access : read-write

ADD_RAW : If 1, mask + shift is bypassed for LANE1 result. This does not affect FULL result.
bits : 18 - 18 (1 bit)
access : read-write

INTERP0_ACCUM0_ADD

Values written here are atomically added to ACCUM0 Reading yields lane 0's raw shift and mask value (BASE0 not added).
address_offset : 0xB4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

INTERP0_ACCUM0_ADD :
bits : 0 - 23 (24 bit)
access : read-write

INTERP0_ACCUM1_ADD

Values written here are atomically added to ACCUM1 Reading yields lane 1's raw shift and mask value (BASE1 not added).
address_offset : 0xB8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

INTERP0_ACCUM1_ADD :
bits : 0 - 23 (24 bit)
access : read-write

INTERP0_BASE_1AND0

On write, the lower 16 bits go to BASE0, upper bits to BASE1 simultaneously. Each half is sign-extended to 32 bits if that lane's SIGNED flag is set.
address_offset : 0xBC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

INTERP0_BASE_1AND0 :
bits : 0 - 31 (32 bit)
access : write-only

INTERP1_ACCUM0

Read/write access to accumulator 0
address_offset : 0xC0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

INTERP1_ACCUM0 :
bits : 0 - 31 (32 bit)
access : read-write

INTERP1_ACCUM1

Read/write access to accumulator 1
address_offset : 0xC4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

INTERP1_ACCUM1 :
bits : 0 - 31 (32 bit)
access : read-write

INTERP1_BASE0

Read/write access to BASE0 register.
address_offset : 0xC8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

INTERP1_BASE0 :
bits : 0 - 31 (32 bit)
access : read-write

INTERP1_BASE1

Read/write access to BASE1 register.
address_offset : 0xCC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

INTERP1_BASE1 :
bits : 0 - 31 (32 bit)
access : read-write

INTERP1_BASE2

Read/write access to BASE2 register.
address_offset : 0xD0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

INTERP1_BASE2 :
bits : 0 - 31 (32 bit)
access : read-write

INTERP1_POP_LANE0

Read LANE0 result, and simultaneously write lane results to both accumulators (POP).
address_offset : 0xD4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

INTERP1_POP_LANE0 :
bits : 0 - 31 (32 bit)
access : read-only

INTERP1_POP_LANE1

Read LANE1 result, and simultaneously write lane results to both accumulators (POP).
address_offset : 0xD8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

INTERP1_POP_LANE1 :
bits : 0 - 31 (32 bit)
access : read-only

INTERP1_POP_FULL

Read FULL result, and simultaneously write lane results to both accumulators (POP).
address_offset : 0xDC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

INTERP1_POP_FULL :
bits : 0 - 31 (32 bit)
access : read-only

INTERP1_PEEK_LANE0

Read LANE0 result, without altering any internal state (PEEK).
address_offset : 0xE0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

INTERP1_PEEK_LANE0 :
bits : 0 - 31 (32 bit)
access : read-only

INTERP1_PEEK_LANE1

Read LANE1 result, without altering any internal state (PEEK).
address_offset : 0xE4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

INTERP1_PEEK_LANE1 :
bits : 0 - 31 (32 bit)
access : read-only

INTERP1_PEEK_FULL

Read FULL result, without altering any internal state (PEEK).
address_offset : 0xE8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

INTERP1_PEEK_FULL :
bits : 0 - 31 (32 bit)
access : read-only

INTERP1_CTRL_LANE0

Control register for lane 0
address_offset : 0xEC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SHIFT : Right-rotate applied to accumulator before masking. By appropriately configuring the masks, left and right shifts can be synthesised.
bits : 0 - 4 (5 bit)
access : read-write

MASK_LSB : The least-significant bit allowed to pass by the mask (inclusive)
bits : 5 - 9 (5 bit)
access : read-write

MASK_MSB : The most-significant bit allowed to pass by the mask (inclusive) Setting MSB < LSB may cause chip to turn inside-out
bits : 10 - 14 (5 bit)
access : read-write

CROSS_RESULT : If 1, feed the opposite lane's result into this lane's accumulator on POP.
bits : 17 - 17 (1 bit)
access : read-write

ADD_RAW : If 1, mask + shift is bypassed for LANE0 result. This does not affect FULL result.
bits : 18 - 18 (1 bit)
access : read-write

CLAMP : Only present on INTERP1 on each core. If CLAMP mode is enabled: - LANE0 result is shifted and masked ACCUM0, clamped by a lower bound of BASE0 and an upper bound of BASE1. - Signedness of these comparisons is determined by LANE0_CTRL_SIGNED
bits : 22 - 22 (1 bit)
access : read-write

OVERF0 : Indicates if any masked-off MSBs in ACCUM0 are set.
bits : 23 - 23 (1 bit)
access : read-only

OVERF1 : Indicates if any masked-off MSBs in ACCUM1 are set.
bits : 24 - 24 (1 bit)
access : read-only

OVERF : Set if either OVERF0 or OVERF1 is set.
bits : 25 - 25 (1 bit)
access : read-only

INTERP1_CTRL_LANE1

Control register for lane 1
address_offset : 0xF0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SHIFT : Right-rotate applied to accumulator before masking. By appropriately configuring the masks, left and right shifts can be synthesised.
bits : 0 - 4 (5 bit)
access : read-write

MASK_LSB : The least-significant bit allowed to pass by the mask (inclusive)
bits : 5 - 9 (5 bit)
access : read-write

MASK_MSB : The most-significant bit allowed to pass by the mask (inclusive) Setting MSB < LSB may cause chip to turn inside-out
bits : 10 - 14 (5 bit)
access : read-write

CROSS_RESULT : If 1, feed the opposite lane's result into this lane's accumulator on POP.
bits : 17 - 17 (1 bit)
access : read-write

ADD_RAW : If 1, mask + shift is bypassed for LANE1 result. This does not affect FULL result.
bits : 18 - 18 (1 bit)
access : read-write

INTERP1_ACCUM0_ADD

Values written here are atomically added to ACCUM0 Reading yields lane 0's raw shift and mask value (BASE0 not added).
address_offset : 0xF4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

INTERP1_ACCUM0_ADD :
bits : 0 - 23 (24 bit)
access : read-write

INTERP1_ACCUM1_ADD

Values written here are atomically added to ACCUM1 Reading yields lane 1's raw shift and mask value (BASE1 not added).
address_offset : 0xF8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

INTERP1_ACCUM1_ADD :
bits : 0 - 23 (24 bit)
access : read-write

INTERP1_BASE_1AND0

On write, the lower 16 bits go to BASE0, upper bits to BASE1 simultaneously. Each half is sign-extended to 32 bits if that lane's SIGNED flag is set.
address_offset : 0xFC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

INTERP1_BASE_1AND0 :
bits : 0 - 31 (32 bit)
access : write-only

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