USB

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x118 byte (0x0)
mem_usage : registers
protection :

Registers

ADDR_ENDP

ADDR_ENDP4

SOF_TIMESTAMP_RAW

SOF_TIMESTAMP_LAST

SM_STATE

EP_TX_ERROR

EP_RX_ERROR

DEV_SM_WATCHDOG

ADDR_ENDP5

ADDR_ENDP6

ADDR_ENDP7

ADDR_ENDP8

ADDR_ENDP9

ADDR_ENDP10

ADDR_ENDP11

ADDR_ENDP12

ADDR_ENDP13

ADDR_ENDP14

ADDR_ENDP15

ADDR_ENDP1

MAIN_CTRL

SOF_WR

SOF_RD

SIE_CTRL

SIE_STATUS

INT_EP_CTRL

BUFF_STATUS

BUFF_CPU_SHOULD_HANDLE

EP_ABORT

EP_ABORT_DONE

EP_STALL_ARM

NAK_POLL

EP_STATUS_STALL_NAK

USB_MUXING

USB_PWR

USBPHY_DIRECT

ADDR_ENDP2

USBPHY_DIRECT_OVERRIDE

USBPHY_TRIM

LINESTATE_TUNING

INTR

INTE

INTF

INTS

ADDR_ENDP3


ADDR_ENDP

Device address and endpoint control
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADDR_ENDP ADDR_ENDP read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADDRESS ENDPOINT

ADDRESS : In device mode, the address that the device should respond to. Set in response to a SET_ADDR setup packet from the host. In host mode set to the address of the device to communicate with.
bits : 0 - 6 (7 bit)
access : read-write

ENDPOINT : Device endpoint to send data to. Only valid for HOST mode.
bits : 16 - 19 (4 bit)
access : read-write


ADDR_ENDP4

Interrupt endpoint 4. Only valid for HOST mode.
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADDR_ENDP4 ADDR_ENDP4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADDRESS ENDPOINT INTEP_DIR INTEP_PREAMBLE

ADDRESS : Device address
bits : 0 - 6 (7 bit)
access : read-write

ENDPOINT : Endpoint number of the interrupt endpoint
bits : 16 - 19 (4 bit)
access : read-write

INTEP_DIR : Direction of the interrupt endpoint. In=0, Out=1
bits : 25 - 25 (1 bit)
access : read-write

INTEP_PREAMBLE : Interrupt EP requires preamble (is a low speed device on a full speed hub)
bits : 26 - 26 (1 bit)
access : read-write


SOF_TIMESTAMP_RAW

Device only. Raw value of free-running PHY clock counter @48MHz. Used to calculate time between SOF events.
address_offset : 0x100 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SOF_TIMESTAMP_RAW SOF_TIMESTAMP_RAW read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SOF_TIMESTAMP_RAW

SOF_TIMESTAMP_RAW :
bits : 0 - 20 (21 bit)
access : read-only


SOF_TIMESTAMP_LAST

Device only. Value of free-running PHY clock counter @48MHz when last SOF event occurred.
address_offset : 0x104 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SOF_TIMESTAMP_LAST SOF_TIMESTAMP_LAST read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SOF_TIMESTAMP_LAST

SOF_TIMESTAMP_LAST :
bits : 0 - 20 (21 bit)
access : read-only


SM_STATE


address_offset : 0x108 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SM_STATE SM_STATE read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 STATE BC_STATE RX_DASM

STATE :
bits : 0 - 4 (5 bit)
access : read-only

BC_STATE :
bits : 5 - 7 (3 bit)
access : read-only

RX_DASM :
bits : 8 - 11 (4 bit)
access : read-only


EP_TX_ERROR

TX error count for each endpoint. Write to each field to reset the counter to 0.
address_offset : 0x10C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EP_TX_ERROR EP_TX_ERROR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EP0 EP1 EP2 EP3 EP4 EP5 EP6 EP7 EP8 EP9 EP10 EP11 EP12 EP13 EP14 EP15

EP0 :
bits : 0 - 1 (2 bit)
access : read-write

EP1 :
bits : 2 - 3 (2 bit)
access : read-write

EP2 :
bits : 4 - 5 (2 bit)
access : read-write

EP3 :
bits : 6 - 7 (2 bit)
access : read-write

EP4 :
bits : 8 - 9 (2 bit)
access : read-write

EP5 :
bits : 10 - 11 (2 bit)
access : read-write

EP6 :
bits : 12 - 13 (2 bit)
access : read-write

EP7 :
bits : 14 - 15 (2 bit)
access : read-write

EP8 :
bits : 16 - 17 (2 bit)
access : read-write

EP9 :
bits : 18 - 19 (2 bit)
access : read-write

EP10 :
bits : 20 - 21 (2 bit)
access : read-write

EP11 :
bits : 22 - 23 (2 bit)
access : read-write

EP12 :
bits : 24 - 25 (2 bit)
access : read-write

EP13 :
bits : 26 - 27 (2 bit)
access : read-write

EP14 :
bits : 28 - 29 (2 bit)
access : read-write

EP15 :
bits : 30 - 31 (2 bit)
access : read-write


EP_RX_ERROR

RX error count for each endpoint. Write to each field to reset the counter to 0.
address_offset : 0x110 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EP_RX_ERROR EP_RX_ERROR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EP0_TRANSACTION EP0_SEQ EP1_TRANSACTION EP1_SEQ EP2_TRANSACTION EP2_SEQ EP3_TRANSACTION EP3_SEQ EP4_TRANSACTION EP4_SEQ EP5_TRANSACTION EP5_SEQ EP6_TRANSACTION EP6_SEQ EP7_TRANSACTION EP7_SEQ EP8_TRANSACTION EP8_SEQ EP9_TRANSACTION EP9_SEQ EP10_TRANSACTION EP10_SEQ EP11_TRANSACTION EP11_SEQ EP12_TRANSACTION EP12_SEQ EP13_TRANSACTION EP13_SEQ EP14_TRANSACTION EP14_SEQ EP15_TRANSACTION EP15_SEQ

EP0_TRANSACTION :
bits : 0 - 0 (1 bit)
access : read-write

EP0_SEQ :
bits : 1 - 1 (1 bit)
access : read-write

EP1_TRANSACTION :
bits : 2 - 2 (1 bit)
access : read-write

EP1_SEQ :
bits : 3 - 3 (1 bit)
access : read-write

EP2_TRANSACTION :
bits : 4 - 4 (1 bit)
access : read-write

EP2_SEQ :
bits : 5 - 5 (1 bit)
access : read-write

EP3_TRANSACTION :
bits : 6 - 6 (1 bit)
access : read-write

EP3_SEQ :
bits : 7 - 7 (1 bit)
access : read-write

EP4_TRANSACTION :
bits : 8 - 8 (1 bit)
access : read-write

EP4_SEQ :
bits : 9 - 9 (1 bit)
access : read-write

EP5_TRANSACTION :
bits : 10 - 10 (1 bit)
access : read-write

EP5_SEQ :
bits : 11 - 11 (1 bit)
access : read-write

EP6_TRANSACTION :
bits : 12 - 12 (1 bit)
access : read-write

EP6_SEQ :
bits : 13 - 13 (1 bit)
access : read-write

EP7_TRANSACTION :
bits : 14 - 14 (1 bit)
access : read-write

EP7_SEQ :
bits : 15 - 15 (1 bit)
access : read-write

EP8_TRANSACTION :
bits : 16 - 16 (1 bit)
access : read-write

EP8_SEQ :
bits : 17 - 17 (1 bit)
access : read-write

EP9_TRANSACTION :
bits : 18 - 18 (1 bit)
access : read-write

EP9_SEQ :
bits : 19 - 19 (1 bit)
access : read-write

EP10_TRANSACTION :
bits : 20 - 20 (1 bit)
access : read-write

EP10_SEQ :
bits : 21 - 21 (1 bit)
access : read-write

EP11_TRANSACTION :
bits : 22 - 22 (1 bit)
access : read-write

EP11_SEQ :
bits : 23 - 23 (1 bit)
access : read-write

EP12_TRANSACTION :
bits : 24 - 24 (1 bit)
access : read-write

EP12_SEQ :
bits : 25 - 25 (1 bit)
access : read-write

EP13_TRANSACTION :
bits : 26 - 26 (1 bit)
access : read-write

EP13_SEQ :
bits : 27 - 27 (1 bit)
access : read-write

EP14_TRANSACTION :
bits : 28 - 28 (1 bit)
access : read-write

EP14_SEQ :
bits : 29 - 29 (1 bit)
access : read-write

EP15_TRANSACTION :
bits : 30 - 30 (1 bit)
access : read-write

EP15_SEQ :
bits : 31 - 31 (1 bit)
access : read-write


DEV_SM_WATCHDOG

Watchdog that forces the device state machine to idle and raises an interrupt if the device stays in a state that isn't idle for the configured limit. The counter is reset on every state transition. Set limit while enable is low and then set the enable.
address_offset : 0x114 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DEV_SM_WATCHDOG DEV_SM_WATCHDOG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LIMIT ENABLE RESET FIRED

LIMIT :
bits : 0 - 17 (18 bit)
access : read-write

ENABLE :
bits : 18 - 18 (1 bit)
access : read-write

RESET : Set to 1 to forcibly reset the device state machine on watchdog expiry
bits : 19 - 19 (1 bit)
access : read-write

FIRED :
bits : 20 - 20 (1 bit)
access : read-write


ADDR_ENDP5

Interrupt endpoint 5. Only valid for HOST mode.
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADDR_ENDP5 ADDR_ENDP5 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADDRESS ENDPOINT INTEP_DIR INTEP_PREAMBLE

ADDRESS : Device address
bits : 0 - 6 (7 bit)
access : read-write

ENDPOINT : Endpoint number of the interrupt endpoint
bits : 16 - 19 (4 bit)
access : read-write

INTEP_DIR : Direction of the interrupt endpoint. In=0, Out=1
bits : 25 - 25 (1 bit)
access : read-write

INTEP_PREAMBLE : Interrupt EP requires preamble (is a low speed device on a full speed hub)
bits : 26 - 26 (1 bit)
access : read-write


ADDR_ENDP6

Interrupt endpoint 6. Only valid for HOST mode.
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADDR_ENDP6 ADDR_ENDP6 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADDRESS ENDPOINT INTEP_DIR INTEP_PREAMBLE

ADDRESS : Device address
bits : 0 - 6 (7 bit)
access : read-write

ENDPOINT : Endpoint number of the interrupt endpoint
bits : 16 - 19 (4 bit)
access : read-write

INTEP_DIR : Direction of the interrupt endpoint. In=0, Out=1
bits : 25 - 25 (1 bit)
access : read-write

INTEP_PREAMBLE : Interrupt EP requires preamble (is a low speed device on a full speed hub)
bits : 26 - 26 (1 bit)
access : read-write


ADDR_ENDP7

Interrupt endpoint 7. Only valid for HOST mode.
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADDR_ENDP7 ADDR_ENDP7 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADDRESS ENDPOINT INTEP_DIR INTEP_PREAMBLE

ADDRESS : Device address
bits : 0 - 6 (7 bit)
access : read-write

ENDPOINT : Endpoint number of the interrupt endpoint
bits : 16 - 19 (4 bit)
access : read-write

INTEP_DIR : Direction of the interrupt endpoint. In=0, Out=1
bits : 25 - 25 (1 bit)
access : read-write

INTEP_PREAMBLE : Interrupt EP requires preamble (is a low speed device on a full speed hub)
bits : 26 - 26 (1 bit)
access : read-write


ADDR_ENDP8

Interrupt endpoint 8. Only valid for HOST mode.
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADDR_ENDP8 ADDR_ENDP8 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADDRESS ENDPOINT INTEP_DIR INTEP_PREAMBLE

ADDRESS : Device address
bits : 0 - 6 (7 bit)
access : read-write

ENDPOINT : Endpoint number of the interrupt endpoint
bits : 16 - 19 (4 bit)
access : read-write

INTEP_DIR : Direction of the interrupt endpoint. In=0, Out=1
bits : 25 - 25 (1 bit)
access : read-write

INTEP_PREAMBLE : Interrupt EP requires preamble (is a low speed device on a full speed hub)
bits : 26 - 26 (1 bit)
access : read-write


ADDR_ENDP9

Interrupt endpoint 9. Only valid for HOST mode.
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADDR_ENDP9 ADDR_ENDP9 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADDRESS ENDPOINT INTEP_DIR INTEP_PREAMBLE

ADDRESS : Device address
bits : 0 - 6 (7 bit)
access : read-write

ENDPOINT : Endpoint number of the interrupt endpoint
bits : 16 - 19 (4 bit)
access : read-write

INTEP_DIR : Direction of the interrupt endpoint. In=0, Out=1
bits : 25 - 25 (1 bit)
access : read-write

INTEP_PREAMBLE : Interrupt EP requires preamble (is a low speed device on a full speed hub)
bits : 26 - 26 (1 bit)
access : read-write


ADDR_ENDP10

Interrupt endpoint 10. Only valid for HOST mode.
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADDR_ENDP10 ADDR_ENDP10 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADDRESS ENDPOINT INTEP_DIR INTEP_PREAMBLE

ADDRESS : Device address
bits : 0 - 6 (7 bit)
access : read-write

ENDPOINT : Endpoint number of the interrupt endpoint
bits : 16 - 19 (4 bit)
access : read-write

INTEP_DIR : Direction of the interrupt endpoint. In=0, Out=1
bits : 25 - 25 (1 bit)
access : read-write

INTEP_PREAMBLE : Interrupt EP requires preamble (is a low speed device on a full speed hub)
bits : 26 - 26 (1 bit)
access : read-write


ADDR_ENDP11

Interrupt endpoint 11. Only valid for HOST mode.
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADDR_ENDP11 ADDR_ENDP11 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADDRESS ENDPOINT INTEP_DIR INTEP_PREAMBLE

ADDRESS : Device address
bits : 0 - 6 (7 bit)
access : read-write

ENDPOINT : Endpoint number of the interrupt endpoint
bits : 16 - 19 (4 bit)
access : read-write

INTEP_DIR : Direction of the interrupt endpoint. In=0, Out=1
bits : 25 - 25 (1 bit)
access : read-write

INTEP_PREAMBLE : Interrupt EP requires preamble (is a low speed device on a full speed hub)
bits : 26 - 26 (1 bit)
access : read-write


ADDR_ENDP12

Interrupt endpoint 12. Only valid for HOST mode.
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADDR_ENDP12 ADDR_ENDP12 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADDRESS ENDPOINT INTEP_DIR INTEP_PREAMBLE

ADDRESS : Device address
bits : 0 - 6 (7 bit)
access : read-write

ENDPOINT : Endpoint number of the interrupt endpoint
bits : 16 - 19 (4 bit)
access : read-write

INTEP_DIR : Direction of the interrupt endpoint. In=0, Out=1
bits : 25 - 25 (1 bit)
access : read-write

INTEP_PREAMBLE : Interrupt EP requires preamble (is a low speed device on a full speed hub)
bits : 26 - 26 (1 bit)
access : read-write


ADDR_ENDP13

Interrupt endpoint 13. Only valid for HOST mode.
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADDR_ENDP13 ADDR_ENDP13 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADDRESS ENDPOINT INTEP_DIR INTEP_PREAMBLE

ADDRESS : Device address
bits : 0 - 6 (7 bit)
access : read-write

ENDPOINT : Endpoint number of the interrupt endpoint
bits : 16 - 19 (4 bit)
access : read-write

INTEP_DIR : Direction of the interrupt endpoint. In=0, Out=1
bits : 25 - 25 (1 bit)
access : read-write

INTEP_PREAMBLE : Interrupt EP requires preamble (is a low speed device on a full speed hub)
bits : 26 - 26 (1 bit)
access : read-write


ADDR_ENDP14

Interrupt endpoint 14. Only valid for HOST mode.
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADDR_ENDP14 ADDR_ENDP14 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADDRESS ENDPOINT INTEP_DIR INTEP_PREAMBLE

ADDRESS : Device address
bits : 0 - 6 (7 bit)
access : read-write

ENDPOINT : Endpoint number of the interrupt endpoint
bits : 16 - 19 (4 bit)
access : read-write

INTEP_DIR : Direction of the interrupt endpoint. In=0, Out=1
bits : 25 - 25 (1 bit)
access : read-write

INTEP_PREAMBLE : Interrupt EP requires preamble (is a low speed device on a full speed hub)
bits : 26 - 26 (1 bit)
access : read-write


ADDR_ENDP15

Interrupt endpoint 15. Only valid for HOST mode.
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADDR_ENDP15 ADDR_ENDP15 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADDRESS ENDPOINT INTEP_DIR INTEP_PREAMBLE

ADDRESS : Device address
bits : 0 - 6 (7 bit)
access : read-write

ENDPOINT : Endpoint number of the interrupt endpoint
bits : 16 - 19 (4 bit)
access : read-write

INTEP_DIR : Direction of the interrupt endpoint. In=0, Out=1
bits : 25 - 25 (1 bit)
access : read-write

INTEP_PREAMBLE : Interrupt EP requires preamble (is a low speed device on a full speed hub)
bits : 26 - 26 (1 bit)
access : read-write


ADDR_ENDP1

Interrupt endpoint 1. Only valid for HOST mode.
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADDR_ENDP1 ADDR_ENDP1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADDRESS ENDPOINT INTEP_DIR INTEP_PREAMBLE

ADDRESS : Device address
bits : 0 - 6 (7 bit)
access : read-write

ENDPOINT : Endpoint number of the interrupt endpoint
bits : 16 - 19 (4 bit)
access : read-write

INTEP_DIR : Direction of the interrupt endpoint. In=0, Out=1
bits : 25 - 25 (1 bit)
access : read-write

INTEP_PREAMBLE : Interrupt EP requires preamble (is a low speed device on a full speed hub)
bits : 26 - 26 (1 bit)
access : read-write


MAIN_CTRL

Main control register
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MAIN_CTRL MAIN_CTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CONTROLLER_EN HOST_NDEVICE PHY_ISO SIM_TIMING

CONTROLLER_EN : Enable controller
bits : 0 - 0 (1 bit)
access : read-write

HOST_NDEVICE : Device mode = 0, Host mode = 1
bits : 1 - 1 (1 bit)
access : read-write

PHY_ISO : Isolates USB phy after controller power-up Remove isolation once software has configured the controller Not isolated = 0, Isolated = 1
bits : 2 - 2 (1 bit)
access : read-write

SIM_TIMING : Reduced timings for simulation
bits : 31 - 31 (1 bit)
access : read-write


SOF_WR

Set the SOF (Start of Frame) frame number in the host controller. The SOF packet is sent every 1ms and the host will increment the frame number by 1 each time.
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SOF_WR SOF_WR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 COUNT

COUNT :
bits : 0 - 10 (11 bit)
access : write-only


SOF_RD

Read the last SOF (Start of Frame) frame number seen. In device mode the last SOF received from the host. In host mode the last SOF sent by the host.
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SOF_RD SOF_RD read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 COUNT

COUNT :
bits : 0 - 10 (11 bit)
access : read-only


SIE_CTRL

SIE control register
address_offset : 0x4C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SIE_CTRL SIE_CTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 START_TRANS SEND_SETUP SEND_DATA RECEIVE_DATA STOP_TRANS PREAMBLE_EN SOF_SYNC SOF_EN KEEP_ALIVE_EN VBUS_EN RESUME RESET_BUS PULLDOWN_EN PULLUP_EN RPU_OPT TRANSCEIVER_PD EP0_STOP_ON_SHORT_PACKET DIRECT_DM DIRECT_DP DIRECT_EN EP0_INT_NAK EP0_INT_2BUF EP0_INT_1BUF EP0_DOUBLE_BUF EP0_INT_STALL

START_TRANS : Host: Start transaction
bits : 0 - 0 (1 bit)
access : write-only

SEND_SETUP : Host: Send Setup packet
bits : 1 - 1 (1 bit)
access : read-write

SEND_DATA : Host: Send transaction (OUT from host)
bits : 2 - 2 (1 bit)
access : read-write

RECEIVE_DATA : Host: Receive transaction (IN to host)
bits : 3 - 3 (1 bit)
access : read-write

STOP_TRANS : Host: Stop transaction
bits : 4 - 4 (1 bit)
access : write-only

PREAMBLE_EN : Host: Preable enable for LS device on FS hub
bits : 6 - 6 (1 bit)
access : read-write

SOF_SYNC : Host: Delay packet(s) until after SOF
bits : 8 - 8 (1 bit)
access : read-write

SOF_EN : Host: Enable SOF generation (for full speed bus)
bits : 9 - 9 (1 bit)
access : read-write

KEEP_ALIVE_EN : Host: Enable keep alive packet (for low speed bus)
bits : 10 - 10 (1 bit)
access : read-write

VBUS_EN : Host: Enable VBUS
bits : 11 - 11 (1 bit)
access : read-write

RESUME : Device: Remote wakeup. Device can initiate its own resume after suspend.
bits : 12 - 12 (1 bit)
access : write-only

RESET_BUS : Host: Reset bus
bits : 13 - 13 (1 bit)
access : write-only

PULLDOWN_EN : Host: Enable pull down resistors
bits : 15 - 15 (1 bit)
access : read-write

PULLUP_EN : Device: Enable pull up resistor
bits : 16 - 16 (1 bit)
access : read-write

RPU_OPT : Device: Pull-up strength (0=1K2, 1=2k3)
bits : 17 - 17 (1 bit)
access : read-write

TRANSCEIVER_PD : Power down bus transceiver
bits : 18 - 18 (1 bit)
access : read-write

EP0_STOP_ON_SHORT_PACKET : Device: Stop EP0 on a short packet.
bits : 19 - 19 (1 bit)
access : read-write

DIRECT_DM : Direct control of DM
bits : 24 - 24 (1 bit)
access : read-write

DIRECT_DP : Direct control of DP
bits : 25 - 25 (1 bit)
access : read-write

DIRECT_EN : Direct bus drive enable
bits : 26 - 26 (1 bit)
access : read-write

EP0_INT_NAK : Device: Set bit in EP_STATUS_STALL_NAK when EP0 sends a NAK
bits : 27 - 27 (1 bit)
access : read-write

EP0_INT_2BUF : Device: Set bit in BUFF_STATUS for every 2 buffers completed on EP0
bits : 28 - 28 (1 bit)
access : read-write

EP0_INT_1BUF : Device: Set bit in BUFF_STATUS for every buffer completed on EP0
bits : 29 - 29 (1 bit)
access : read-write

EP0_DOUBLE_BUF : Device: EP0 single buffered = 0, double buffered = 1
bits : 30 - 30 (1 bit)
access : read-write

EP0_INT_STALL : Device: Set bit in EP_STATUS_STALL_NAK when EP0 sends a STALL
bits : 31 - 31 (1 bit)
access : read-write


SIE_STATUS

SIE status register
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SIE_STATUS SIE_STATUS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VBUS_DETECTED LINE_STATE SUSPENDED SPEED VBUS_OVER_CURR RESUME RX_SHORT_PACKET CONNECTED SETUP_REC TRANS_COMPLETE BUS_RESET ENDPOINT_ERROR CRC_ERROR BIT_STUFF_ERROR RX_OVERFLOW RX_TIMEOUT NAK_REC STALL_REC ACK_REC DATA_SEQ_ERROR

VBUS_DETECTED : Device: VBUS Detected
bits : 0 - 0 (1 bit)
access : read-only

LINE_STATE : USB bus line state
bits : 2 - 3 (2 bit)
access : read-only

SUSPENDED : Bus in suspended state. Valid for device. Device will go into suspend if neither Keep Alive / SOF frames are enabled.
bits : 4 - 4 (1 bit)
access : read-write

SPEED : Host: device speed. Disconnected = 00, LS = 01, FS = 10
bits : 8 - 9 (2 bit)
access : read-only

VBUS_OVER_CURR : VBUS over current detected
bits : 10 - 10 (1 bit)
access : read-only

RESUME : Host: Device has initiated a remote resume. Device: host has initiated a resume.
bits : 11 - 11 (1 bit)
access : read-write

RX_SHORT_PACKET : Device or Host has received a short packet. This is when the data received is less than configured in the buffer control register. Device: If using double buffered mode on device the buffer select will not be toggled after writing status back to the buffer control register. This is to prevent any further transactions on that endpoint until the user has reset the buffer control registers. Host: the current transfer will be stopped early.
bits : 12 - 12 (1 bit)
access : read-write

CONNECTED : Device: connected
bits : 16 - 16 (1 bit)
access : read-only

SETUP_REC : Device: Setup packet received
bits : 17 - 17 (1 bit)
access : read-write

TRANS_COMPLETE : Transaction complete. Raised by device if: * An IN or OUT packet is sent with the `LAST_BUFF` bit set in the buffer control register Raised by host if: * A setup packet is sent when no data in or data out transaction follows * An IN packet is received and the `LAST_BUFF` bit is set in the buffer control register * An IN packet is received with zero length * An OUT packet is sent and the `LAST_BUFF` bit is set
bits : 18 - 18 (1 bit)
access : read-write

BUS_RESET : Device: bus reset received
bits : 19 - 19 (1 bit)
access : read-write

ENDPOINT_ERROR : An endpoint has encountered an error. Read the ep_rx_error and ep_tx_error registers to find out which endpoint had an error.
bits : 23 - 23 (1 bit)
access : read-write

CRC_ERROR : CRC Error. Raised by the Serial RX engine.
bits : 24 - 24 (1 bit)
access : read-write

BIT_STUFF_ERROR : Bit Stuff Error. Raised by the Serial RX engine.
bits : 25 - 25 (1 bit)
access : read-write

RX_OVERFLOW : RX overflow is raised by the Serial RX engine if the incoming data is too fast.
bits : 26 - 26 (1 bit)
access : read-write

RX_TIMEOUT : RX timeout is raised by both the host and device if an ACK is not received in the maximum time specified by the USB spec.
bits : 27 - 27 (1 bit)
access : read-write

NAK_REC : Host: NAK received
bits : 28 - 28 (1 bit)
access : read-write

STALL_REC : Host: STALL received
bits : 29 - 29 (1 bit)
access : read-write

ACK_REC : ACK received. Raised by both host and device.
bits : 30 - 30 (1 bit)
access : read-write

DATA_SEQ_ERROR : Data Sequence Error. The device can raise a sequence error in the following conditions: * A SETUP packet is received followed by a DATA1 packet (data phase should always be DATA0) * An OUT packet is received from the host but doesn't match the data pid in the buffer control register read from DPSRAM The host can raise a data sequence error in the following conditions: * An IN packet from the device has the wrong data PID
bits : 31 - 31 (1 bit)
access : read-write


INT_EP_CTRL

interrupt endpoint control register
address_offset : 0x54 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

INT_EP_CTRL INT_EP_CTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INT_EP_ACTIVE

INT_EP_ACTIVE : Host: Enable interrupt endpoint 1 -> 15
bits : 1 - 15 (15 bit)
access : read-write


BUFF_STATUS

Buffer status register. A bit set here indicates that a buffer has completed on the endpoint (if the buffer interrupt is enabled). It is possible for 2 buffers to be completed, so clearing the buffer status bit may instantly re set it on the next clock cycle.
address_offset : 0x58 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BUFF_STATUS BUFF_STATUS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EP0_IN EP0_OUT EP1_IN EP1_OUT EP2_IN EP2_OUT EP3_IN EP3_OUT EP4_IN EP4_OUT EP5_IN EP5_OUT EP6_IN EP6_OUT EP7_IN EP7_OUT EP8_IN EP8_OUT EP9_IN EP9_OUT EP10_IN EP10_OUT EP11_IN EP11_OUT EP12_IN EP12_OUT EP13_IN EP13_OUT EP14_IN EP14_OUT EP15_IN EP15_OUT

EP0_IN :
bits : 0 - 0 (1 bit)
access : read-write

EP0_OUT :
bits : 1 - 1 (1 bit)
access : read-write

EP1_IN :
bits : 2 - 2 (1 bit)
access : read-write

EP1_OUT :
bits : 3 - 3 (1 bit)
access : read-write

EP2_IN :
bits : 4 - 4 (1 bit)
access : read-write

EP2_OUT :
bits : 5 - 5 (1 bit)
access : read-write

EP3_IN :
bits : 6 - 6 (1 bit)
access : read-write

EP3_OUT :
bits : 7 - 7 (1 bit)
access : read-write

EP4_IN :
bits : 8 - 8 (1 bit)
access : read-write

EP4_OUT :
bits : 9 - 9 (1 bit)
access : read-write

EP5_IN :
bits : 10 - 10 (1 bit)
access : read-write

EP5_OUT :
bits : 11 - 11 (1 bit)
access : read-write

EP6_IN :
bits : 12 - 12 (1 bit)
access : read-write

EP6_OUT :
bits : 13 - 13 (1 bit)
access : read-write

EP7_IN :
bits : 14 - 14 (1 bit)
access : read-write

EP7_OUT :
bits : 15 - 15 (1 bit)
access : read-write

EP8_IN :
bits : 16 - 16 (1 bit)
access : read-write

EP8_OUT :
bits : 17 - 17 (1 bit)
access : read-write

EP9_IN :
bits : 18 - 18 (1 bit)
access : read-write

EP9_OUT :
bits : 19 - 19 (1 bit)
access : read-write

EP10_IN :
bits : 20 - 20 (1 bit)
access : read-write

EP10_OUT :
bits : 21 - 21 (1 bit)
access : read-write

EP11_IN :
bits : 22 - 22 (1 bit)
access : read-write

EP11_OUT :
bits : 23 - 23 (1 bit)
access : read-write

EP12_IN :
bits : 24 - 24 (1 bit)
access : read-write

EP12_OUT :
bits : 25 - 25 (1 bit)
access : read-write

EP13_IN :
bits : 26 - 26 (1 bit)
access : read-write

EP13_OUT :
bits : 27 - 27 (1 bit)
access : read-write

EP14_IN :
bits : 28 - 28 (1 bit)
access : read-write

EP14_OUT :
bits : 29 - 29 (1 bit)
access : read-write

EP15_IN :
bits : 30 - 30 (1 bit)
access : read-write

EP15_OUT :
bits : 31 - 31 (1 bit)
access : read-write


BUFF_CPU_SHOULD_HANDLE

Which of the double buffers should be handled. Only valid if using an interrupt per buffer (i.e. not per 2 buffers). Not valid for host interrupt endpoint polling because they are only single buffered.
address_offset : 0x5C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BUFF_CPU_SHOULD_HANDLE BUFF_CPU_SHOULD_HANDLE read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EP0_IN EP0_OUT EP1_IN EP1_OUT EP2_IN EP2_OUT EP3_IN EP3_OUT EP4_IN EP4_OUT EP5_IN EP5_OUT EP6_IN EP6_OUT EP7_IN EP7_OUT EP8_IN EP8_OUT EP9_IN EP9_OUT EP10_IN EP10_OUT EP11_IN EP11_OUT EP12_IN EP12_OUT EP13_IN EP13_OUT EP14_IN EP14_OUT EP15_IN EP15_OUT

EP0_IN :
bits : 0 - 0 (1 bit)
access : read-only

EP0_OUT :
bits : 1 - 1 (1 bit)
access : read-only

EP1_IN :
bits : 2 - 2 (1 bit)
access : read-only

EP1_OUT :
bits : 3 - 3 (1 bit)
access : read-only

EP2_IN :
bits : 4 - 4 (1 bit)
access : read-only

EP2_OUT :
bits : 5 - 5 (1 bit)
access : read-only

EP3_IN :
bits : 6 - 6 (1 bit)
access : read-only

EP3_OUT :
bits : 7 - 7 (1 bit)
access : read-only

EP4_IN :
bits : 8 - 8 (1 bit)
access : read-only

EP4_OUT :
bits : 9 - 9 (1 bit)
access : read-only

EP5_IN :
bits : 10 - 10 (1 bit)
access : read-only

EP5_OUT :
bits : 11 - 11 (1 bit)
access : read-only

EP6_IN :
bits : 12 - 12 (1 bit)
access : read-only

EP6_OUT :
bits : 13 - 13 (1 bit)
access : read-only

EP7_IN :
bits : 14 - 14 (1 bit)
access : read-only

EP7_OUT :
bits : 15 - 15 (1 bit)
access : read-only

EP8_IN :
bits : 16 - 16 (1 bit)
access : read-only

EP8_OUT :
bits : 17 - 17 (1 bit)
access : read-only

EP9_IN :
bits : 18 - 18 (1 bit)
access : read-only

EP9_OUT :
bits : 19 - 19 (1 bit)
access : read-only

EP10_IN :
bits : 20 - 20 (1 bit)
access : read-only

EP10_OUT :
bits : 21 - 21 (1 bit)
access : read-only

EP11_IN :
bits : 22 - 22 (1 bit)
access : read-only

EP11_OUT :
bits : 23 - 23 (1 bit)
access : read-only

EP12_IN :
bits : 24 - 24 (1 bit)
access : read-only

EP12_OUT :
bits : 25 - 25 (1 bit)
access : read-only

EP13_IN :
bits : 26 - 26 (1 bit)
access : read-only

EP13_OUT :
bits : 27 - 27 (1 bit)
access : read-only

EP14_IN :
bits : 28 - 28 (1 bit)
access : read-only

EP14_OUT :
bits : 29 - 29 (1 bit)
access : read-only

EP15_IN :
bits : 30 - 30 (1 bit)
access : read-only

EP15_OUT :
bits : 31 - 31 (1 bit)
access : read-only


EP_ABORT

Device only: Can be set to ignore the buffer control register for this endpoint in case you would like to revoke a buffer. A NAK will be sent for every access to the endpoint until this bit is cleared. A corresponding bit in `EP_ABORT_DONE` is set when it is safe to modify the buffer control register.
address_offset : 0x60 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EP_ABORT EP_ABORT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EP0_IN EP0_OUT EP1_IN EP1_OUT EP2_IN EP2_OUT EP3_IN EP3_OUT EP4_IN EP4_OUT EP5_IN EP5_OUT EP6_IN EP6_OUT EP7_IN EP7_OUT EP8_IN EP8_OUT EP9_IN EP9_OUT EP10_IN EP10_OUT EP11_IN EP11_OUT EP12_IN EP12_OUT EP13_IN EP13_OUT EP14_IN EP14_OUT EP15_IN EP15_OUT

EP0_IN :
bits : 0 - 0 (1 bit)
access : read-write

EP0_OUT :
bits : 1 - 1 (1 bit)
access : read-write

EP1_IN :
bits : 2 - 2 (1 bit)
access : read-write

EP1_OUT :
bits : 3 - 3 (1 bit)
access : read-write

EP2_IN :
bits : 4 - 4 (1 bit)
access : read-write

EP2_OUT :
bits : 5 - 5 (1 bit)
access : read-write

EP3_IN :
bits : 6 - 6 (1 bit)
access : read-write

EP3_OUT :
bits : 7 - 7 (1 bit)
access : read-write

EP4_IN :
bits : 8 - 8 (1 bit)
access : read-write

EP4_OUT :
bits : 9 - 9 (1 bit)
access : read-write

EP5_IN :
bits : 10 - 10 (1 bit)
access : read-write

EP5_OUT :
bits : 11 - 11 (1 bit)
access : read-write

EP6_IN :
bits : 12 - 12 (1 bit)
access : read-write

EP6_OUT :
bits : 13 - 13 (1 bit)
access : read-write

EP7_IN :
bits : 14 - 14 (1 bit)
access : read-write

EP7_OUT :
bits : 15 - 15 (1 bit)
access : read-write

EP8_IN :
bits : 16 - 16 (1 bit)
access : read-write

EP8_OUT :
bits : 17 - 17 (1 bit)
access : read-write

EP9_IN :
bits : 18 - 18 (1 bit)
access : read-write

EP9_OUT :
bits : 19 - 19 (1 bit)
access : read-write

EP10_IN :
bits : 20 - 20 (1 bit)
access : read-write

EP10_OUT :
bits : 21 - 21 (1 bit)
access : read-write

EP11_IN :
bits : 22 - 22 (1 bit)
access : read-write

EP11_OUT :
bits : 23 - 23 (1 bit)
access : read-write

EP12_IN :
bits : 24 - 24 (1 bit)
access : read-write

EP12_OUT :
bits : 25 - 25 (1 bit)
access : read-write

EP13_IN :
bits : 26 - 26 (1 bit)
access : read-write

EP13_OUT :
bits : 27 - 27 (1 bit)
access : read-write

EP14_IN :
bits : 28 - 28 (1 bit)
access : read-write

EP14_OUT :
bits : 29 - 29 (1 bit)
access : read-write

EP15_IN :
bits : 30 - 30 (1 bit)
access : read-write

EP15_OUT :
bits : 31 - 31 (1 bit)
access : read-write


EP_ABORT_DONE

Device only: Used in conjunction with `EP_ABORT`. Set once an endpoint is idle so the programmer knows it is safe to modify the buffer control register.
address_offset : 0x64 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EP_ABORT_DONE EP_ABORT_DONE read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EP0_IN EP0_OUT EP1_IN EP1_OUT EP2_IN EP2_OUT EP3_IN EP3_OUT EP4_IN EP4_OUT EP5_IN EP5_OUT EP6_IN EP6_OUT EP7_IN EP7_OUT EP8_IN EP8_OUT EP9_IN EP9_OUT EP10_IN EP10_OUT EP11_IN EP11_OUT EP12_IN EP12_OUT EP13_IN EP13_OUT EP14_IN EP14_OUT EP15_IN EP15_OUT

EP0_IN :
bits : 0 - 0 (1 bit)
access : read-write

EP0_OUT :
bits : 1 - 1 (1 bit)
access : read-write

EP1_IN :
bits : 2 - 2 (1 bit)
access : read-write

EP1_OUT :
bits : 3 - 3 (1 bit)
access : read-write

EP2_IN :
bits : 4 - 4 (1 bit)
access : read-write

EP2_OUT :
bits : 5 - 5 (1 bit)
access : read-write

EP3_IN :
bits : 6 - 6 (1 bit)
access : read-write

EP3_OUT :
bits : 7 - 7 (1 bit)
access : read-write

EP4_IN :
bits : 8 - 8 (1 bit)
access : read-write

EP4_OUT :
bits : 9 - 9 (1 bit)
access : read-write

EP5_IN :
bits : 10 - 10 (1 bit)
access : read-write

EP5_OUT :
bits : 11 - 11 (1 bit)
access : read-write

EP6_IN :
bits : 12 - 12 (1 bit)
access : read-write

EP6_OUT :
bits : 13 - 13 (1 bit)
access : read-write

EP7_IN :
bits : 14 - 14 (1 bit)
access : read-write

EP7_OUT :
bits : 15 - 15 (1 bit)
access : read-write

EP8_IN :
bits : 16 - 16 (1 bit)
access : read-write

EP8_OUT :
bits : 17 - 17 (1 bit)
access : read-write

EP9_IN :
bits : 18 - 18 (1 bit)
access : read-write

EP9_OUT :
bits : 19 - 19 (1 bit)
access : read-write

EP10_IN :
bits : 20 - 20 (1 bit)
access : read-write

EP10_OUT :
bits : 21 - 21 (1 bit)
access : read-write

EP11_IN :
bits : 22 - 22 (1 bit)
access : read-write

EP11_OUT :
bits : 23 - 23 (1 bit)
access : read-write

EP12_IN :
bits : 24 - 24 (1 bit)
access : read-write

EP12_OUT :
bits : 25 - 25 (1 bit)
access : read-write

EP13_IN :
bits : 26 - 26 (1 bit)
access : read-write

EP13_OUT :
bits : 27 - 27 (1 bit)
access : read-write

EP14_IN :
bits : 28 - 28 (1 bit)
access : read-write

EP14_OUT :
bits : 29 - 29 (1 bit)
access : read-write

EP15_IN :
bits : 30 - 30 (1 bit)
access : read-write

EP15_OUT :
bits : 31 - 31 (1 bit)
access : read-write


EP_STALL_ARM

Device: this bit must be set in conjunction with the `STALL` bit in the buffer control register to send a STALL on EP0. The device controller clears these bits when a SETUP packet is received because the USB spec requires that a STALL condition is cleared when a SETUP packet is received.
address_offset : 0x68 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EP_STALL_ARM EP_STALL_ARM read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EP0_IN EP0_OUT

EP0_IN :
bits : 0 - 0 (1 bit)
access : read-write

EP0_OUT :
bits : 1 - 1 (1 bit)
access : read-write


NAK_POLL

Used by the host controller. Sets the wait time in microseconds before trying again if the device replies with a NAK.
address_offset : 0x6C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NAK_POLL NAK_POLL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DELAY_LS RETRY_COUNT_LO DELAY_FS STOP_EPX_ON_NAK EPX_STOPPED_ON_NAK RETRY_COUNT_HI

DELAY_LS : NAK polling interval for a low speed device
bits : 0 - 9 (10 bit)
access : read-write

RETRY_COUNT_LO : Bits 5:0 of nak_retry_count
bits : 10 - 15 (6 bit)
access : read-only

DELAY_FS : NAK polling interval for a full speed device
bits : 16 - 25 (10 bit)
access : read-write

STOP_EPX_ON_NAK : Stop polling epx when a nak is received
bits : 26 - 26 (1 bit)
access : read-write

EPX_STOPPED_ON_NAK : EPX polling has stopped because a nak was received
bits : 27 - 27 (1 bit)
access : read-write

RETRY_COUNT_HI : Bits 9:6 of nak_retry count
bits : 28 - 31 (4 bit)
access : read-only


EP_STATUS_STALL_NAK

Device: bits are set when the `IRQ_ON_NAK` or `IRQ_ON_STALL` bits are set. For EP0 this comes from `SIE_CTRL`. For all other endpoints it comes from the endpoint control register.
address_offset : 0x70 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EP_STATUS_STALL_NAK EP_STATUS_STALL_NAK read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EP0_IN EP0_OUT EP1_IN EP1_OUT EP2_IN EP2_OUT EP3_IN EP3_OUT EP4_IN EP4_OUT EP5_IN EP5_OUT EP6_IN EP6_OUT EP7_IN EP7_OUT EP8_IN EP8_OUT EP9_IN EP9_OUT EP10_IN EP10_OUT EP11_IN EP11_OUT EP12_IN EP12_OUT EP13_IN EP13_OUT EP14_IN EP14_OUT EP15_IN EP15_OUT

EP0_IN :
bits : 0 - 0 (1 bit)
access : read-write

EP0_OUT :
bits : 1 - 1 (1 bit)
access : read-write

EP1_IN :
bits : 2 - 2 (1 bit)
access : read-write

EP1_OUT :
bits : 3 - 3 (1 bit)
access : read-write

EP2_IN :
bits : 4 - 4 (1 bit)
access : read-write

EP2_OUT :
bits : 5 - 5 (1 bit)
access : read-write

EP3_IN :
bits : 6 - 6 (1 bit)
access : read-write

EP3_OUT :
bits : 7 - 7 (1 bit)
access : read-write

EP4_IN :
bits : 8 - 8 (1 bit)
access : read-write

EP4_OUT :
bits : 9 - 9 (1 bit)
access : read-write

EP5_IN :
bits : 10 - 10 (1 bit)
access : read-write

EP5_OUT :
bits : 11 - 11 (1 bit)
access : read-write

EP6_IN :
bits : 12 - 12 (1 bit)
access : read-write

EP6_OUT :
bits : 13 - 13 (1 bit)
access : read-write

EP7_IN :
bits : 14 - 14 (1 bit)
access : read-write

EP7_OUT :
bits : 15 - 15 (1 bit)
access : read-write

EP8_IN :
bits : 16 - 16 (1 bit)
access : read-write

EP8_OUT :
bits : 17 - 17 (1 bit)
access : read-write

EP9_IN :
bits : 18 - 18 (1 bit)
access : read-write

EP9_OUT :
bits : 19 - 19 (1 bit)
access : read-write

EP10_IN :
bits : 20 - 20 (1 bit)
access : read-write

EP10_OUT :
bits : 21 - 21 (1 bit)
access : read-write

EP11_IN :
bits : 22 - 22 (1 bit)
access : read-write

EP11_OUT :
bits : 23 - 23 (1 bit)
access : read-write

EP12_IN :
bits : 24 - 24 (1 bit)
access : read-write

EP12_OUT :
bits : 25 - 25 (1 bit)
access : read-write

EP13_IN :
bits : 26 - 26 (1 bit)
access : read-write

EP13_OUT :
bits : 27 - 27 (1 bit)
access : read-write

EP14_IN :
bits : 28 - 28 (1 bit)
access : read-write

EP14_OUT :
bits : 29 - 29 (1 bit)
access : read-write

EP15_IN :
bits : 30 - 30 (1 bit)
access : read-write

EP15_OUT :
bits : 31 - 31 (1 bit)
access : read-write


USB_MUXING

Where to connect the USB controller. Should be to_phy by default.
address_offset : 0x74 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USB_MUXING USB_MUXING read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TO_PHY TO_EXTPHY TO_DIGITAL_PAD SOFTCON USBPHY_AS_GPIO SWAP_DPDM

TO_PHY :
bits : 0 - 0 (1 bit)
access : read-write

TO_EXTPHY :
bits : 1 - 1 (1 bit)
access : read-write

TO_DIGITAL_PAD :
bits : 2 - 2 (1 bit)
access : read-write

SOFTCON :
bits : 3 - 3 (1 bit)
access : read-write

USBPHY_AS_GPIO : Use the usb DP and DM pins as GPIO pins instead of connecting them to the USB controller.
bits : 4 - 4 (1 bit)
access : read-write

SWAP_DPDM : Swap the USB PHY DP and DM pins and all related controls and flip receive differential data. Can be used to switch USB DP/DP on the PCB. This is done at a low level so overrides all other controls.
bits : 31 - 31 (1 bit)
access : read-write


USB_PWR

Overrides for the power signals in the event that the VBUS signals are not hooked up to GPIO. Set the value of the override and then the override enable to switch over to the override value.
address_offset : 0x78 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USB_PWR USB_PWR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VBUS_EN VBUS_EN_OVERRIDE_EN VBUS_DETECT VBUS_DETECT_OVERRIDE_EN OVERCURR_DETECT OVERCURR_DETECT_EN

VBUS_EN :
bits : 0 - 0 (1 bit)
access : read-write

VBUS_EN_OVERRIDE_EN :
bits : 1 - 1 (1 bit)
access : read-write

VBUS_DETECT :
bits : 2 - 2 (1 bit)
access : read-write

VBUS_DETECT_OVERRIDE_EN :
bits : 3 - 3 (1 bit)
access : read-write

OVERCURR_DETECT :
bits : 4 - 4 (1 bit)
access : read-write

OVERCURR_DETECT_EN :
bits : 5 - 5 (1 bit)
access : read-write


USBPHY_DIRECT

This register allows for direct control of the USB phy. Use in conjunction with usbphy_direct_override register to enable each override bit.
address_offset : 0x7C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USBPHY_DIRECT USBPHY_DIRECT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DP_PULLUP_HISEL DP_PULLUP_EN DP_PULLDN_EN DM_PULLUP_HISEL DM_PULLUP_EN DM_PULLDN_EN TX_DP_OE TX_DM_OE TX_DP TX_DM RX_PD TX_PD TX_FSSLEW TX_DIFFMODE RX_DD RX_DP RX_DM DP_OVCN DM_OVCN DP_OVV DM_OVV RX_DD_OVERRIDE RX_DP_OVERRIDE RX_DM_OVERRIDE

DP_PULLUP_HISEL : Enable the second DP pull up resistor. 0 - Pull = Rpu2 1 - Pull = Rpu1 + Rpu2
bits : 0 - 0 (1 bit)
access : read-write

DP_PULLUP_EN : DP pull up enable
bits : 1 - 1 (1 bit)
access : read-write

DP_PULLDN_EN : DP pull down enable
bits : 2 - 2 (1 bit)
access : read-write

DM_PULLUP_HISEL : Enable the second DM pull up resistor. 0 - Pull = Rpu2 1 - Pull = Rpu1 + Rpu2
bits : 4 - 4 (1 bit)
access : read-write

DM_PULLUP_EN : DM pull up enable
bits : 5 - 5 (1 bit)
access : read-write

DM_PULLDN_EN : DM pull down enable
bits : 6 - 6 (1 bit)
access : read-write

TX_DP_OE : Output enable. If TX_DIFFMODE=1, OE for DPP/DPM diff pair. 0 - DPP/DPM in Hi-Z state 1 - DPP/DPM driving If TX_DIFFMODE=0, OE for DPP only. 0 - DPP in Hi-Z state 1 - DPP driving
bits : 8 - 8 (1 bit)
access : read-write

TX_DM_OE : Output enable. If TX_DIFFMODE=1, Ignored. If TX_DIFFMODE=0, OE for DPM only. 0 - DPM in Hi-Z state 1 - DPM driving
bits : 9 - 9 (1 bit)
access : read-write

TX_DP : Output data. If TX_DIFFMODE=1, Drives DPP/DPM diff pair. TX_DP_OE=1 to enable drive. DPP=TX_DP, DPM=~TX_DP If TX_DIFFMODE=0, Drives DPP only. TX_DP_OE=1 to enable drive. DPP=TX_DP
bits : 10 - 10 (1 bit)
access : read-write

TX_DM : Output data. TX_DIFFMODE=1, Ignored TX_DIFFMODE=0, Drives DPM only. TX_DM_OE=1 to enable drive. DPM=TX_DM
bits : 11 - 11 (1 bit)
access : read-write

RX_PD : RX power down override (if override enable is set). 1 = powered down.
bits : 12 - 12 (1 bit)
access : read-write

TX_PD : TX power down override (if override enable is set). 1 = powered down.
bits : 13 - 13 (1 bit)
access : read-write

TX_FSSLEW : TX_FSSLEW=0: Low speed slew rate TX_FSSLEW=1: Full speed slew rate
bits : 14 - 14 (1 bit)
access : read-write

TX_DIFFMODE : TX_DIFFMODE=0: Single ended mode TX_DIFFMODE=1: Differential drive mode (TX_DM, TX_DM_OE ignored)
bits : 15 - 15 (1 bit)
access : read-write

RX_DD : Differential RX
bits : 16 - 16 (1 bit)
access : read-only

RX_DP : DPP pin state
bits : 17 - 17 (1 bit)
access : read-only

RX_DM : DPM pin state
bits : 18 - 18 (1 bit)
access : read-only

DP_OVCN : DP overcurrent
bits : 19 - 19 (1 bit)
access : read-only

DM_OVCN : DM overcurrent
bits : 20 - 20 (1 bit)
access : read-only

DP_OVV : DP over voltage
bits : 21 - 21 (1 bit)
access : read-only

DM_OVV : DM over voltage
bits : 22 - 22 (1 bit)
access : read-only

RX_DD_OVERRIDE : Override rx_dd value into controller
bits : 23 - 23 (1 bit)
access : read-write

RX_DP_OVERRIDE : Override rx_dp value into controller
bits : 24 - 24 (1 bit)
access : read-write

RX_DM_OVERRIDE : Override rx_dm value into controller
bits : 25 - 25 (1 bit)
access : read-write


ADDR_ENDP2

Interrupt endpoint 2. Only valid for HOST mode.
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADDR_ENDP2 ADDR_ENDP2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADDRESS ENDPOINT INTEP_DIR INTEP_PREAMBLE

ADDRESS : Device address
bits : 0 - 6 (7 bit)
access : read-write

ENDPOINT : Endpoint number of the interrupt endpoint
bits : 16 - 19 (4 bit)
access : read-write

INTEP_DIR : Direction of the interrupt endpoint. In=0, Out=1
bits : 25 - 25 (1 bit)
access : read-write

INTEP_PREAMBLE : Interrupt EP requires preamble (is a low speed device on a full speed hub)
bits : 26 - 26 (1 bit)
access : read-write


USBPHY_DIRECT_OVERRIDE

Override enable for each control in usbphy_direct
address_offset : 0x80 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USBPHY_DIRECT_OVERRIDE USBPHY_DIRECT_OVERRIDE read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DP_PULLUP_HISEL_OVERRIDE_EN DM_PULLUP_HISEL_OVERRIDE_EN DP_PULLUP_EN_OVERRIDE_EN DP_PULLDN_EN_OVERRIDE_EN DM_PULLDN_EN_OVERRIDE_EN TX_DP_OE_OVERRIDE_EN TX_DM_OE_OVERRIDE_EN TX_DP_OVERRIDE_EN TX_DM_OVERRIDE_EN RX_PD_OVERRIDE_EN TX_PD_OVERRIDE_EN TX_FSSLEW_OVERRIDE_EN DM_PULLUP_OVERRIDE_EN TX_DIFFMODE_OVERRIDE_EN RX_DD_OVERRIDE_EN RX_DP_OVERRIDE_EN RX_DM_OVERRIDE_EN

DP_PULLUP_HISEL_OVERRIDE_EN :
bits : 0 - 0 (1 bit)
access : read-write

DM_PULLUP_HISEL_OVERRIDE_EN :
bits : 1 - 1 (1 bit)
access : read-write

DP_PULLUP_EN_OVERRIDE_EN :
bits : 2 - 2 (1 bit)
access : read-write

DP_PULLDN_EN_OVERRIDE_EN :
bits : 3 - 3 (1 bit)
access : read-write

DM_PULLDN_EN_OVERRIDE_EN :
bits : 4 - 4 (1 bit)
access : read-write

TX_DP_OE_OVERRIDE_EN :
bits : 5 - 5 (1 bit)
access : read-write

TX_DM_OE_OVERRIDE_EN :
bits : 6 - 6 (1 bit)
access : read-write

TX_DP_OVERRIDE_EN :
bits : 7 - 7 (1 bit)
access : read-write

TX_DM_OVERRIDE_EN :
bits : 8 - 8 (1 bit)
access : read-write

RX_PD_OVERRIDE_EN :
bits : 9 - 9 (1 bit)
access : read-write

TX_PD_OVERRIDE_EN :
bits : 10 - 10 (1 bit)
access : read-write

TX_FSSLEW_OVERRIDE_EN :
bits : 11 - 11 (1 bit)
access : read-write

DM_PULLUP_OVERRIDE_EN :
bits : 12 - 12 (1 bit)
access : read-write

TX_DIFFMODE_OVERRIDE_EN :
bits : 15 - 15 (1 bit)
access : read-write

RX_DD_OVERRIDE_EN :
bits : 16 - 16 (1 bit)
access : read-write

RX_DP_OVERRIDE_EN :
bits : 17 - 17 (1 bit)
access : read-write

RX_DM_OVERRIDE_EN :
bits : 18 - 18 (1 bit)
access : read-write


USBPHY_TRIM

Used to adjust trim values of USB phy pull down resistors.
address_offset : 0x84 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USBPHY_TRIM USBPHY_TRIM read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DP_PULLDN_TRIM DM_PULLDN_TRIM

DP_PULLDN_TRIM : Value to drive to USB PHY DP pulldown resistor trim control Experimental data suggests that the reset value will work, but this register allows adjustment if required
bits : 0 - 4 (5 bit)
access : read-write

DM_PULLDN_TRIM : Value to drive to USB PHY DM pulldown resistor trim control Experimental data suggests that the reset value will work, but this register allows adjustment if required
bits : 8 - 12 (5 bit)
access : read-write


LINESTATE_TUNING

Used for debug only.
address_offset : 0x88 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

LINESTATE_TUNING LINESTATE_TUNING read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RCV_DELAY LINESTATE_DELAY MULTI_HUB_FIX DEV_BUFF_CONTROL_DOUBLE_READ_FIX SIE_RX_BITSTUFF_FIX SIE_RX_CHATTER_SE0_FIX DEV_RX_ERR_QUIESCE DEV_LS_WAKE_FIX SPARE_FIX

RCV_DELAY : Device - register the received data to account for hub bit dribble before EOP. Only affects certain hubs.
bits : 0 - 0 (1 bit)
access : read-write

LINESTATE_DELAY : Device/Host - add an extra 1-bit debounce of linestate sampling.
bits : 1 - 1 (1 bit)
access : read-write

MULTI_HUB_FIX : Host - increase inter-packet and turnaround timeouts to accommodate worst-case hub delays.
bits : 2 - 2 (1 bit)
access : read-write

DEV_BUFF_CONTROL_DOUBLE_READ_FIX : Device - the controller FSM performs two reads of the buffer status memory address to avoid sampling metastable data. An enabled buffer is only used if both reads match.
bits : 3 - 3 (1 bit)
access : read-write

SIE_RX_BITSTUFF_FIX : RX - when a bitstuff error is signalled by rx_dasm, unconditionally terminate RX decode to avoid a hang during certain packet phases.
bits : 4 - 4 (1 bit)
access : read-write

SIE_RX_CHATTER_SE0_FIX : RX - when recovering from line chatter or bitstuff errors, treat SE0 as the end of chatter as well as 8 consecutive idle bits.
bits : 5 - 5 (1 bit)
access : read-write

DEV_RX_ERR_QUIESCE : Device - suppress repeated errors until the device FSM is next in the process of decoding an inbound packet.
bits : 6 - 6 (1 bit)
access : read-write

DEV_LS_WAKE_FIX : Device - exit suspend on any non-idle signalling, not qualified with a 1ms timer
bits : 7 - 7 (1 bit)
access : read-write

SPARE_FIX :
bits : 8 - 11 (4 bit)
access : read-write


INTR

Raw Interrupts
address_offset : 0x8C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

INTR INTR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HOST_CONN_DIS HOST_RESUME HOST_SOF TRANS_COMPLETE BUFF_STATUS ERROR_DATA_SEQ ERROR_RX_TIMEOUT ERROR_RX_OVERFLOW ERROR_BIT_STUFF ERROR_CRC STALL VBUS_DETECT BUS_RESET DEV_CONN_DIS DEV_SUSPEND DEV_RESUME_FROM_HOST SETUP_REQ DEV_SOF ABORT_DONE EP_STALL_NAK RX_SHORT_PACKET ENDPOINT_ERROR DEV_SM_WATCHDOG_FIRED EPX_STOPPED_ON_NAK

HOST_CONN_DIS : Host: raised when a device is connected or disconnected (i.e. when SIE_STATUS.SPEED changes). Cleared by writing to SIE_STATUS.SPEED
bits : 0 - 0 (1 bit)
access : read-only

HOST_RESUME : Host: raised when a device wakes up the host. Cleared by writing to SIE_STATUS.RESUME
bits : 1 - 1 (1 bit)
access : read-only

HOST_SOF : Host: raised every time the host sends a SOF (Start of Frame). Cleared by reading SOF_RD
bits : 2 - 2 (1 bit)
access : read-only

TRANS_COMPLETE : Raised every time SIE_STATUS.TRANS_COMPLETE is set. Clear by writing to this bit.
bits : 3 - 3 (1 bit)
access : read-only

BUFF_STATUS : Raised when any bit in BUFF_STATUS is set. Clear by clearing all bits in BUFF_STATUS.
bits : 4 - 4 (1 bit)
access : read-only

ERROR_DATA_SEQ : Source: SIE_STATUS.DATA_SEQ_ERROR
bits : 5 - 5 (1 bit)
access : read-only

ERROR_RX_TIMEOUT : Source: SIE_STATUS.RX_TIMEOUT
bits : 6 - 6 (1 bit)
access : read-only

ERROR_RX_OVERFLOW : Source: SIE_STATUS.RX_OVERFLOW
bits : 7 - 7 (1 bit)
access : read-only

ERROR_BIT_STUFF : Source: SIE_STATUS.BIT_STUFF_ERROR
bits : 8 - 8 (1 bit)
access : read-only

ERROR_CRC : Source: SIE_STATUS.CRC_ERROR
bits : 9 - 9 (1 bit)
access : read-only

STALL : Source: SIE_STATUS.STALL_REC
bits : 10 - 10 (1 bit)
access : read-only

VBUS_DETECT : Source: SIE_STATUS.VBUS_DETECTED
bits : 11 - 11 (1 bit)
access : read-only

BUS_RESET : Source: SIE_STATUS.BUS_RESET
bits : 12 - 12 (1 bit)
access : read-only

DEV_CONN_DIS : Set when the device connection state changes. Cleared by writing to SIE_STATUS.CONNECTED
bits : 13 - 13 (1 bit)
access : read-only

DEV_SUSPEND : Set when the device suspend state changes. Cleared by writing to SIE_STATUS.SUSPENDED
bits : 14 - 14 (1 bit)
access : read-only

DEV_RESUME_FROM_HOST : Set when the device receives a resume from the host. Cleared by writing to SIE_STATUS.RESUME
bits : 15 - 15 (1 bit)
access : read-only

SETUP_REQ : Device. Source: SIE_STATUS.SETUP_REC
bits : 16 - 16 (1 bit)
access : read-only

DEV_SOF : Set every time the device receives a SOF (Start of Frame) packet. Cleared by reading SOF_RD
bits : 17 - 17 (1 bit)
access : read-only

ABORT_DONE : Raised when any bit in ABORT_DONE is set. Clear by clearing all bits in ABORT_DONE.
bits : 18 - 18 (1 bit)
access : read-only

EP_STALL_NAK : Raised when any bit in EP_STATUS_STALL_NAK is set. Clear by clearing all bits in EP_STATUS_STALL_NAK.
bits : 19 - 19 (1 bit)
access : read-only

RX_SHORT_PACKET : Source: SIE_STATUS.RX_SHORT_PACKET
bits : 20 - 20 (1 bit)
access : read-only

ENDPOINT_ERROR : Source: SIE_STATUS.ENDPOINT_ERROR
bits : 21 - 21 (1 bit)
access : read-only

DEV_SM_WATCHDOG_FIRED : Source: DEV_SM_WATCHDOG.FIRED
bits : 22 - 22 (1 bit)
access : read-only

EPX_STOPPED_ON_NAK : Source: NAK_POLL.EPX_STOPPED_ON_NAK
bits : 23 - 23 (1 bit)
access : read-only


INTE

Interrupt Enable
address_offset : 0x90 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

INTE INTE read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HOST_CONN_DIS HOST_RESUME HOST_SOF TRANS_COMPLETE BUFF_STATUS ERROR_DATA_SEQ ERROR_RX_TIMEOUT ERROR_RX_OVERFLOW ERROR_BIT_STUFF ERROR_CRC STALL VBUS_DETECT BUS_RESET DEV_CONN_DIS DEV_SUSPEND DEV_RESUME_FROM_HOST SETUP_REQ DEV_SOF ABORT_DONE EP_STALL_NAK RX_SHORT_PACKET ENDPOINT_ERROR DEV_SM_WATCHDOG_FIRED EPX_STOPPED_ON_NAK

HOST_CONN_DIS : Host: raised when a device is connected or disconnected (i.e. when SIE_STATUS.SPEED changes). Cleared by writing to SIE_STATUS.SPEED
bits : 0 - 0 (1 bit)
access : read-write

HOST_RESUME : Host: raised when a device wakes up the host. Cleared by writing to SIE_STATUS.RESUME
bits : 1 - 1 (1 bit)
access : read-write

HOST_SOF : Host: raised every time the host sends a SOF (Start of Frame). Cleared by reading SOF_RD
bits : 2 - 2 (1 bit)
access : read-write

TRANS_COMPLETE : Raised every time SIE_STATUS.TRANS_COMPLETE is set. Clear by writing to this bit.
bits : 3 - 3 (1 bit)
access : read-write

BUFF_STATUS : Raised when any bit in BUFF_STATUS is set. Clear by clearing all bits in BUFF_STATUS.
bits : 4 - 4 (1 bit)
access : read-write

ERROR_DATA_SEQ : Source: SIE_STATUS.DATA_SEQ_ERROR
bits : 5 - 5 (1 bit)
access : read-write

ERROR_RX_TIMEOUT : Source: SIE_STATUS.RX_TIMEOUT
bits : 6 - 6 (1 bit)
access : read-write

ERROR_RX_OVERFLOW : Source: SIE_STATUS.RX_OVERFLOW
bits : 7 - 7 (1 bit)
access : read-write

ERROR_BIT_STUFF : Source: SIE_STATUS.BIT_STUFF_ERROR
bits : 8 - 8 (1 bit)
access : read-write

ERROR_CRC : Source: SIE_STATUS.CRC_ERROR
bits : 9 - 9 (1 bit)
access : read-write

STALL : Source: SIE_STATUS.STALL_REC
bits : 10 - 10 (1 bit)
access : read-write

VBUS_DETECT : Source: SIE_STATUS.VBUS_DETECTED
bits : 11 - 11 (1 bit)
access : read-write

BUS_RESET : Source: SIE_STATUS.BUS_RESET
bits : 12 - 12 (1 bit)
access : read-write

DEV_CONN_DIS : Set when the device connection state changes. Cleared by writing to SIE_STATUS.CONNECTED
bits : 13 - 13 (1 bit)
access : read-write

DEV_SUSPEND : Set when the device suspend state changes. Cleared by writing to SIE_STATUS.SUSPENDED
bits : 14 - 14 (1 bit)
access : read-write

DEV_RESUME_FROM_HOST : Set when the device receives a resume from the host. Cleared by writing to SIE_STATUS.RESUME
bits : 15 - 15 (1 bit)
access : read-write

SETUP_REQ : Device. Source: SIE_STATUS.SETUP_REC
bits : 16 - 16 (1 bit)
access : read-write

DEV_SOF : Set every time the device receives a SOF (Start of Frame) packet. Cleared by reading SOF_RD
bits : 17 - 17 (1 bit)
access : read-write

ABORT_DONE : Raised when any bit in ABORT_DONE is set. Clear by clearing all bits in ABORT_DONE.
bits : 18 - 18 (1 bit)
access : read-write

EP_STALL_NAK : Raised when any bit in EP_STATUS_STALL_NAK is set. Clear by clearing all bits in EP_STATUS_STALL_NAK.
bits : 19 - 19 (1 bit)
access : read-write

RX_SHORT_PACKET : Source: SIE_STATUS.RX_SHORT_PACKET
bits : 20 - 20 (1 bit)
access : read-write

ENDPOINT_ERROR : Source: SIE_STATUS.ENDPOINT_ERROR
bits : 21 - 21 (1 bit)
access : read-write

DEV_SM_WATCHDOG_FIRED : Source: DEV_SM_WATCHDOG.FIRED
bits : 22 - 22 (1 bit)
access : read-write

EPX_STOPPED_ON_NAK : Source: NAK_POLL.EPX_STOPPED_ON_NAK
bits : 23 - 23 (1 bit)
access : read-write


INTF

Interrupt Force
address_offset : 0x94 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

INTF INTF read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HOST_CONN_DIS HOST_RESUME HOST_SOF TRANS_COMPLETE BUFF_STATUS ERROR_DATA_SEQ ERROR_RX_TIMEOUT ERROR_RX_OVERFLOW ERROR_BIT_STUFF ERROR_CRC STALL VBUS_DETECT BUS_RESET DEV_CONN_DIS DEV_SUSPEND DEV_RESUME_FROM_HOST SETUP_REQ DEV_SOF ABORT_DONE EP_STALL_NAK RX_SHORT_PACKET ENDPOINT_ERROR DEV_SM_WATCHDOG_FIRED EPX_STOPPED_ON_NAK

HOST_CONN_DIS : Host: raised when a device is connected or disconnected (i.e. when SIE_STATUS.SPEED changes). Cleared by writing to SIE_STATUS.SPEED
bits : 0 - 0 (1 bit)
access : read-write

HOST_RESUME : Host: raised when a device wakes up the host. Cleared by writing to SIE_STATUS.RESUME
bits : 1 - 1 (1 bit)
access : read-write

HOST_SOF : Host: raised every time the host sends a SOF (Start of Frame). Cleared by reading SOF_RD
bits : 2 - 2 (1 bit)
access : read-write

TRANS_COMPLETE : Raised every time SIE_STATUS.TRANS_COMPLETE is set. Clear by writing to this bit.
bits : 3 - 3 (1 bit)
access : read-write

BUFF_STATUS : Raised when any bit in BUFF_STATUS is set. Clear by clearing all bits in BUFF_STATUS.
bits : 4 - 4 (1 bit)
access : read-write

ERROR_DATA_SEQ : Source: SIE_STATUS.DATA_SEQ_ERROR
bits : 5 - 5 (1 bit)
access : read-write

ERROR_RX_TIMEOUT : Source: SIE_STATUS.RX_TIMEOUT
bits : 6 - 6 (1 bit)
access : read-write

ERROR_RX_OVERFLOW : Source: SIE_STATUS.RX_OVERFLOW
bits : 7 - 7 (1 bit)
access : read-write

ERROR_BIT_STUFF : Source: SIE_STATUS.BIT_STUFF_ERROR
bits : 8 - 8 (1 bit)
access : read-write

ERROR_CRC : Source: SIE_STATUS.CRC_ERROR
bits : 9 - 9 (1 bit)
access : read-write

STALL : Source: SIE_STATUS.STALL_REC
bits : 10 - 10 (1 bit)
access : read-write

VBUS_DETECT : Source: SIE_STATUS.VBUS_DETECTED
bits : 11 - 11 (1 bit)
access : read-write

BUS_RESET : Source: SIE_STATUS.BUS_RESET
bits : 12 - 12 (1 bit)
access : read-write

DEV_CONN_DIS : Set when the device connection state changes. Cleared by writing to SIE_STATUS.CONNECTED
bits : 13 - 13 (1 bit)
access : read-write

DEV_SUSPEND : Set when the device suspend state changes. Cleared by writing to SIE_STATUS.SUSPENDED
bits : 14 - 14 (1 bit)
access : read-write

DEV_RESUME_FROM_HOST : Set when the device receives a resume from the host. Cleared by writing to SIE_STATUS.RESUME
bits : 15 - 15 (1 bit)
access : read-write

SETUP_REQ : Device. Source: SIE_STATUS.SETUP_REC
bits : 16 - 16 (1 bit)
access : read-write

DEV_SOF : Set every time the device receives a SOF (Start of Frame) packet. Cleared by reading SOF_RD
bits : 17 - 17 (1 bit)
access : read-write

ABORT_DONE : Raised when any bit in ABORT_DONE is set. Clear by clearing all bits in ABORT_DONE.
bits : 18 - 18 (1 bit)
access : read-write

EP_STALL_NAK : Raised when any bit in EP_STATUS_STALL_NAK is set. Clear by clearing all bits in EP_STATUS_STALL_NAK.
bits : 19 - 19 (1 bit)
access : read-write

RX_SHORT_PACKET : Source: SIE_STATUS.RX_SHORT_PACKET
bits : 20 - 20 (1 bit)
access : read-write

ENDPOINT_ERROR : Source: SIE_STATUS.ENDPOINT_ERROR
bits : 21 - 21 (1 bit)
access : read-write

DEV_SM_WATCHDOG_FIRED : Source: DEV_SM_WATCHDOG.FIRED
bits : 22 - 22 (1 bit)
access : read-write

EPX_STOPPED_ON_NAK : Source: NAK_POLL.EPX_STOPPED_ON_NAK
bits : 23 - 23 (1 bit)
access : read-write


INTS

Interrupt status after masking & forcing
address_offset : 0x98 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

INTS INTS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HOST_CONN_DIS HOST_RESUME HOST_SOF TRANS_COMPLETE BUFF_STATUS ERROR_DATA_SEQ ERROR_RX_TIMEOUT ERROR_RX_OVERFLOW ERROR_BIT_STUFF ERROR_CRC STALL VBUS_DETECT BUS_RESET DEV_CONN_DIS DEV_SUSPEND DEV_RESUME_FROM_HOST SETUP_REQ DEV_SOF ABORT_DONE EP_STALL_NAK RX_SHORT_PACKET ENDPOINT_ERROR DEV_SM_WATCHDOG_FIRED EPX_STOPPED_ON_NAK

HOST_CONN_DIS : Host: raised when a device is connected or disconnected (i.e. when SIE_STATUS.SPEED changes). Cleared by writing to SIE_STATUS.SPEED
bits : 0 - 0 (1 bit)
access : read-only

HOST_RESUME : Host: raised when a device wakes up the host. Cleared by writing to SIE_STATUS.RESUME
bits : 1 - 1 (1 bit)
access : read-only

HOST_SOF : Host: raised every time the host sends a SOF (Start of Frame). Cleared by reading SOF_RD
bits : 2 - 2 (1 bit)
access : read-only

TRANS_COMPLETE : Raised every time SIE_STATUS.TRANS_COMPLETE is set. Clear by writing to this bit.
bits : 3 - 3 (1 bit)
access : read-only

BUFF_STATUS : Raised when any bit in BUFF_STATUS is set. Clear by clearing all bits in BUFF_STATUS.
bits : 4 - 4 (1 bit)
access : read-only

ERROR_DATA_SEQ : Source: SIE_STATUS.DATA_SEQ_ERROR
bits : 5 - 5 (1 bit)
access : read-only

ERROR_RX_TIMEOUT : Source: SIE_STATUS.RX_TIMEOUT
bits : 6 - 6 (1 bit)
access : read-only

ERROR_RX_OVERFLOW : Source: SIE_STATUS.RX_OVERFLOW
bits : 7 - 7 (1 bit)
access : read-only

ERROR_BIT_STUFF : Source: SIE_STATUS.BIT_STUFF_ERROR
bits : 8 - 8 (1 bit)
access : read-only

ERROR_CRC : Source: SIE_STATUS.CRC_ERROR
bits : 9 - 9 (1 bit)
access : read-only

STALL : Source: SIE_STATUS.STALL_REC
bits : 10 - 10 (1 bit)
access : read-only

VBUS_DETECT : Source: SIE_STATUS.VBUS_DETECTED
bits : 11 - 11 (1 bit)
access : read-only

BUS_RESET : Source: SIE_STATUS.BUS_RESET
bits : 12 - 12 (1 bit)
access : read-only

DEV_CONN_DIS : Set when the device connection state changes. Cleared by writing to SIE_STATUS.CONNECTED
bits : 13 - 13 (1 bit)
access : read-only

DEV_SUSPEND : Set when the device suspend state changes. Cleared by writing to SIE_STATUS.SUSPENDED
bits : 14 - 14 (1 bit)
access : read-only

DEV_RESUME_FROM_HOST : Set when the device receives a resume from the host. Cleared by writing to SIE_STATUS.RESUME
bits : 15 - 15 (1 bit)
access : read-only

SETUP_REQ : Device. Source: SIE_STATUS.SETUP_REC
bits : 16 - 16 (1 bit)
access : read-only

DEV_SOF : Set every time the device receives a SOF (Start of Frame) packet. Cleared by reading SOF_RD
bits : 17 - 17 (1 bit)
access : read-only

ABORT_DONE : Raised when any bit in ABORT_DONE is set. Clear by clearing all bits in ABORT_DONE.
bits : 18 - 18 (1 bit)
access : read-only

EP_STALL_NAK : Raised when any bit in EP_STATUS_STALL_NAK is set. Clear by clearing all bits in EP_STATUS_STALL_NAK.
bits : 19 - 19 (1 bit)
access : read-only

RX_SHORT_PACKET : Source: SIE_STATUS.RX_SHORT_PACKET
bits : 20 - 20 (1 bit)
access : read-only

ENDPOINT_ERROR : Source: SIE_STATUS.ENDPOINT_ERROR
bits : 21 - 21 (1 bit)
access : read-only

DEV_SM_WATCHDOG_FIRED : Source: DEV_SM_WATCHDOG.FIRED
bits : 22 - 22 (1 bit)
access : read-only

EPX_STOPPED_ON_NAK : Source: NAK_POLL.EPX_STOPPED_ON_NAK
bits : 23 - 23 (1 bit)
access : read-only


ADDR_ENDP3

Interrupt endpoint 3. Only valid for HOST mode.
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ADDR_ENDP3 ADDR_ENDP3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADDRESS ENDPOINT INTEP_DIR INTEP_PREAMBLE

ADDRESS : Device address
bits : 0 - 6 (7 bit)
access : read-write

ENDPOINT : Endpoint number of the interrupt endpoint
bits : 16 - 19 (4 bit)
access : read-write

INTEP_DIR : Direction of the interrupt endpoint. In=0, Out=1
bits : 25 - 25 (1 bit)
access : read-write

INTEP_PREAMBLE : Interrupt EP requires preamble (is a low speed device on a full speed hub)
bits : 26 - 26 (1 bit)
access : read-write



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