GLITCH_DETECTOR

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x18 byte (0x0)
mem_usage : registers
protection :

Registers

ARM

TRIG_STATUS

TRIG_FORCE

DISARM

SENSITIVITY

LOCK


ARM

Forcibly arm the glitch detectors, if they are not already armed by OTP. When armed, any individual detector trigger will cause a restart of the switched core power domain's power-on reset state machine. Glitch detector triggers are recorded accumulatively in TRIG_STATUS. If the system is reset by a glitch detector trigger, this is recorded in POWMAN_CHIP_RESET. This register is Secure read/write only.
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ARM ARM read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ARM

ARM :
bits : 0 - 15 (16 bit)
access : read-write

Enumeration:

23469 : no

Do not force the glitch detectors to be armed

0 : yes

Force the glitch detectors to be armed. (Any value other than ARM_NO counts as YES)

End of enumeration elements list.


TRIG_STATUS

Set when a detector output triggers. Write-1-clear. (May immediately return high if the detector remains in a failed state. Detectors can only be cleared by a full reset of the switched core power domain.) This register is Secure read/write only.
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TRIG_STATUS TRIG_STATUS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DET0 DET1 DET2 DET3

DET0 :
bits : 0 - 0 (1 bit)
access : read-write

DET1 :
bits : 1 - 1 (1 bit)
access : read-write

DET2 :
bits : 2 - 2 (1 bit)
access : read-write

DET3 :
bits : 3 - 3 (1 bit)
access : read-write


TRIG_FORCE

Simulate the firing of one or more detectors. Writing ones to this register will set the matching bits in STATUS_TRIG. If the glitch detectors are currently armed, writing ones will also immediately reset the switched core power domain, and set the reset reason latches in POWMAN_CHIP_RESET to indicate a glitch detector resets. This register is Secure read/write only.
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TRIG_FORCE TRIG_FORCE read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TRIG_FORCE

TRIG_FORCE :
bits : 0 - 3 (4 bit)
access : write-only


DISARM


address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DISARM DISARM read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DISARM

DISARM : Forcibly disarm the glitch detectors, if they are armed by OTP. Ignored if ARM is YES. This register is Secure read/write only.
bits : 0 - 15 (16 bit)
access : read-write

Enumeration:

0 : no

Do not disarm the glitch detectors. (Any value other than DISARM_YES counts as NO)

56495 : yes

Disarm the glitch detectors

End of enumeration elements list.


SENSITIVITY

Adjust the sensitivity of glitch detectors to values other than their OTP-provided defaults. This register is Secure read/write only.
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SENSITIVITY SENSITIVITY read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DET0 DET1 DET2 DET3 DET0_INV DET1_INV DET2_INV DET3_INV DEFAULT

DET0 : Set sensitivity for detector 0. Higher values are more sensitive.
bits : 0 - 1 (2 bit)
access : read-write

DET1 : Set sensitivity for detector 1. Higher values are more sensitive.
bits : 2 - 3 (2 bit)
access : read-write

DET2 : Set sensitivity for detector 2. Higher values are more sensitive.
bits : 4 - 5 (2 bit)
access : read-write

DET3 : Set sensitivity for detector 3. Higher values are more sensitive.
bits : 6 - 7 (2 bit)
access : read-write

DET0_INV : Must be the inverse of DET0, else the default value is used.
bits : 8 - 9 (2 bit)
access : read-write

DET1_INV : Must be the inverse of DET1, else the default value is used.
bits : 10 - 11 (2 bit)
access : read-write

DET2_INV : Must be the inverse of DET2, else the default value is used.
bits : 12 - 13 (2 bit)
access : read-write

DET3_INV : Must be the inverse of DET3, else the default value is used.
bits : 14 - 15 (2 bit)
access : read-write

DEFAULT :
bits : 24 - 31 (8 bit)
access : read-write

Enumeration:

0 : yes

Use the default sensitivity configured in OTP for all detectors. (Any value other than DEFAULT_NO counts as YES)

222 : no

Do not use the default sensitivity configured in OTP. Instead use the value from this register.

End of enumeration elements list.


LOCK


address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

LOCK LOCK read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LOCK

LOCK : Write any nonzero value to disable writes to ARM, DISARM, SENSITIVITY and LOCK. This register is Secure read/write only.
bits : 0 - 7 (8 bit)
access : read-write



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