address_offset : 0x0 Bytes (0x0)
size : 0x1EF0 byte (0x0)
mem_usage : registers
protection :
Bits 15:0 of public device ID. (ECC)
The CHIPID0..3 rows contain a 64-bit random identifier for this chip, which can be read from the USB bootloader PICOBOOT interface or from the get_sys_info ROM API.
The number of random bits makes the occurrence of twins exceedingly unlikely: for example, a fleet of a hundred million devices has a 99.97% probability of no twinned IDs. This is estimated to be lower than the occurrence of process errors in the assignment of sequential random IDs, and for practical purposes CHIPID may be treated as unique.
address_offset : 0x0 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHIPID0 :
bits : 0 - 15 (16 bit)
access : read-only
Bits 79:64 of private per-device random number (ECC)
address_offset : 0x10 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RANDID4 :
bits : 0 - 15 (16 bit)
access : read-only
Bits 15:0 of SHA-256 hash of boot key 0 (ECC)
address_offset : 0x100 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BOOTKEY0_0 :
bits : 0 - 15 (16 bit)
access : read-only
Bits 31:16 of SHA-256 hash of boot key 0 (ECC)
address_offset : 0x102 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BOOTKEY0_1 :
bits : 0 - 15 (16 bit)
access : read-only
Bits 47:32 of SHA-256 hash of boot key 0 (ECC)
address_offset : 0x104 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BOOTKEY0_2 :
bits : 0 - 15 (16 bit)
access : read-only
Bits 63:48 of SHA-256 hash of boot key 0 (ECC)
address_offset : 0x106 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BOOTKEY0_3 :
bits : 0 - 15 (16 bit)
access : read-only
Bits 79:64 of SHA-256 hash of boot key 0 (ECC)
address_offset : 0x108 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BOOTKEY0_4 :
bits : 0 - 15 (16 bit)
access : read-only
Bits 95:80 of SHA-256 hash of boot key 0 (ECC)
address_offset : 0x10A Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BOOTKEY0_5 :
bits : 0 - 15 (16 bit)
access : read-only
Bits 111:96 of SHA-256 hash of boot key 0 (ECC)
address_offset : 0x10C Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BOOTKEY0_6 :
bits : 0 - 15 (16 bit)
access : read-only
Bits 127:112 of SHA-256 hash of boot key 0 (ECC)
address_offset : 0x10E Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BOOTKEY0_7 :
bits : 0 - 15 (16 bit)
access : read-only
Bits 143:128 of SHA-256 hash of boot key 0 (ECC)
address_offset : 0x110 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BOOTKEY0_8 :
bits : 0 - 15 (16 bit)
access : read-only
Bits 159:144 of SHA-256 hash of boot key 0 (ECC)
address_offset : 0x112 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BOOTKEY0_9 :
bits : 0 - 15 (16 bit)
access : read-only
Bits 175:160 of SHA-256 hash of boot key 0 (ECC)
address_offset : 0x114 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BOOTKEY0_10 :
bits : 0 - 15 (16 bit)
access : read-only
Bits 191:176 of SHA-256 hash of boot key 0 (ECC)
address_offset : 0x116 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BOOTKEY0_11 :
bits : 0 - 15 (16 bit)
access : read-only
Bits 207:192 of SHA-256 hash of boot key 0 (ECC)
address_offset : 0x118 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BOOTKEY0_12 :
bits : 0 - 15 (16 bit)
access : read-only
Bits 223:208 of SHA-256 hash of boot key 0 (ECC)
address_offset : 0x11A Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BOOTKEY0_13 :
bits : 0 - 15 (16 bit)
access : read-only
Bits 239:224 of SHA-256 hash of boot key 0 (ECC)
address_offset : 0x11C Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BOOTKEY0_14 :
bits : 0 - 15 (16 bit)
access : read-only
Bits 255:240 of SHA-256 hash of boot key 0 (ECC)
address_offset : 0x11E Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BOOTKEY0_15 :
bits : 0 - 15 (16 bit)
access : read-only
Bits 95:80 of private per-device random number (ECC)
address_offset : 0x12 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RANDID5 :
bits : 0 - 15 (16 bit)
access : read-only
Bits 15:0 of SHA-256 hash of boot key 1 (ECC)
address_offset : 0x120 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BOOTKEY1_0 :
bits : 0 - 15 (16 bit)
access : read-only
Bits 31:16 of SHA-256 hash of boot key 1 (ECC)
address_offset : 0x122 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BOOTKEY1_1 :
bits : 0 - 15 (16 bit)
access : read-only
Bits 47:32 of SHA-256 hash of boot key 1 (ECC)
address_offset : 0x124 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BOOTKEY1_2 :
bits : 0 - 15 (16 bit)
access : read-only
Bits 63:48 of SHA-256 hash of boot key 1 (ECC)
address_offset : 0x126 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BOOTKEY1_3 :
bits : 0 - 15 (16 bit)
access : read-only
Bits 79:64 of SHA-256 hash of boot key 1 (ECC)
address_offset : 0x128 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BOOTKEY1_4 :
bits : 0 - 15 (16 bit)
access : read-only
Bits 95:80 of SHA-256 hash of boot key 1 (ECC)
address_offset : 0x12A Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BOOTKEY1_5 :
bits : 0 - 15 (16 bit)
access : read-only
Bits 111:96 of SHA-256 hash of boot key 1 (ECC)
address_offset : 0x12C Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BOOTKEY1_6 :
bits : 0 - 15 (16 bit)
access : read-only
Bits 127:112 of SHA-256 hash of boot key 1 (ECC)
address_offset : 0x12E Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BOOTKEY1_7 :
bits : 0 - 15 (16 bit)
access : read-only
Bits 143:128 of SHA-256 hash of boot key 1 (ECC)
address_offset : 0x130 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BOOTKEY1_8 :
bits : 0 - 15 (16 bit)
access : read-only
Bits 159:144 of SHA-256 hash of boot key 1 (ECC)
address_offset : 0x132 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BOOTKEY1_9 :
bits : 0 - 15 (16 bit)
access : read-only
Bits 175:160 of SHA-256 hash of boot key 1 (ECC)
address_offset : 0x134 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BOOTKEY1_10 :
bits : 0 - 15 (16 bit)
access : read-only
Bits 191:176 of SHA-256 hash of boot key 1 (ECC)
address_offset : 0x136 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BOOTKEY1_11 :
bits : 0 - 15 (16 bit)
access : read-only
Bits 207:192 of SHA-256 hash of boot key 1 (ECC)
address_offset : 0x138 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BOOTKEY1_12 :
bits : 0 - 15 (16 bit)
access : read-only
Bits 223:208 of SHA-256 hash of boot key 1 (ECC)
address_offset : 0x13A Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BOOTKEY1_13 :
bits : 0 - 15 (16 bit)
access : read-only
Bits 239:224 of SHA-256 hash of boot key 1 (ECC)
address_offset : 0x13C Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BOOTKEY1_14 :
bits : 0 - 15 (16 bit)
access : read-only
Bits 255:240 of SHA-256 hash of boot key 1 (ECC)
address_offset : 0x13E Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BOOTKEY1_15 :
bits : 0 - 15 (16 bit)
access : read-only
Bits 111:96 of private per-device random number (ECC)
address_offset : 0x14 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RANDID6 :
bits : 0 - 15 (16 bit)
access : read-only
Bits 15:0 of SHA-256 hash of boot key 2 (ECC)
address_offset : 0x140 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BOOTKEY2_0 :
bits : 0 - 15 (16 bit)
access : read-only
Bits 31:16 of SHA-256 hash of boot key 2 (ECC)
address_offset : 0x142 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BOOTKEY2_1 :
bits : 0 - 15 (16 bit)
access : read-only
Bits 47:32 of SHA-256 hash of boot key 2 (ECC)
address_offset : 0x144 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BOOTKEY2_2 :
bits : 0 - 15 (16 bit)
access : read-only
Bits 63:48 of SHA-256 hash of boot key 2 (ECC)
address_offset : 0x146 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BOOTKEY2_3 :
bits : 0 - 15 (16 bit)
access : read-only
Bits 79:64 of SHA-256 hash of boot key 2 (ECC)
address_offset : 0x148 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BOOTKEY2_4 :
bits : 0 - 15 (16 bit)
access : read-only
Bits 95:80 of SHA-256 hash of boot key 2 (ECC)
address_offset : 0x14A Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BOOTKEY2_5 :
bits : 0 - 15 (16 bit)
access : read-only
Bits 111:96 of SHA-256 hash of boot key 2 (ECC)
address_offset : 0x14C Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BOOTKEY2_6 :
bits : 0 - 15 (16 bit)
access : read-only
Bits 127:112 of SHA-256 hash of boot key 2 (ECC)
address_offset : 0x14E Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BOOTKEY2_7 :
bits : 0 - 15 (16 bit)
access : read-only
Bits 143:128 of SHA-256 hash of boot key 2 (ECC)
address_offset : 0x150 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BOOTKEY2_8 :
bits : 0 - 15 (16 bit)
access : read-only
Bits 159:144 of SHA-256 hash of boot key 2 (ECC)
address_offset : 0x152 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BOOTKEY2_9 :
bits : 0 - 15 (16 bit)
access : read-only
Bits 175:160 of SHA-256 hash of boot key 2 (ECC)
address_offset : 0x154 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BOOTKEY2_10 :
bits : 0 - 15 (16 bit)
access : read-only
Bits 191:176 of SHA-256 hash of boot key 2 (ECC)
address_offset : 0x156 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BOOTKEY2_11 :
bits : 0 - 15 (16 bit)
access : read-only
Bits 207:192 of SHA-256 hash of boot key 2 (ECC)
address_offset : 0x158 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BOOTKEY2_12 :
bits : 0 - 15 (16 bit)
access : read-only
Bits 223:208 of SHA-256 hash of boot key 2 (ECC)
address_offset : 0x15A Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BOOTKEY2_13 :
bits : 0 - 15 (16 bit)
access : read-only
Bits 239:224 of SHA-256 hash of boot key 2 (ECC)
address_offset : 0x15C Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BOOTKEY2_14 :
bits : 0 - 15 (16 bit)
access : read-only
Bits 255:240 of SHA-256 hash of boot key 2 (ECC)
address_offset : 0x15E Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BOOTKEY2_15 :
bits : 0 - 15 (16 bit)
access : read-only
Bits 127:112 of private per-device random number (ECC)
address_offset : 0x16 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RANDID7 :
bits : 0 - 15 (16 bit)
access : read-only
Bits 15:0 of SHA-256 hash of boot key 3 (ECC)
address_offset : 0x160 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BOOTKEY3_0 :
bits : 0 - 15 (16 bit)
access : read-only
Bits 31:16 of SHA-256 hash of boot key 3 (ECC)
address_offset : 0x162 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BOOTKEY3_1 :
bits : 0 - 15 (16 bit)
access : read-only
Bits 47:32 of SHA-256 hash of boot key 3 (ECC)
address_offset : 0x164 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BOOTKEY3_2 :
bits : 0 - 15 (16 bit)
access : read-only
Bits 63:48 of SHA-256 hash of boot key 3 (ECC)
address_offset : 0x166 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BOOTKEY3_3 :
bits : 0 - 15 (16 bit)
access : read-only
Bits 79:64 of SHA-256 hash of boot key 3 (ECC)
address_offset : 0x168 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BOOTKEY3_4 :
bits : 0 - 15 (16 bit)
access : read-only
Bits 95:80 of SHA-256 hash of boot key 3 (ECC)
address_offset : 0x16A Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BOOTKEY3_5 :
bits : 0 - 15 (16 bit)
access : read-only
Bits 111:96 of SHA-256 hash of boot key 3 (ECC)
address_offset : 0x16C Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BOOTKEY3_6 :
bits : 0 - 15 (16 bit)
access : read-only
Bits 127:112 of SHA-256 hash of boot key 3 (ECC)
address_offset : 0x16E Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BOOTKEY3_7 :
bits : 0 - 15 (16 bit)
access : read-only
Bits 143:128 of SHA-256 hash of boot key 3 (ECC)
address_offset : 0x170 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BOOTKEY3_8 :
bits : 0 - 15 (16 bit)
access : read-only
Bits 159:144 of SHA-256 hash of boot key 3 (ECC)
address_offset : 0x172 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BOOTKEY3_9 :
bits : 0 - 15 (16 bit)
access : read-only
Bits 175:160 of SHA-256 hash of boot key 3 (ECC)
address_offset : 0x174 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BOOTKEY3_10 :
bits : 0 - 15 (16 bit)
access : read-only
Bits 191:176 of SHA-256 hash of boot key 3 (ECC)
address_offset : 0x176 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BOOTKEY3_11 :
bits : 0 - 15 (16 bit)
access : read-only
Bits 207:192 of SHA-256 hash of boot key 3 (ECC)
address_offset : 0x178 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BOOTKEY3_12 :
bits : 0 - 15 (16 bit)
access : read-only
Bits 223:208 of SHA-256 hash of boot key 3 (ECC)
address_offset : 0x17A Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BOOTKEY3_13 :
bits : 0 - 15 (16 bit)
access : read-only
Bits 239:224 of SHA-256 hash of boot key 3 (ECC)
address_offset : 0x17C Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BOOTKEY3_14 :
bits : 0 - 15 (16 bit)
access : read-only
Bits 255:240 of SHA-256 hash of boot key 3 (ECC)
address_offset : 0x17E Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BOOTKEY3_15 :
bits : 0 - 15 (16 bit)
access : read-only
Bits 15:0 of OTP access key 1 (ECC)
address_offset : 0x1E90 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
KEY1_0 :
bits : 0 - 15 (16 bit)
access : read-only
Bits 31:16 of OTP access key 1 (ECC)
address_offset : 0x1E92 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
KEY1_1 :
bits : 0 - 15 (16 bit)
access : read-only
Bits 47:32 of OTP access key 1 (ECC)
address_offset : 0x1E94 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
KEY1_2 :
bits : 0 - 15 (16 bit)
access : read-only
Bits 63:48 of OTP access key 1 (ECC)
address_offset : 0x1E96 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
KEY1_3 :
bits : 0 - 15 (16 bit)
access : read-only
Bits 79:64 of OTP access key 1 (ECC)
address_offset : 0x1E98 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
KEY1_4 :
bits : 0 - 15 (16 bit)
access : read-only
Bits 95:80 of OTP access key 1 (ECC)
address_offset : 0x1E9A Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
KEY1_5 :
bits : 0 - 15 (16 bit)
access : read-only
Bits 111:96 of OTP access key 1 (ECC)
address_offset : 0x1E9C Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
KEY1_6 :
bits : 0 - 15 (16 bit)
access : read-only
Bits 127:112 of OTP access key 1 (ECC)
address_offset : 0x1E9E Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
KEY1_7 :
bits : 0 - 15 (16 bit)
access : read-only
Bits 15:0 of OTP access key 2 (ECC)
address_offset : 0x1EA0 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
KEY2_0 :
bits : 0 - 15 (16 bit)
access : read-only
Bits 31:16 of OTP access key 2 (ECC)
address_offset : 0x1EA2 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
KEY2_1 :
bits : 0 - 15 (16 bit)
access : read-only
Bits 47:32 of OTP access key 2 (ECC)
address_offset : 0x1EA4 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
KEY2_2 :
bits : 0 - 15 (16 bit)
access : read-only
Bits 63:48 of OTP access key 2 (ECC)
address_offset : 0x1EA6 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
KEY2_3 :
bits : 0 - 15 (16 bit)
access : read-only
Bits 79:64 of OTP access key 2 (ECC)
address_offset : 0x1EA8 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
KEY2_4 :
bits : 0 - 15 (16 bit)
access : read-only
Bits 95:80 of OTP access key 2 (ECC)
address_offset : 0x1EAA Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
KEY2_5 :
bits : 0 - 15 (16 bit)
access : read-only
Bits 111:96 of OTP access key 2 (ECC)
address_offset : 0x1EAC Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
KEY2_6 :
bits : 0 - 15 (16 bit)
access : read-only
Bits 127:112 of OTP access key 2 (ECC)
address_offset : 0x1EAE Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
KEY2_7 :
bits : 0 - 15 (16 bit)
access : read-only
Bits 15:0 of OTP access key 3 (ECC)
address_offset : 0x1EB0 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
KEY3_0 :
bits : 0 - 15 (16 bit)
access : read-only
Bits 31:16 of OTP access key 3 (ECC)
address_offset : 0x1EB2 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
KEY3_1 :
bits : 0 - 15 (16 bit)
access : read-only
Bits 47:32 of OTP access key 3 (ECC)
address_offset : 0x1EB4 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
KEY3_2 :
bits : 0 - 15 (16 bit)
access : read-only
Bits 63:48 of OTP access key 3 (ECC)
address_offset : 0x1EB6 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
KEY3_3 :
bits : 0 - 15 (16 bit)
access : read-only
Bits 79:64 of OTP access key 3 (ECC)
address_offset : 0x1EB8 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
KEY3_4 :
bits : 0 - 15 (16 bit)
access : read-only
Bits 95:80 of OTP access key 3 (ECC)
address_offset : 0x1EBA Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
KEY3_5 :
bits : 0 - 15 (16 bit)
access : read-only
Bits 111:96 of OTP access key 3 (ECC)
address_offset : 0x1EBC Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
KEY3_6 :
bits : 0 - 15 (16 bit)
access : read-only
Bits 127:112 of OTP access key 3 (ECC)
address_offset : 0x1EBE Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
KEY3_7 :
bits : 0 - 15 (16 bit)
access : read-only
Bits 15:0 of OTP access key 4 (ECC)
address_offset : 0x1EC0 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
KEY4_0 :
bits : 0 - 15 (16 bit)
access : read-only
Bits 31:16 of OTP access key 4 (ECC)
address_offset : 0x1EC2 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
KEY4_1 :
bits : 0 - 15 (16 bit)
access : read-only
Bits 47:32 of OTP access key 4 (ECC)
address_offset : 0x1EC4 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
KEY4_2 :
bits : 0 - 15 (16 bit)
access : read-only
Bits 63:48 of OTP access key 4 (ECC)
address_offset : 0x1EC6 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
KEY4_3 :
bits : 0 - 15 (16 bit)
access : read-only
Bits 79:64 of OTP access key 4 (ECC)
address_offset : 0x1EC8 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
KEY4_4 :
bits : 0 - 15 (16 bit)
access : read-only
Bits 95:80 of OTP access key 4 (ECC)
address_offset : 0x1ECA Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
KEY4_5 :
bits : 0 - 15 (16 bit)
access : read-only
Bits 111:96 of OTP access key 4 (ECC)
address_offset : 0x1ECC Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
KEY4_6 :
bits : 0 - 15 (16 bit)
access : read-only
Bits 127:112 of OTP access key 4 (ECC)
address_offset : 0x1ECE Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
KEY4_7 :
bits : 0 - 15 (16 bit)
access : read-only
Bits 15:0 of OTP access key 5 (ECC)
address_offset : 0x1ED0 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
KEY5_0 :
bits : 0 - 15 (16 bit)
access : read-only
Bits 31:16 of OTP access key 5 (ECC)
address_offset : 0x1ED2 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
KEY5_1 :
bits : 0 - 15 (16 bit)
access : read-only
Bits 47:32 of OTP access key 5 (ECC)
address_offset : 0x1ED4 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
KEY5_2 :
bits : 0 - 15 (16 bit)
access : read-only
Bits 63:48 of OTP access key 5 (ECC)
address_offset : 0x1ED6 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
KEY5_3 :
bits : 0 - 15 (16 bit)
access : read-only
Bits 79:64 of OTP access key 5 (ECC)
address_offset : 0x1ED8 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
KEY5_4 :
bits : 0 - 15 (16 bit)
access : read-only
Bits 95:80 of OTP access key 5 (ECC)
address_offset : 0x1EDA Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
KEY5_5 :
bits : 0 - 15 (16 bit)
access : read-only
Bits 111:96 of OTP access key 5 (ECC)
address_offset : 0x1EDC Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
KEY5_6 :
bits : 0 - 15 (16 bit)
access : read-only
Bits 127:112 of OTP access key 5 (ECC)
address_offset : 0x1EDE Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
KEY5_7 :
bits : 0 - 15 (16 bit)
access : read-only
Bits 15:0 of OTP access key 6 (ECC)
address_offset : 0x1EE0 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
KEY6_0 :
bits : 0 - 15 (16 bit)
access : read-only
Bits 31:16 of OTP access key 6 (ECC)
address_offset : 0x1EE2 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
KEY6_1 :
bits : 0 - 15 (16 bit)
access : read-only
Bits 47:32 of OTP access key 6 (ECC)
address_offset : 0x1EE4 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
KEY6_2 :
bits : 0 - 15 (16 bit)
access : read-only
Bits 63:48 of OTP access key 6 (ECC)
address_offset : 0x1EE6 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
KEY6_3 :
bits : 0 - 15 (16 bit)
access : read-only
Bits 79:64 of OTP access key 6 (ECC)
address_offset : 0x1EE8 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
KEY6_4 :
bits : 0 - 15 (16 bit)
access : read-only
Bits 95:80 of OTP access key 6 (ECC)
address_offset : 0x1EEA Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
KEY6_5 :
bits : 0 - 15 (16 bit)
access : read-only
Bits 111:96 of OTP access key 6 (ECC)
address_offset : 0x1EEC Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
KEY6_6 :
bits : 0 - 15 (16 bit)
access : read-only
Bits 127:112 of OTP access key 6 (ECC)
address_offset : 0x1EEE Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
KEY6_7 :
bits : 0 - 15 (16 bit)
access : read-only
Bits 31:16 of public device ID (ECC)
address_offset : 0x2 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHIPID1 :
bits : 0 - 15 (16 bit)
access : read-only
Ring oscillator frequency in kHz, measured during manufacturing (ECC)
This is measured at 1.1 V, at room temperature, with the ROSC configuration registers in their reset state.
address_offset : 0x20 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ROSC_CALIB :
bits : 0 - 15 (16 bit)
access : read-only
Low-power oscillator frequency in Hz, measured during manufacturing (ECC)
This is measured at 1.1V, at room temperature, with the LPOSC trim register in its reset state.
address_offset : 0x22 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LPOSC_CALIB :
bits : 0 - 15 (16 bit)
access : read-only
The number of main user GPIOs (bank 0). Should read 48 in the QFN80 package, and 30 in the QFN60 package. (ECC)
address_offset : 0x30 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
NUM_GPIOS :
bits : 0 - 7 (8 bit)
access : read-only
Bits 47:32 of public device ID (ECC)
address_offset : 0x4 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHIPID2 :
bits : 0 - 15 (16 bit)
access : read-only
Bits 63:48 of public device ID (ECC)
address_offset : 0x6 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHIPID3 :
bits : 0 - 15 (16 bit)
access : read-only
Lower 16 bits of CRC32 of OTP addresses 0x00 through 0x6b (polynomial 0x4c11db7, input reflected, output reflected, seed all-ones, final XOR all-ones) (ECC)
address_offset : 0x6C Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INFO_CRC0 :
bits : 0 - 15 (16 bit)
access : read-only
Upper 16 bits of CRC32 of OTP addresses 0x00 through 0x6b (ECC)
address_offset : 0x6E Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INFO_CRC1 :
bits : 0 - 15 (16 bit)
access : read-only
Bits 15:0 of private per-device random number (ECC)
The RANDID0..7 rows form a 128-bit random number generated during device test.
This ID is not exposed through the USB PICOBOOT GET_INFO command or the ROM `get_sys_info()` API. However note that the USB PICOBOOT OTP access point can read the entirety of page 0, so this value is not meaningfully private unless the USB PICOBOOT interface is disabled via the DISABLE_BOOTSEL_USB_PICOBOOT_IFC flag in BOOT_FLAGS0.
address_offset : 0x8 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RANDID0 :
bits : 0 - 15 (16 bit)
access : read-only
Bits 31:16 of private per-device random number (ECC)
address_offset : 0xA Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RANDID1 :
bits : 0 - 15 (16 bit)
access : read-only
Stores information about external flash device(s). (ECC)
Assumed to be valid if BOOT_FLAGS0_FLASH_DEVINFO_ENABLE is set.
address_offset : 0xA8 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CS1_GPIO : Indicate a GPIO number to be used for the secondary flash chip select (CS1), which selects the external QSPI device mapped at system addresses 0x11000000 through 0x11ffffff. There is no such configuration for CS0, as the primary chip select has a dedicated pin.
On RP2350 the permissible GPIO numbers are 0, 8, 19 and 47.
Ignored if CS1_size is zero. If CS1_SIZE is nonzero, the bootrom will automatically configure this GPIO as a second chip select upon entering the flash boot path, or entering any other path that may use the QSPI flash interface, such as BOOTSEL mode (nsboot).
bits : 0 - 5 (6 bit)
access : read-only
D8H_ERASE_SUPPORTED : If true, all attached devices are assumed to support (or ignore, in the case of PSRAM) a block erase command with a command prefix of D8h, an erase size of 64 kiB, and a 24-bit address. Almost all 25-series flash devices support this command.
If set, the bootrom will use the D8h erase command where it is able, to accelerate bulk erase operations. This makes flash programming faster.
When BOOT_FLAGS0_FLASH_DEVINFO_ENABLE is not set, this field defaults to false.
bits : 7 - 7 (1 bit)
access : read-only
CS0_SIZE : The size of the flash/PSRAM device on chip select 0 (addressable at 0x10000000 through 0x10ffffff).
A value of zero is decoded as a size of zero (no device). Nonzero values are decoded as 4kiB << CS0_SIZE. For example, four megabytes is encoded with a CS0_SIZE value of 10, and 16 megabytes is encoded with a CS0_SIZE value of 12.
When BOOT_FLAGS0_FLASH_DEVINFO_ENABLE is not set, a default of 12 (16 MiB) is used.
bits : 8 - 11 (4 bit)
access : read-only
Enumeration:
0 : NONE
1 : 8K
2 : 16K
3 : 32K
4 : 64k
5 : 128K
6 : 256K
7 : 512K
8 : 1M
9 : 2M
10 : 4M
11 : 8M
12 : 16M
End of enumeration elements list.
CS1_SIZE : The size of the flash/PSRAM device on chip select 1 (addressable at 0x11000000 through 0x11ffffff).
A value of zero is decoded as a size of zero (no device). Nonzero values are decoded as 4kiB << CS1_SIZE. For example, four megabytes is encoded with a CS1_SIZE value of 10, and 16 megabytes is encoded with a CS1_SIZE value of 12.
When BOOT_FLAGS0_FLASH_DEVINFO_ENABLE is not set, a default of zero is used.
bits : 12 - 15 (4 bit)
access : read-only
Enumeration:
0 : NONE
1 : 8K
2 : 16K
3 : 32K
4 : 64k
5 : 128K
6 : 256K
7 : 512K
8 : 1M
9 : 2M
10 : 4M
11 : 8M
12 : 16M
End of enumeration elements list.
Gap between partition table slot 0 and slot 1 at the start of flash (the default size is 4096 bytes) (ECC) Enabled by the OVERRIDE_FLASH_PARTITION_SLOT_SIZE bit in BOOT_FLAGS, the size is 4096 * (value + 1)
address_offset : 0xAA Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FLASH_PARTITION_SLOT_SIZE :
bits : 0 - 15 (16 bit)
access : read-only
Pin configuration for LED status, used by USB bootloader. (ECC)
Must be valid if BOOT_FLAGS0_ENABLE_BOOTSEL_LED is set.
address_offset : 0xAC Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PIN : GPIO index to use for bootloader activity LED.
bits : 0 - 5 (6 bit)
access : read-only
ACTIVELOW : LED is active-low. (Default: active-high.)
bits : 8 - 8 (1 bit)
access : read-only
Optional PLL configuration for BOOTSEL mode. (ECC)
This should be configured to produce an exact 48 MHz based on the crystal oscillator frequency. User mode software may also use this value to calculate the expected crystal frequency based on an assumed 48 MHz PLL output.
If no configuration is given, the crystal is assumed to be 12 MHz.
The PLL frequency can be calculated as:
PLL out = (XOSC frequency / (REFDIV+1)) x FBDIV / (POSTDIV1 x POSTDIV2)
Conversely the crystal frequency can be calculated as:
XOSC frequency = 48 MHz x (REFDIV+1) x (POSTDIV1 x POSTDIV2) / FBDIV
(Note the +1 on REFDIV is because the value stored in this OTP location is the actual divisor value minus one.)
Used if and only if ENABLE_BOOTSEL_NON_DEFAULT_PLL_XOSC_CFG is set in BOOT_FLAGS0. That bit should be set only after this row and BOOTSEL_XOSC_CFG are both correctly programmed.
address_offset : 0xAE Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FBDIV : PLL feedback divisor, in the range 16..320 inclusive.
bits : 0 - 8 (9 bit)
access : read-only
POSTDIV1 : PLL post-divide 1 divisor, in the range 1..7 inclusive.
bits : 9 - 11 (3 bit)
access : read-only
POSTDIV2 : PLL post-divide 2 divisor, in the range 1..7 inclusive.
bits : 12 - 14 (3 bit)
access : read-only
REFDIV : PLL reference divisor, minus one.
Programming a value of 0 means a reference divisor of 1. Programming a value of 1 means a reference divisor of 2 (for exceptionally fast XIN inputs)
bits : 15 - 15 (1 bit)
access : read-only
Non-default crystal oscillator configuration for the USB bootloader. (ECC)
These values may also be used by user code configuring the crystal oscillator.
Used if and only if ENABLE_BOOTSEL_NON_DEFAULT_PLL_XOSC_CFG is set in BOOT_FLAGS0. That bit should be set only after this row and BOOTSEL_PLL_CFG are both correctly programmed.
address_offset : 0xB0 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
STARTUP : Value of the XOSC_STARTUP register
bits : 0 - 13 (14 bit)
access : read-only
RANGE : Value of the XOSC_CTRL_FREQ_RANGE register.
bits : 14 - 15 (2 bit)
access : read-only
Enumeration:
0 : 1_15MHZ
1 : 10_30MHZ
2 : 25_60MHZ
3 : 40_100MHZ
End of enumeration elements list.
Row index of the USB_WHITE_LABEL structure within OTP (ECC)
The table has 16 rows, each of which are also ECC and marked valid by the corresponding valid bit in USB_BOOT_FLAGS (ECC).
The entries are either _VALUEs where the 16 bit value is used as is, or _STRDEFs which acts as a pointers to a string value.
The value stored in a _STRDEF is two separate bytes: The low seven bits of the first (LSB) byte indicates the number of characters in the string, and the top bit of the first (LSB) byte if set to indicate that each character in the string is two bytes (Unicode) versus one byte if unset. The second (MSB) byte represents the location of the string data, and is encoded as the number of rows from this USB_WHITE_LABEL_ADDR i.e. the row of the start of the string is USB_WHITE_LABEL_ADDR value + msb_byte.
In each case, the corresponding valid bit enables replacing the default value for the corresponding item provided by the boot rom.
Note that Unicode _STRDEFs are only supported for USB_DEVICE_PRODUCT_STRDEF, USB_DEVICE_SERIAL_NUMBER_STRDEF and USB_DEVICE_MANUFACTURER_STRDEF. Unicode values will be ignored if specified for other fields, and non-unicode values for these three items will be converted to Unicode characters by setting the upper 8 bits to zero.
Note that if the USB_WHITE_LABEL structure or the corresponding strings are not readable by BOOTSEL mode based on OTP permissions, or if alignment requirements are not met, then the corresponding default values are used.
The index values indicate where each field is located (row USB_WHITE_LABEL_ADDR value + index):
address_offset : 0xB8 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
USB_WHITE_LABEL_ADDR :
bits : 0 - 15 (16 bit)
access : read-only
Enumeration:
0 : INDEX_USB_DEVICE_VID_VALUE
1 : INDEX_USB_DEVICE_PID_VALUE
2 : INDEX_USB_DEVICE_BCD_DEVICE_VALUE
3 : INDEX_USB_DEVICE_LANG_ID_VALUE
4 : INDEX_USB_DEVICE_MANUFACTURER_STRDEF
5 : INDEX_USB_DEVICE_PRODUCT_STRDEF
6 : INDEX_USB_DEVICE_SERIAL_NUMBER_STRDEF
7 : INDEX_USB_CONFIG_ATTRIBUTES_MAX_POWER_VALUES
8 : INDEX_VOLUME_LABEL_STRDEF
9 : INDEX_SCSI_INQUIRY_VENDOR_STRDEF
10 : INDEX_SCSI_INQUIRY_PRODUCT_STRDEF
11 : INDEX_SCSI_INQUIRY_VERSION_STRDEF
12 : INDEX_INDEX_HTM_REDIRECT_URL_STRDEF
13 : INDEX_INDEX_HTM_REDIRECT_NAME_STRDEF
14 : INDEX_INFO_UF2_TXT_MODEL_STRDEF
15 : INDEX_INFO_UF2_TXT_BOARD_ID_STRDEF
End of enumeration elements list.
OTP start row for the OTP boot image. (ECC)
If OTP boot is enabled, the bootrom will load from this location into SRAM and then directly enter the loaded image. Note that the image must be signed if SECURE_BOOT_ENABLE is set. The image itself is assumed to be ECC-protected.
This must be an even number. Equivalently, the OTP boot image must start at a word-aligned location in the ECC read data address window.
address_offset : 0xBC Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OTPBOOT_SRC :
bits : 0 - 15 (16 bit)
access : read-only
Length in rows of the OTP boot image. (ECC)
OTPBOOT_LEN must be even. The total image size must be a multiple of 4 bytes (32 bits).
address_offset : 0xBE Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OTPBOOT_LEN :
bits : 0 - 15 (16 bit)
access : read-only
Bits 47:32 of private per-device random number (ECC)
address_offset : 0xC Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RANDID2 :
bits : 0 - 15 (16 bit)
access : read-only
Bits 15:0 of the OTP boot image load destination (and entry point). (ECC)
This must be a location in main SRAM (main SRAM is addresses 0x20000000 through 0x20082000) and must be word-aligned.
address_offset : 0xC0 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OTPBOOT_DST0 :
bits : 0 - 15 (16 bit)
access : read-only
Bits 31:16 of the OTP boot image load destination (and entry point). (ECC)
This must be a location in main SRAM (main SRAM is addresses 0x20000000 through 0x20082000) and must be word-aligned.
address_offset : 0xC2 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OTPBOOT_DST1 :
bits : 0 - 15 (16 bit)
access : read-only
Bits 63:48 of private per-device random number (ECC)
address_offset : 0xE Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RANDID3 :
bits : 0 - 15 (16 bit)
access : read-only
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