CR

AHB1RSTR

AHB2RSTR

AHB3RSTR

APB1RSTR

APB2RSTR

AHB1ENR

AHB2ENR

AHB3ENR

PLLCFGR

APB1ENR

APB2ENR

AHB1LPENR

AHB2LPENR

AHB3LPENR

APB1LPENR

APB2LPENR

BDCR

CSR

CFGR

SSCGR

PLLI2SCFGR

PLLSAICFGR

DCKCFGR1

DCKCFGR2

CIR

HSION : Internal high-speed clock enable
bits : 0 - 0 (1 bit)
access : read-write

HSIRDY : Internal high-speed clock ready flag
bits : 1 - 1 (1 bit)
access : read-only

HSITRIM : Internal high-speed clock trimming
bits : 3 - 7 (5 bit)
access : read-write

HSICAL : Internal high-speed clock calibration
bits : 8 - 15 (8 bit)
access : read-only

HSEON : HSE clock enable
bits : 16 - 16 (1 bit)
access : read-write

HSERDY : HSE clock ready flag
bits : 17 - 17 (1 bit)
access : read-only

HSEBYP : HSE clock bypass
bits : 18 - 18 (1 bit)
access : read-write

CSSON : Clock security system enable
bits : 19 - 19 (1 bit)
access : read-write

PLLON : Main PLL (PLL) enable
bits : 24 - 24 (1 bit)
access : read-write

PLLRDY : Main PLL (PLL) clock ready flag
bits : 25 - 25 (1 bit)
access : read-only

PLLI2SON : PLLI2S enable
bits : 26 - 26 (1 bit)
access : read-write

PLLI2SRDY : PLLI2S clock ready flag
bits : 27 - 27 (1 bit)
access : read-only

PLLSAION : PLLSAI enable
bits : 28 - 28 (1 bit)
access : read-write

PLLSAIRDY : PLLSAI clock ready flag
bits : 29 - 29 (1 bit)
access : read-write

GPIOARST : IO port A reset
bits : 0 - 0 (1 bit)

GPIOBRST : IO port B reset
bits : 1 - 1 (1 bit)

GPIOCRST : IO port C reset
bits : 2 - 2 (1 bit)

GPIODRST : IO port D reset
bits : 3 - 3 (1 bit)

GPIOERST : IO port E reset
bits : 4 - 4 (1 bit)

GPIOFRST : IO port F reset
bits : 5 - 5 (1 bit)

GPIOGRST : IO port G reset
bits : 6 - 6 (1 bit)

GPIOHRST : IO port H reset
bits : 7 - 7 (1 bit)

GPIOIRST : IO port I reset
bits : 8 - 8 (1 bit)

CRCRST : CRC reset
bits : 12 - 12 (1 bit)

DMA1RST : DMA2 reset
bits : 21 - 21 (1 bit)

DMA2RST : DMA2 reset
bits : 22 - 22 (1 bit)

OTGHSRST : USB OTG HS module reset
bits : 29 - 29 (1 bit)

AESRST : AES module reset
bits : 4 - 4 (1 bit)

RNGRST : Random number generator module reset
bits : 6 - 6 (1 bit)

OTGFSRST : USB OTG FS module reset
bits : 7 - 7 (1 bit)

FMCRST : Flexible memory controller module reset
bits : 0 - 0 (1 bit)

QSPIRST : Quad SPI memory controller reset
bits : 1 - 1 (1 bit)

TIM2RST : TIM2 reset
bits : 0 - 0 (1 bit)

TIM3RST : TIM3 reset
bits : 1 - 1 (1 bit)

TIM4RST : TIM4 reset
bits : 2 - 2 (1 bit)

TIM5RST : TIM5 reset
bits : 3 - 3 (1 bit)

TIM6RST : TIM6 reset
bits : 4 - 4 (1 bit)

TIM7RST : TIM7 reset
bits : 5 - 5 (1 bit)

TIM12RST : TIM12 reset
bits : 6 - 6 (1 bit)

TIM13RST : TIM13 reset
bits : 7 - 7 (1 bit)

TIM14RST : TIM14 reset
bits : 8 - 8 (1 bit)

LPTIM1RST : Low power timer 1 reset
bits : 9 - 9 (1 bit)

WWDGRST : Window watchdog reset
bits : 11 - 11 (1 bit)

SPI2RST : SPI 2 reset
bits : 14 - 14 (1 bit)

SPI3RST : SPI 3 reset
bits : 15 - 15 (1 bit)

UART2RST : USART 2 reset
bits : 17 - 17 (1 bit)

UART3RST : USART 3 reset
bits : 18 - 18 (1 bit)

UART4RST : USART 4 reset
bits : 19 - 19 (1 bit)

UART5RST : USART 5 reset
bits : 20 - 20 (1 bit)

I2C1RST : I2C 1 reset
bits : 21 - 21 (1 bit)

I2C2RST : I2C 2 reset
bits : 22 - 22 (1 bit)

I2C3RST : I2C3 reset
bits : 23 - 23 (1 bit)

CAN1RST : CAN1 reset
bits : 25 - 25 (1 bit)

CECRST : HDMI-CEC reset
bits : 27 - 27 (1 bit)

PWRRST : Power interface reset
bits : 28 - 28 (1 bit)

DACRST : DAC reset
bits : 29 - 29 (1 bit)

UART7RST : UART7 reset
bits : 30 - 30 (1 bit)

UART8RST : UART8 reset
bits : 31 - 31 (1 bit)

TIM1RST : TIM1 reset
bits : 0 - 0 (1 bit)

TIM8RST : TIM8 reset
bits : 1 - 1 (1 bit)

USART1RST : USART1 reset
bits : 4 - 4 (1 bit)

USART6RST : USART6 reset
bits : 5 - 5 (1 bit)

SDMMC2RST : SDMMC2 reset
bits : 7 - 7 (1 bit)

ADCRST : ADC interface reset (common to all ADCs)
bits : 8 - 8 (1 bit)

SDMMC1RST : SDMMC1 reset
bits : 11 - 11 (1 bit)

SPI1RST : SPI 1 reset
bits : 12 - 12 (1 bit)

SPI4RST : SPI4 reset
bits : 13 - 13 (1 bit)

SYSCFGRST : System configuration controller reset
bits : 14 - 14 (1 bit)

TIM9RST : TIM9 reset
bits : 16 - 16 (1 bit)

TIM10RST : TIM10 reset
bits : 17 - 17 (1 bit)

TIM11RST : TIM11 reset
bits : 18 - 18 (1 bit)

SPI5RST : SPI5 reset
bits : 20 - 20 (1 bit)

SAI1RST : SAI1 reset
bits : 22 - 22 (1 bit)

SAI2RST : SAI2 reset
bits : 23 - 23 (1 bit)

USBPHYCRST : USB OTG HS PHY controller reset
bits : 31 - 31 (1 bit)

GPIOAEN : IO port A clock enable
bits : 0 - 0 (1 bit)

GPIOBEN : IO port B clock enable
bits : 1 - 1 (1 bit)

GPIOCEN : IO port C clock enable
bits : 2 - 2 (1 bit)

GPIODEN : IO port D clock enable
bits : 3 - 3 (1 bit)

GPIOEEN : IO port E clock enable
bits : 4 - 4 (1 bit)

GPIOFEN : IO port F clock enable
bits : 5 - 5 (1 bit)

GPIOGEN : IO port G clock enable
bits : 6 - 6 (1 bit)

GPIOHEN : IO port H clock enable
bits : 7 - 7 (1 bit)

GPIOIEN : IO port I clock enable
bits : 8 - 8 (1 bit)

CRCEN : CRC clock enable
bits : 12 - 12 (1 bit)

BKPSRAMEN : Backup SRAM interface clock enable
bits : 18 - 18 (1 bit)

DTCMRAMEN : CCM data RAM clock enable
bits : 20 - 20 (1 bit)

DMA1EN : DMA1 clock enable
bits : 21 - 21 (1 bit)

DMA2EN : DMA2 clock enable
bits : 22 - 22 (1 bit)

OTGHSEN : USB OTG HS clock enable
bits : 29 - 29 (1 bit)

OTGHSULPIEN : USB OTG HSULPI clock enable
bits : 30 - 30 (1 bit)

AESEN : AES module clock enable
bits : 4 - 4 (1 bit)

RNGEN : Random number generator clock enable
bits : 6 - 6 (1 bit)

OTGFSEN : USB OTG FS clock enable
bits : 7 - 7 (1 bit)

FMCEN : Flexible memory controller module clock enable
bits : 0 - 0 (1 bit)

QSPIEN : Quad SPI memory controller clock enable
bits : 1 - 1 (1 bit)

PLLM0 : Division factor for the main PLL (PLL) and audio PLL (PLLI2S) input clock
bits : 0 - 0 (1 bit)

PLLM1 : Division factor for the main PLL (PLL) and audio PLL (PLLI2S) input clock
bits : 1 - 1 (1 bit)

PLLM2 : Division factor for the main PLL (PLL) and audio PLL (PLLI2S) input clock
bits : 2 - 2 (1 bit)

PLLM3 : Division factor for the main PLL (PLL) and audio PLL (PLLI2S) input clock
bits : 3 - 3 (1 bit)

PLLM4 : Division factor for the main PLL (PLL) and audio PLL (PLLI2S) input clock
bits : 4 - 4 (1 bit)

PLLM5 : Division factor for the main PLL (PLL) and audio PLL (PLLI2S) input clock
bits : 5 - 5 (1 bit)

PLLN0 : Main PLL (PLL) multiplication factor for VCO
bits : 6 - 6 (1 bit)

PLLN1 : Main PLL (PLL) multiplication factor for VCO
bits : 7 - 7 (1 bit)

PLLN2 : Main PLL (PLL) multiplication factor for VCO
bits : 8 - 8 (1 bit)

PLLN3 : Main PLL (PLL) multiplication factor for VCO
bits : 9 - 9 (1 bit)

PLLN4 : Main PLL (PLL) multiplication factor for VCO
bits : 10 - 10 (1 bit)

PLLN5 : Main PLL (PLL) multiplication factor for VCO
bits : 11 - 11 (1 bit)

PLLN6 : Main PLL (PLL) multiplication factor for VCO
bits : 12 - 12 (1 bit)

PLLN7 : Main PLL (PLL) multiplication factor for VCO
bits : 13 - 13 (1 bit)

PLLN8 : Main PLL (PLL) multiplication factor for VCO
bits : 14 - 14 (1 bit)

PLLP0 : Main PLL (PLL) division factor for main system clock
bits : 16 - 16 (1 bit)

PLLP1 : Main PLL (PLL) division factor for main system clock
bits : 17 - 17 (1 bit)

PLLSRC : Main PLL(PLL) and audio PLL (PLLI2S) entry clock source
bits : 22 - 22 (1 bit)

PLLQ0 : Main PLL (PLL) division factor for USB OTG FS, SDIO and random number generator clocks
bits : 24 - 24 (1 bit)

PLLQ1 : Main PLL (PLL) division factor for USB OTG FS, SDIO and random number generator clocks
bits : 25 - 25 (1 bit)

PLLQ2 : Main PLL (PLL) division factor for USB OTG FS, SDIO and random number generator clocks
bits : 26 - 26 (1 bit)

PLLQ3 : Main PLL (PLL) division factor for USB OTG FS, SDIO and random number generator clocks
bits : 27 - 27 (1 bit)

TIM2EN : TIM2 clock enable
bits : 0 - 0 (1 bit)

TIM3EN : TIM3 clock enable
bits : 1 - 1 (1 bit)

TIM4EN : TIM4 clock enable
bits : 2 - 2 (1 bit)

TIM5EN : TIM5 clock enable
bits : 3 - 3 (1 bit)

TIM6EN : TIM6 clock enable
bits : 4 - 4 (1 bit)

TIM7EN : TIM7 clock enable
bits : 5 - 5 (1 bit)

TIM12EN : TIM12 clock enable
bits : 6 - 6 (1 bit)

TIM13EN : TIM13 clock enable
bits : 7 - 7 (1 bit)

TIM14EN : TIM14 clock enable
bits : 8 - 8 (1 bit)

LPTIM1EN : Low power timer 1 clock enable
bits : 9 - 9 (1 bit)

RTCAPBEN : RTCAPB clock enable
bits : 10 - 10 (1 bit)

WWDGEN : Window watchdog clock enable
bits : 11 - 11 (1 bit)

SPI2EN : SPI2 clock enable
bits : 14 - 14 (1 bit)

SPI3EN : SPI3 clock enable
bits : 15 - 15 (1 bit)

USART2EN : USART 2 clock enable
bits : 17 - 17 (1 bit)

USART3EN : USART3 clock enable
bits : 18 - 18 (1 bit)

UART4EN : UART4 clock enable
bits : 19 - 19 (1 bit)

UART5EN : UART5 clock enable
bits : 20 - 20 (1 bit)

I2C1EN : I2C1 clock enable
bits : 21 - 21 (1 bit)

I2C2EN : I2C2 clock enable
bits : 22 - 22 (1 bit)

I2C3EN : I2C3 clock enable
bits : 23 - 23 (1 bit)

CAN1EN : CAN 1 clock enable
bits : 25 - 25 (1 bit)

PWREN : Power interface clock enable
bits : 28 - 28 (1 bit)

DACEN : DAC interface clock enable
bits : 29 - 29 (1 bit)

UART7EN : UART7 clock enable
bits : 30 - 30 (1 bit)

UART8EN : UART8 clock enable
bits : 31 - 31 (1 bit)

TIM1EN : TIM1 clock enable
bits : 0 - 0 (1 bit)

TIM8EN : TIM8 clock enable
bits : 1 - 1 (1 bit)

USART1EN : USART1 clock enable
bits : 4 - 4 (1 bit)

USART6EN : USART6 clock enable
bits : 5 - 5 (1 bit)

SDMMC2EN : SDMMC2 clock enable
bits : 7 - 7 (1 bit)

ADC1EN : ADC1 clock enable
bits : 8 - 8 (1 bit)

ADC2EN : ADC2 clock enable
bits : 9 - 9 (1 bit)

ADC3EN : ADC3 clock enable
bits : 10 - 10 (1 bit)

SDMMC1EN : SDMMC1 clock enable
bits : 11 - 11 (1 bit)

SPI1EN : SPI1 clock enable
bits : 12 - 12 (1 bit)

SPI4EN : SPI4 clock enable
bits : 13 - 13 (1 bit)

SYSCFGEN : System configuration controller clock enable
bits : 14 - 14 (1 bit)

TIM9EN : TIM9 clock enable
bits : 16 - 16 (1 bit)

TIM10EN : TIM10 clock enable
bits : 17 - 17 (1 bit)

TIM11EN : TIM11 clock enable
bits : 18 - 18 (1 bit)

SPI5EN : SPI5 clock enable
bits : 20 - 20 (1 bit)

SAI1EN : SAI1 clock enable
bits : 22 - 22 (1 bit)

SAI2EN : SAI2 clock enable
bits : 23 - 23 (1 bit)

USBPHYCEN : USB OTG HS PHY controller clock enable
bits : 31 - 31 (1 bit)

GPIOALPEN : IO port A clock enable during sleep mode
bits : 0 - 0 (1 bit)

GPIOBLPEN : IO port B clock enable during Sleep mode
bits : 1 - 1 (1 bit)

GPIOCLPEN : IO port C clock enable during Sleep mode
bits : 2 - 2 (1 bit)

GPIODLPEN : IO port D clock enable during Sleep mode
bits : 3 - 3 (1 bit)

GPIOELPEN : IO port E clock enable during Sleep mode
bits : 4 - 4 (1 bit)

GPIOFLPEN : IO port F clock enable during Sleep mode
bits : 5 - 5 (1 bit)

GPIOGLPEN : IO port G clock enable during Sleep mode
bits : 6 - 6 (1 bit)

GPIOHLPEN : IO port H clock enable during Sleep mode
bits : 7 - 7 (1 bit)

GPIOILPEN : IO port I clock enable during Sleep mode
bits : 8 - 8 (1 bit)

GPIOJLPEN : IO port J clock enable during Sleep mode
bits : 9 - 9 (1 bit)

GPIOKLPEN : IO port K clock enable during Sleep mode
bits : 10 - 10 (1 bit)

CRCLPEN : CRC clock enable during Sleep mode
bits : 12 - 12 (1 bit)

AXILPEN : AXI to AHB bridge clock enable during Sleep mode
bits : 13 - 13 (1 bit)

FLITFLPEN : Flash interface clock enable during Sleep mode
bits : 15 - 15 (1 bit)

SRAM1LPEN : SRAM 1interface clock enable during Sleep mode
bits : 16 - 16 (1 bit)

SRAM2LPEN : SRAM 2 interface clock enable during Sleep mode
bits : 17 - 17 (1 bit)

BKPSRAMLPEN : Backup SRAM interface clock enable during Sleep mode
bits : 18 - 18 (1 bit)

SRAM3LPEN : SRAM 3 interface clock enable during Sleep mode
bits : 19 - 19 (1 bit)

DTCMLPEN : DTCM RAM interface clock enable during Sleep mode
bits : 20 - 20 (1 bit)

DMA1LPEN : DMA1 clock enable during Sleep mode
bits : 21 - 21 (1 bit)

DMA2LPEN : DMA2 clock enable during Sleep mode
bits : 22 - 22 (1 bit)

DMA2DLPEN : DMA2D clock enable during Sleep mode
bits : 23 - 23 (1 bit)

ETHMACLPEN : Ethernet MAC clock enable during Sleep mode
bits : 25 - 25 (1 bit)

ETHMACTXLPEN : Ethernet transmission clock enable during Sleep mode
bits : 26 - 26 (1 bit)

ETHMACRXLPEN : Ethernet reception clock enable during Sleep mode
bits : 27 - 27 (1 bit)

ETHMACPTPLPEN : Ethernet PTP clock enable during Sleep mode
bits : 28 - 28 (1 bit)

OTGHSLPEN : USB OTG HS clock enable during Sleep mode
bits : 29 - 29 (1 bit)

OTGHSULPILPEN : USB OTG HS ULPI clock enable during Sleep mode
bits : 30 - 30 (1 bit)

AESLPEN : AES module clock enable during Sleep mode
bits : 4 - 4 (1 bit)

RNGLPEN : Random number generator clock enable during Sleep mode
bits : 6 - 6 (1 bit)

OTGFSLPEN : USB OTG FS clock enable during Sleep mode
bits : 7 - 7 (1 bit)

FMCLPEN : Flexible memory controller module clock enable during Sleep mode
bits : 0 - 0 (1 bit)

QSPILPEN : Quand SPI memory controller clock enable during Sleep mode
bits : 1 - 1 (1 bit)

TIM2LPEN : TIM2 clock enable during Sleep mode
bits : 0 - 0 (1 bit)

TIM3LPEN : TIM3 clock enable during Sleep mode
bits : 1 - 1 (1 bit)

TIM4LPEN : TIM4 clock enable during Sleep mode
bits : 2 - 2 (1 bit)

TIM5LPEN : TIM5 clock enable during Sleep mode
bits : 3 - 3 (1 bit)

TIM6LPEN : TIM6 clock enable during Sleep mode
bits : 4 - 4 (1 bit)

TIM7LPEN : TIM7 clock enable during Sleep mode
bits : 5 - 5 (1 bit)

TIM12LPEN : TIM12 clock enable during Sleep mode
bits : 6 - 6 (1 bit)

TIM13LPEN : TIM13 clock enable during Sleep mode
bits : 7 - 7 (1 bit)

TIM14LPEN : TIM14 clock enable during Sleep mode
bits : 8 - 8 (1 bit)

LPTIM1LPEN : low power timer 1 clock enable during Sleep mode
bits : 9 - 9 (1 bit)

WWDGLPEN : Window watchdog clock enable during Sleep mode
bits : 11 - 11 (1 bit)

SPI2LPEN : SPI2 clock enable during Sleep mode
bits : 14 - 14 (1 bit)

SPI3LPEN : SPI3 clock enable during Sleep mode
bits : 15 - 15 (1 bit)

USART2LPEN : USART2 clock enable during Sleep mode
bits : 17 - 17 (1 bit)

USART3LPEN : USART3 clock enable during Sleep mode
bits : 18 - 18 (1 bit)

UART4LPEN : UART4 clock enable during Sleep mode
bits : 19 - 19 (1 bit)

UART5LPEN : UART5 clock enable during Sleep mode
bits : 20 - 20 (1 bit)

I2C1LPEN : I2C1 clock enable during Sleep mode
bits : 21 - 21 (1 bit)

I2C2LPEN : I2C2 clock enable during Sleep mode
bits : 22 - 22 (1 bit)

I2C3LPEN : I2C3 clock enable during Sleep mode
bits : 23 - 23 (1 bit)

CAN1LPEN : CAN 1 clock enable during Sleep mode
bits : 25 - 25 (1 bit)

CAN2LPEN : CAN 2 clock enable during Sleep mode
bits : 26 - 26 (1 bit)

PWRLPEN : Power interface clock enable during Sleep mode
bits : 28 - 28 (1 bit)

DACLPEN : DAC interface clock enable during Sleep mode
bits : 29 - 29 (1 bit)

UART7LPEN : UART7 clock enable during Sleep mode
bits : 30 - 30 (1 bit)

UART8LPEN : UART8 clock enable during Sleep mode
bits : 31 - 31 (1 bit)

TIM1LPEN : TIM1 clock enable during Sleep mode
bits : 0 - 0 (1 bit)

TIM8LPEN : TIM8 clock enable during Sleep mode
bits : 1 - 1 (1 bit)

USART1LPEN : USART1 clock enable during Sleep mode
bits : 4 - 4 (1 bit)

USART6LPEN : USART6 clock enable during Sleep mode
bits : 5 - 5 (1 bit)

SDMMC2LPEN : SDMMC2 clock enable during Sleep mode
bits : 7 - 7 (1 bit)

ADC1LPEN : ADC1 clock enable during Sleep mode
bits : 8 - 8 (1 bit)

ADC2LPEN : ADC2 clock enable during Sleep mode
bits : 9 - 9 (1 bit)

ADC3LPEN : ADC 3 clock enable during Sleep mode
bits : 10 - 10 (1 bit)

SDMMC1LPEN : SDMMC1 clock enable during Sleep mode
bits : 11 - 11 (1 bit)

SPI1LPEN : SPI 1 clock enable during Sleep mode
bits : 12 - 12 (1 bit)

SPI4LPEN : SPI 4 clock enable during Sleep mode
bits : 13 - 13 (1 bit)

SYSCFGLPEN : System configuration controller clock enable during Sleep mode
bits : 14 - 14 (1 bit)

TIM9LPEN : TIM9 clock enable during sleep mode
bits : 16 - 16 (1 bit)

TIM10LPEN : TIM10 clock enable during Sleep mode
bits : 17 - 17 (1 bit)

TIM11LPEN : TIM11 clock enable during Sleep mode
bits : 18 - 18 (1 bit)

SPI5LPEN : SPI 5 clock enable during Sleep mode
bits : 20 - 20 (1 bit)

SAI1LPEN : SAI1 clock enable during sleep mode
bits : 22 - 22 (1 bit)

SAI2LPEN : SAI2 clock enable during sleep mode
bits : 23 - 23 (1 bit)

LSEON : External low-speed oscillator enable
bits : 0 - 0 (1 bit)
access : read-write

LSERDY : External low-speed oscillator ready
bits : 1 - 1 (1 bit)
access : read-only

LSEBYP : External low-speed oscillator bypass
bits : 2 - 2 (1 bit)
access : read-write

RTCSEL0 : RTC clock source selection
bits : 8 - 8 (1 bit)
access : read-write

RTCSEL1 : RTC clock source selection
bits : 9 - 9 (1 bit)
access : read-write

RTCEN : RTC clock enable
bits : 15 - 15 (1 bit)
access : read-write

BDRST : Backup domain software reset
bits : 16 - 16 (1 bit)
access : read-write

LSION : Internal low-speed oscillator enable
bits : 0 - 0 (1 bit)
access : read-write

LSIRDY : Internal low-speed oscillator ready
bits : 1 - 1 (1 bit)
access : read-only

RMVF : Remove reset flag
bits : 24 - 24 (1 bit)
access : read-write

BORRSTF : BOR reset flag
bits : 25 - 25 (1 bit)
access : read-write

PADRSTF : PIN reset flag
bits : 26 - 26 (1 bit)
access : read-write

PORRSTF : POR/PDR reset flag
bits : 27 - 27 (1 bit)
access : read-write

SFTRSTF : Software reset flag
bits : 28 - 28 (1 bit)
access : read-write

WDGRSTF : Independent watchdog reset flag
bits : 29 - 29 (1 bit)
access : read-write

WWDGRSTF : Window watchdog reset flag
bits : 30 - 30 (1 bit)
access : read-write

LPWRRSTF : Low-power reset flag
bits : 31 - 31 (1 bit)
access : read-write

SW0 : System clock switch
bits : 0 - 0 (1 bit)
access : read-write

SW1 : System clock switch
bits : 1 - 1 (1 bit)
access : read-write

SWS0 : System clock switch status
bits : 2 - 2 (1 bit)
access : read-only

SWS1 : System clock switch status
bits : 3 - 3 (1 bit)
access : read-only

HPRE : AHB prescaler
bits : 4 - 7 (4 bit)
access : read-write

PPRE1 : APB Low speed prescaler (APB1)
bits : 10 - 12 (3 bit)
access : read-write

PPRE2 : APB high-speed prescaler (APB2)
bits : 13 - 15 (3 bit)
access : read-write

RTCPRE : HSE division factor for RTC clock
bits : 16 - 20 (5 bit)
access : read-write

MCO1 : Microcontroller clock output 1
bits : 21 - 22 (2 bit)
access : read-write

I2SSRC : I2S clock selection
bits : 23 - 23 (1 bit)
access : read-write

MCO1PRE : MCO1 prescaler
bits : 24 - 26 (3 bit)
access : read-write

MCO2PRE : MCO2 prescaler
bits : 27 - 29 (3 bit)
access : read-write

MCO2 : Microcontroller clock output 2
bits : 30 - 31 (2 bit)
access : read-write

MODPER : Modulation period
bits : 0 - 12 (13 bit)

INCSTEP : Incrementation step
bits : 13 - 27 (15 bit)

SPREADSEL : Spread Select
bits : 30 - 30 (1 bit)

SSCGEN : Spread spectrum modulation enable
bits : 31 - 31 (1 bit)

PLLI2SN : PLLI2S multiplication factor for VCO
bits : 6 - 14 (9 bit)

PLLI2SQ : PLLI2S division factor for SAI1 clock
bits : 24 - 27 (4 bit)

PLLI2SR : PLLI2S division factor for I2S clocks
bits : 28 - 30 (3 bit)

PLLSAIN : PLLSAI division factor for VCO
bits : 6 - 14 (9 bit)

PLLSAIP : PLLSAI division factor for 48MHz clock
bits : 16 - 17 (2 bit)

PLLSAIQ : PLLSAI division factor for SAI clock
bits : 24 - 27 (4 bit)

PLLI2SDIV : PLLI2S division factor for SAI1 clock
bits : 0 - 4 (5 bit)

PLLSAIDIVQ : PLLSAI division factor for SAI1 clock
bits : 8 - 12 (5 bit)

SAI1SEL : SAI1 clock source selection
bits : 20 - 21 (2 bit)

SAI2SEL : SAI2 clock source selection
bits : 22 - 23 (2 bit)

TIMPRE : Timers clocks prescalers selection
bits : 24 - 24 (1 bit)

UART1SEL : USART 1 clock source selection
bits : 0 - 1 (2 bit)

UART2SEL : USART 2 clock source selection
bits : 2 - 3 (2 bit)

UART3SEL : USART 3 clock source selection
bits : 4 - 5 (2 bit)

UART4SEL : UART 4 clock source selection
bits : 6 - 7 (2 bit)

UART5SEL : UART 5 clock source selection
bits : 8 - 9 (2 bit)

UART6SEL : USART 6 clock source selection
bits : 10 - 11 (2 bit)

UART7SEL : UART 7 clock source selection
bits : 12 - 13 (2 bit)

UART8SEL : UART 8 clock source selection
bits : 14 - 15 (2 bit)

I2C1SEL : I2C1 clock source selection
bits : 16 - 17 (2 bit)

I2C2SEL : I2C2 clock source selection
bits : 18 - 19 (2 bit)

I2C3SEL : I2C3 clock source selection
bits : 20 - 21 (2 bit)

LPTIM1SEL : Low power timer 1 clock source selection
bits : 24 - 25 (2 bit)

CK48MSEL : 48MHz clock source selection
bits : 27 - 27 (1 bit)

SDMMC1SEL : SDMMC1 clock source selection
bits : 28 - 28 (1 bit)

SDMMC2SEL : SDMMC2 clock source selection
bits : 29 - 29 (1 bit)

LSIRDYF : LSI ready interrupt flag
bits : 0 - 0 (1 bit)
access : read-only

LSERDYF : LSE ready interrupt flag
bits : 1 - 1 (1 bit)
access : read-only

HSIRDYF : HSI ready interrupt flag
bits : 2 - 2 (1 bit)
access : read-only

HSERDYF : HSE ready interrupt flag
bits : 3 - 3 (1 bit)
access : read-only

PLLRDYF : Main PLL (PLL) ready interrupt flag
bits : 4 - 4 (1 bit)
access : read-only

PLLI2SRDYF : PLLI2S ready interrupt flag
bits : 5 - 5 (1 bit)
access : read-only

PLLSAIRDYF : PLLSAI ready interrupt flag
bits : 6 - 6 (1 bit)
access : read-only

CSSF : Clock security system interrupt flag
bits : 7 - 7 (1 bit)
access : read-only

LSIRDYIE : LSI ready interrupt enable
bits : 8 - 8 (1 bit)
access : read-write

LSERDYIE : LSE ready interrupt enable
bits : 9 - 9 (1 bit)
access : read-write

HSIRDYIE : HSI ready interrupt enable
bits : 10 - 10 (1 bit)
access : read-write

HSERDYIE : HSE ready interrupt enable
bits : 11 - 11 (1 bit)
access : read-write

PLLRDYIE : Main PLL (PLL) ready interrupt enable
bits : 12 - 12 (1 bit)
access : read-write

PLLI2SRDYIE : PLLI2S ready interrupt enable
bits : 13 - 13 (1 bit)
access : read-write

PLLSAIRDYIE : PLLSAI Ready Interrupt Enable
bits : 14 - 14 (1 bit)
access : read-write

LSIRDYC : LSI ready interrupt clear
bits : 16 - 16 (1 bit)
access : write-only

LSERDYC : LSE ready interrupt clear
bits : 17 - 17 (1 bit)
access : write-only

HSIRDYC : HSI ready interrupt clear
bits : 18 - 18 (1 bit)
access : write-only

HSERDYC : HSE ready interrupt clear
bits : 19 - 19 (1 bit)
access : write-only

PLLRDYC : Main PLL(PLL) ready interrupt clear
bits : 20 - 20 (1 bit)
access : write-only

PLLI2SRDYC : PLLI2S ready interrupt clear
bits : 21 - 21 (1 bit)
access : write-only

PLLSAIRDYC : PLLSAI Ready Interrupt Clear
bits : 22 - 22 (1 bit)
access : write-only

CSSC : Clock security system interrupt clear
bits : 23 - 23 (1 bit)
access : write-only