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LTDC

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x400 byte (0x0)
mem_usage : registers
protection : not protected

Registers

AWCR

L2CR

L2WHPCR

L2WVPCR

L2CKCR

L2PFCR

L2CACR

L2DCCR

L2BFCR

L2CFBAR

L2CFBLR

L2CFBLNR

TWCR

L2CLUTWR

GCR

SRCR

BCCR

IER

ISR

ICR

LIPCR

CPSR

CDSR

SSCR

L1CR

L1WHPCR

L1WVPCR

L1CKCR

L1PFCR

L1CACR

L1DCCR

L1BFCR

L1CFBAR

L1CFBLR

L1CFBLNR

BPCR

L1CLUTWR


AWCR

Active Width Configuration Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AWCR AWCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AAH AAV

AAH : Accumulated Active Height (in units of horizontal scan line)
bits : 0 - 10 (11 bit)

AAV : AAV
bits : 16 - 25 (10 bit)


L2CR

Layerx Control Register
address_offset : 0x104 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

L2CR L2CR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LEN COLKEN CLUTEN

LEN : Layer Enable
bits : 0 - 0 (1 bit)

COLKEN : Color Keying Enable
bits : 1 - 1 (1 bit)

CLUTEN : Color Look-Up Table Enable
bits : 4 - 4 (1 bit)


L2WHPCR

Layerx Window Horizontal Position Configuration Register
address_offset : 0x108 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

L2WHPCR L2WHPCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WHSTPOS WHSPPOS

WHSTPOS : Window Horizontal Start Position
bits : 0 - 11 (12 bit)

WHSPPOS : Window Horizontal Stop Position
bits : 16 - 27 (12 bit)


L2WVPCR

Layerx Window Vertical Position Configuration Register
address_offset : 0x10C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

L2WVPCR L2WVPCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WVSTPOS WVSPPOS

WVSTPOS : Window Vertical Start Position
bits : 0 - 10 (11 bit)

WVSPPOS : Window Vertical Stop Position
bits : 16 - 26 (11 bit)


L2CKCR

Layerx Color Keying Configuration Register
address_offset : 0x110 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

L2CKCR L2CKCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CKBLUE CKGREEN CKRED

CKBLUE : Color Key Blue value
bits : 0 - 7 (8 bit)

CKGREEN : Color Key Green value
bits : 8 - 14 (7 bit)

CKRED : Color Key Red value
bits : 15 - 23 (9 bit)


L2PFCR

Layerx Pixel Format Configuration Register
address_offset : 0x114 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

L2PFCR L2PFCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PF

PF : Pixel Format
bits : 0 - 2 (3 bit)


L2CACR

Layerx Constant Alpha Configuration Register
address_offset : 0x118 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

L2CACR L2CACR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CONSTA

CONSTA : Constant Alpha
bits : 0 - 7 (8 bit)


L2DCCR

Layerx Default Color Configuration Register
address_offset : 0x11C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

L2DCCR L2DCCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DCBLUE DCGREEN DCRED DCALPHA

DCBLUE : Default Color Blue
bits : 0 - 7 (8 bit)

DCGREEN : Default Color Green
bits : 8 - 15 (8 bit)

DCRED : Default Color Red
bits : 16 - 23 (8 bit)

DCALPHA : Default Color Alpha
bits : 24 - 31 (8 bit)


L2BFCR

Layerx Blending Factors Configuration Register
address_offset : 0x120 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

L2BFCR L2BFCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BF2 BF1

BF2 : Blending Factor 2
bits : 0 - 2 (3 bit)

BF1 : Blending Factor 1
bits : 8 - 10 (3 bit)


L2CFBAR

Layerx Color Frame Buffer Address Register
address_offset : 0x12C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

L2CFBAR L2CFBAR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CFBADD

CFBADD : Color Frame Buffer Start Address
bits : 0 - 31 (32 bit)


L2CFBLR

Layerx Color Frame Buffer Length Register
address_offset : 0x130 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

L2CFBLR L2CFBLR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CFBLL CFBP

CFBLL : Color Frame Buffer Line Length
bits : 0 - 12 (13 bit)

CFBP : Color Frame Buffer Pitch in bytes
bits : 16 - 28 (13 bit)


L2CFBLNR

Layerx ColorFrame Buffer Line Number Register
address_offset : 0x134 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

L2CFBLNR L2CFBLNR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CFBLNBR

CFBLNBR : Frame Buffer Line Number
bits : 0 - 10 (11 bit)


TWCR

Total Width Configuration Register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TWCR TWCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TOTALH TOTALW

TOTALH : Total Height (in units of horizontal scan line)
bits : 0 - 10 (11 bit)

TOTALW : Total Width (in units of pixel clock period)
bits : 16 - 25 (10 bit)


L2CLUTWR

Layerx CLUT Write Register
address_offset : 0x144 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

L2CLUTWR L2CLUTWR write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BLUE GREEN RED CLUTADD

BLUE : Blue value
bits : 0 - 7 (8 bit)

GREEN : Green value
bits : 8 - 15 (8 bit)

RED : Red value
bits : 16 - 23 (8 bit)

CLUTADD : CLUT Address
bits : 24 - 31 (8 bit)


GCR

Global Control Register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GCR GCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LTDCEN DBW DGW DRW DEN PCPOL DEPOL VSPOL HSPOL

LTDCEN : LCD-TFT controller enable bit
bits : 0 - 0 (1 bit)
access : read-write

DBW : Dither Blue Width
bits : 4 - 6 (3 bit)
access : read-only

DGW : Dither Green Width
bits : 8 - 10 (3 bit)
access : read-only

DRW : Dither Red Width
bits : 12 - 14 (3 bit)
access : read-only

DEN : Dither Enable
bits : 16 - 16 (1 bit)
access : read-write

PCPOL : Pixel Clock Polarity
bits : 28 - 28 (1 bit)
access : read-write

DEPOL : Data Enable Polarity
bits : 29 - 29 (1 bit)
access : read-write

VSPOL : Vertical Synchronization Polarity
bits : 30 - 30 (1 bit)
access : read-write

HSPOL : Horizontal Synchronization Polarity
bits : 31 - 31 (1 bit)
access : read-write


SRCR

Shadow Reload Configuration Register
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SRCR SRCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IMR VBR

IMR : Immediate Reload
bits : 0 - 0 (1 bit)

VBR : Vertical Blanking Reload
bits : 1 - 1 (1 bit)


BCCR

Background Color Configuration Register
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BCCR BCCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BC

BC : Background Color Red value
bits : 0 - 23 (24 bit)


IER

Interrupt Enable Register
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IER IER read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LIE FUIE TERRIE RRIE

LIE : Line Interrupt Enable
bits : 0 - 0 (1 bit)

FUIE : FIFO Underrun Interrupt Enable
bits : 1 - 1 (1 bit)

TERRIE : Transfer Error Interrupt Enable
bits : 2 - 2 (1 bit)

RRIE : Register Reload interrupt enable
bits : 3 - 3 (1 bit)


ISR

Interrupt Status Register
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

ISR ISR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LIF FUIF TERRIF RRIF

LIF : Line Interrupt flag
bits : 0 - 0 (1 bit)

FUIF : FIFO Underrun Interrupt flag
bits : 1 - 1 (1 bit)

TERRIF : Transfer Error interrupt flag
bits : 2 - 2 (1 bit)

RRIF : Register Reload Interrupt Flag
bits : 3 - 3 (1 bit)


ICR

Interrupt Clear Register
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

ICR ICR write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CLIF CFUIF CTERRIF CRRIF

CLIF : Clears the Line Interrupt Flag
bits : 0 - 0 (1 bit)

CFUIF : Clears the FIFO Underrun Interrupt flag
bits : 1 - 1 (1 bit)

CTERRIF : Clears the Transfer Error Interrupt Flag
bits : 2 - 2 (1 bit)

CRRIF : Clears Register Reload Interrupt Flag
bits : 3 - 3 (1 bit)


LIPCR

Line Interrupt Position Configuration Register
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

LIPCR LIPCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LIPOS

LIPOS : Line Interrupt Position
bits : 0 - 10 (11 bit)


CPSR

Current Position Status Register
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

CPSR CPSR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CYPOS CXPOS

CYPOS : Current Y Position
bits : 0 - 15 (16 bit)

CXPOS : Current X Position
bits : 16 - 31 (16 bit)


CDSR

Current Display Status Register
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0

CDSR CDSR read-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VDES HDES VSYNCS HSYNCS

VDES : Vertical Data Enable display Status
bits : 0 - 0 (1 bit)

HDES : Horizontal Data Enable display Status
bits : 1 - 1 (1 bit)

VSYNCS : Vertical Synchronization display Status
bits : 2 - 2 (1 bit)

HSYNCS : Horizontal Synchronization display Status
bits : 3 - 3 (1 bit)


SSCR

Synchronization Size Configuration Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SSCR SSCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VSH HSW

VSH : Vertical Synchronization Height (in units of horizontal scan line)
bits : 0 - 10 (11 bit)

HSW : Horizontal Synchronization Width (in units of pixel clock period)
bits : 16 - 25 (10 bit)


L1CR

Layerx Control Register
address_offset : 0x84 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

L1CR L1CR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LEN COLKEN CLUTEN

LEN : Layer Enable
bits : 0 - 0 (1 bit)

COLKEN : Color Keying Enable
bits : 1 - 1 (1 bit)

CLUTEN : Color Look-Up Table Enable
bits : 4 - 4 (1 bit)


L1WHPCR

Layerx Window Horizontal Position Configuration Register
address_offset : 0x88 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

L1WHPCR L1WHPCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WHSTPOS WHSPPOS

WHSTPOS : Window Horizontal Start Position
bits : 0 - 11 (12 bit)

WHSPPOS : Window Horizontal Stop Position
bits : 16 - 27 (12 bit)


L1WVPCR

Layerx Window Vertical Position Configuration Register
address_offset : 0x8C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

L1WVPCR L1WVPCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WVSTPOS WVSPPOS

WVSTPOS : Window Vertical Start Position
bits : 0 - 10 (11 bit)

WVSPPOS : Window Vertical Stop Position
bits : 16 - 26 (11 bit)


L1CKCR

Layerx Color Keying Configuration Register
address_offset : 0x90 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

L1CKCR L1CKCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CKBLUE CKGREEN CKRED

CKBLUE : Color Key Blue value
bits : 0 - 7 (8 bit)

CKGREEN : Color Key Green value
bits : 8 - 15 (8 bit)

CKRED : Color Key Red value
bits : 16 - 23 (8 bit)


L1PFCR

Layerx Pixel Format Configuration Register
address_offset : 0x94 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

L1PFCR L1PFCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PF

PF : Pixel Format
bits : 0 - 2 (3 bit)


L1CACR

Layerx Constant Alpha Configuration Register
address_offset : 0x98 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

L1CACR L1CACR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CONSTA

CONSTA : Constant Alpha
bits : 0 - 7 (8 bit)


L1DCCR

Layerx Default Color Configuration Register
address_offset : 0x9C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

L1DCCR L1DCCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DCBLUE DCGREEN DCRED DCALPHA

DCBLUE : Default Color Blue
bits : 0 - 7 (8 bit)

DCGREEN : Default Color Green
bits : 8 - 15 (8 bit)

DCRED : Default Color Red
bits : 16 - 23 (8 bit)

DCALPHA : Default Color Alpha
bits : 24 - 31 (8 bit)


L1BFCR

Layerx Blending Factors Configuration Register
address_offset : 0xA0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

L1BFCR L1BFCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BF2 BF1

BF2 : Blending Factor 2
bits : 0 - 2 (3 bit)

BF1 : Blending Factor 1
bits : 8 - 10 (3 bit)


L1CFBAR

Layerx Color Frame Buffer Address Register
address_offset : 0xAC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

L1CFBAR L1CFBAR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CFBADD

CFBADD : Color Frame Buffer Start Address
bits : 0 - 31 (32 bit)


L1CFBLR

Layerx Color Frame Buffer Length Register
address_offset : 0xB0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

L1CFBLR L1CFBLR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CFBLL CFBP

CFBLL : Color Frame Buffer Line Length
bits : 0 - 12 (13 bit)

CFBP : Color Frame Buffer Pitch in bytes
bits : 16 - 28 (13 bit)


L1CFBLNR

Layerx ColorFrame Buffer Line Number Register
address_offset : 0xB4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

L1CFBLNR L1CFBLNR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CFBLNBR

CFBLNBR : Frame Buffer Line Number
bits : 0 - 10 (11 bit)


BPCR

Back Porch Configuration Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BPCR BPCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AVBP AHBP

AVBP : Accumulated Vertical back porch (in units of horizontal scan line)
bits : 0 - 10 (11 bit)

AHBP : Accumulated Horizontal back porch (in units of pixel clock period)
bits : 16 - 25 (10 bit)


L1CLUTWR

Layerx CLUT Write Register
address_offset : 0xC4 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0

L1CLUTWR L1CLUTWR write-only 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BLUE GREEN RED CLUTADD

BLUE : Blue value
bits : 0 - 7 (8 bit)

GREEN : Green value
bits : 8 - 15 (8 bit)

RED : Red value
bits : 16 - 23 (8 bit)

CLUTADD : CLUT Address
bits : 24 - 31 (8 bit)



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