\n

SPI

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x860 byte (0x0)
mem_usage : registers
protection : not protected

Registers

CMD

RD_STATUS

W0

DMA_CONF

DMA_OUT_LINK

DMA_IN_LINK

DMA_STATUS

DMA_INT_ENA

DMA_INT_RAW

DMA_INT_ST

DMA_INT_CLR

IN_ERR_EOF_DES_ADDR

IN_SUC_EOF_DES_ADDR

INLINK_DSCR

INLINK_DSCR_BF0

INLINK_DSCR_BF1

OUT_EOF_BFR_DES_ADDR

OUT_EOF_DES_ADDR

OUTLINK_DSCR

CTRL2

OUTLINK_DSCR_BF0

OUTLINK_DSCR_BF1

DMA_RSTATUS

DMA_TSTATUS

CLOCK

W1

USER

USER1

W2

USER2

MOSI_DLEN

W3

MISO_DLEN

SLV_WR_STATUS

W4

PIN

SLAVE

W5

SLAVE1

DATE

SLAVE2

SLAVE3

W6

SLV_WRBUF_DLEN

SLV_RDBUF_DLEN

W7

CACHE_FCTRL

CACHE_SCTRL

SRAM_CMD

W8

SRAM_DRD_CMD

SRAM_DWR_CMD

W9

SLV_RD_BIT

W10

W11

CTRL

W12

W13

W14

W15

CTRL1

TX_CRC

EXT0

EXT1

EXT2

EXT3


CMD

SPI_CMD
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CMD CMD read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FLASH_PER FLASH_PES USR FLASH_HPM FLASH_RES FLASH_DP FLASH_CE FLASH_BE FLASH_SE FLASH_PP FLASH_WRSR FLASH_RDSR FLASH_RDID FLASH_WRDI FLASH_WREN FLASH_READ

FLASH_PER :
bits : 16 - 16 (1 bit)

FLASH_PES :
bits : 17 - 17 (1 bit)

USR :
bits : 18 - 18 (1 bit)

FLASH_HPM :
bits : 19 - 19 (1 bit)

FLASH_RES :
bits : 20 - 20 (1 bit)

FLASH_DP :
bits : 21 - 21 (1 bit)

FLASH_CE :
bits : 22 - 22 (1 bit)

FLASH_BE :
bits : 23 - 23 (1 bit)

FLASH_SE :
bits : 24 - 24 (1 bit)

FLASH_PP :
bits : 25 - 25 (1 bit)

FLASH_WRSR :
bits : 26 - 26 (1 bit)

FLASH_RDSR :
bits : 27 - 27 (1 bit)

FLASH_RDID :
bits : 28 - 28 (1 bit)

FLASH_WRDI :
bits : 29 - 29 (1 bit)

FLASH_WREN :
bits : 30 - 30 (1 bit)

FLASH_READ :
bits : 31 - 31 (1 bit)


RD_STATUS

SPI_RD_STATUS
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RD_STATUS RD_STATUS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 STATUS WB_MODE STATUS_EXT

STATUS :
bits : 0 - 15 (16 bit)

WB_MODE :
bits : 16 - 23 (8 bit)

STATUS_EXT :
bits : 24 - 31 (8 bit)


W0

SPI_W0
address_offset : 0x100 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

W0 W0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BUF

BUF :
bits : 0 - 31 (32 bit)


DMA_CONF

SPI_DMA_CONF
address_offset : 0x100 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DMA_CONF DMA_CONF read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IN_RST OUT_RST AHBM_FIFO_RST AHBM_RST IN_LOOP_TEST OUT_LOOP_TEST OUT_AUTO_WRBACK OUT_EOF_MODE OUTDSCR_BURST_EN INDSCR_BURST_EN OUT_DATA_BURST_EN DMA_RX_STOP DMA_TX_STOP DMA_CONTINUE

IN_RST :
bits : 2 - 2 (1 bit)

OUT_RST :
bits : 3 - 3 (1 bit)

AHBM_FIFO_RST :
bits : 4 - 4 (1 bit)

AHBM_RST :
bits : 5 - 5 (1 bit)

IN_LOOP_TEST :
bits : 6 - 6 (1 bit)

OUT_LOOP_TEST :
bits : 7 - 7 (1 bit)

OUT_AUTO_WRBACK :
bits : 8 - 8 (1 bit)

OUT_EOF_MODE :
bits : 9 - 9 (1 bit)

OUTDSCR_BURST_EN :
bits : 10 - 10 (1 bit)

INDSCR_BURST_EN :
bits : 11 - 11 (1 bit)

OUT_DATA_BURST_EN :
bits : 12 - 12 (1 bit)

DMA_RX_STOP :
bits : 14 - 14 (1 bit)

DMA_TX_STOP :
bits : 15 - 15 (1 bit)

DMA_CONTINUE :
bits : 16 - 16 (1 bit)


SPI_DMA_OUT_LINK
address_offset : 0x104 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DMA_OUT_LINK DMA_OUT_LINK read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OUTLINK_ADDR OUTLINK_STOP OUTLINK_START OUTLINK_RESTART

OUTLINK_ADDR :
bits : 0 - 19 (20 bit)

OUTLINK_STOP :
bits : 28 - 28 (1 bit)

OUTLINK_START :
bits : 29 - 29 (1 bit)

OUTLINK_RESTART :
bits : 30 - 30 (1 bit)


SPI_DMA_IN_LINK
address_offset : 0x108 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DMA_IN_LINK DMA_IN_LINK read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INLINK_ADDR INLINK_AUTO_RET INLINK_STOP INLINK_START INLINK_RESTART

INLINK_ADDR :
bits : 0 - 19 (20 bit)

INLINK_AUTO_RET :
bits : 20 - 20 (1 bit)

INLINK_STOP :
bits : 28 - 28 (1 bit)

INLINK_START :
bits : 29 - 29 (1 bit)

INLINK_RESTART :
bits : 30 - 30 (1 bit)


DMA_STATUS

SPI_DMA_STATUS
address_offset : 0x10C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DMA_STATUS DMA_STATUS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMA_RX_EN DMA_TX_EN

DMA_RX_EN :
bits : 0 - 0 (1 bit)

DMA_TX_EN :
bits : 1 - 1 (1 bit)


DMA_INT_ENA

SPI_DMA_INT_ENA
address_offset : 0x110 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DMA_INT_ENA DMA_INT_ENA read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INLINK_DSCR_EMPTY_INT_ENA OUTLINK_DSCR_ERROR_INT_ENA INLINK_DSCR_ERROR_INT_ENA IN_DONE_INT_ENA IN_ERR_EOF_INT_ENA IN_SUC_EOF_INT_ENA OUT_DONE_INT_ENA OUT_EOF_INT_ENA OUT_TOTAL_EOF_INT_ENA

INLINK_DSCR_EMPTY_INT_ENA :
bits : 0 - 0 (1 bit)

OUTLINK_DSCR_ERROR_INT_ENA :
bits : 1 - 1 (1 bit)

INLINK_DSCR_ERROR_INT_ENA :
bits : 2 - 2 (1 bit)

IN_DONE_INT_ENA :
bits : 3 - 3 (1 bit)

IN_ERR_EOF_INT_ENA :
bits : 4 - 4 (1 bit)

IN_SUC_EOF_INT_ENA :
bits : 5 - 5 (1 bit)

OUT_DONE_INT_ENA :
bits : 6 - 6 (1 bit)

OUT_EOF_INT_ENA :
bits : 7 - 7 (1 bit)

OUT_TOTAL_EOF_INT_ENA :
bits : 8 - 8 (1 bit)


DMA_INT_RAW

SPI_DMA_INT_RAW
address_offset : 0x114 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DMA_INT_RAW DMA_INT_RAW read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INLINK_DSCR_EMPTY_INT_RAW OUTLINK_DSCR_ERROR_INT_RAW INLINK_DSCR_ERROR_INT_RAW IN_DONE_INT_RAW IN_ERR_EOF_INT_RAW IN_SUC_EOF_INT_RAW OUT_DONE_INT_RAW OUT_EOF_INT_RAW OUT_TOTAL_EOF_INT_RAW

INLINK_DSCR_EMPTY_INT_RAW :
bits : 0 - 0 (1 bit)

OUTLINK_DSCR_ERROR_INT_RAW :
bits : 1 - 1 (1 bit)

INLINK_DSCR_ERROR_INT_RAW :
bits : 2 - 2 (1 bit)

IN_DONE_INT_RAW :
bits : 3 - 3 (1 bit)

IN_ERR_EOF_INT_RAW :
bits : 4 - 4 (1 bit)

IN_SUC_EOF_INT_RAW :
bits : 5 - 5 (1 bit)

OUT_DONE_INT_RAW :
bits : 6 - 6 (1 bit)

OUT_EOF_INT_RAW :
bits : 7 - 7 (1 bit)

OUT_TOTAL_EOF_INT_RAW :
bits : 8 - 8 (1 bit)


DMA_INT_ST

SPI_DMA_INT_ST
address_offset : 0x118 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DMA_INT_ST DMA_INT_ST read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INLINK_DSCR_EMPTY_INT_ST OUTLINK_DSCR_ERROR_INT_ST INLINK_DSCR_ERROR_INT_ST IN_DONE_INT_ST IN_ERR_EOF_INT_ST IN_SUC_EOF_INT_ST OUT_DONE_INT_ST OUT_EOF_INT_ST OUT_TOTAL_EOF_INT_ST

INLINK_DSCR_EMPTY_INT_ST :
bits : 0 - 0 (1 bit)

OUTLINK_DSCR_ERROR_INT_ST :
bits : 1 - 1 (1 bit)

INLINK_DSCR_ERROR_INT_ST :
bits : 2 - 2 (1 bit)

IN_DONE_INT_ST :
bits : 3 - 3 (1 bit)

IN_ERR_EOF_INT_ST :
bits : 4 - 4 (1 bit)

IN_SUC_EOF_INT_ST :
bits : 5 - 5 (1 bit)

OUT_DONE_INT_ST :
bits : 6 - 6 (1 bit)

OUT_EOF_INT_ST :
bits : 7 - 7 (1 bit)

OUT_TOTAL_EOF_INT_ST :
bits : 8 - 8 (1 bit)


DMA_INT_CLR

SPI_DMA_INT_CLR
address_offset : 0x11C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DMA_INT_CLR DMA_INT_CLR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INLINK_DSCR_EMPTY_INT_CLR OUTLINK_DSCR_ERROR_INT_CLR INLINK_DSCR_ERROR_INT_CLR IN_DONE_INT_CLR IN_ERR_EOF_INT_CLR IN_SUC_EOF_INT_CLR OUT_DONE_INT_CLR OUT_EOF_INT_CLR OUT_TOTAL_EOF_INT_CLR

INLINK_DSCR_EMPTY_INT_CLR :
bits : 0 - 0 (1 bit)

OUTLINK_DSCR_ERROR_INT_CLR :
bits : 1 - 1 (1 bit)

INLINK_DSCR_ERROR_INT_CLR :
bits : 2 - 2 (1 bit)

IN_DONE_INT_CLR :
bits : 3 - 3 (1 bit)

IN_ERR_EOF_INT_CLR :
bits : 4 - 4 (1 bit)

IN_SUC_EOF_INT_CLR :
bits : 5 - 5 (1 bit)

OUT_DONE_INT_CLR :
bits : 6 - 6 (1 bit)

OUT_EOF_INT_CLR :
bits : 7 - 7 (1 bit)

OUT_TOTAL_EOF_INT_CLR :
bits : 8 - 8 (1 bit)


IN_ERR_EOF_DES_ADDR

SPI_IN_ERR_EOF_DES_ADDR
address_offset : 0x120 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IN_ERR_EOF_DES_ADDR IN_ERR_EOF_DES_ADDR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMA_IN_ERR_EOF_DES_ADDR

DMA_IN_ERR_EOF_DES_ADDR :
bits : 0 - 31 (32 bit)


IN_SUC_EOF_DES_ADDR

SPI_IN_SUC_EOF_DES_ADDR
address_offset : 0x124 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IN_SUC_EOF_DES_ADDR IN_SUC_EOF_DES_ADDR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMA_IN_SUC_EOF_DES_ADDR

DMA_IN_SUC_EOF_DES_ADDR :
bits : 0 - 31 (32 bit)


SPI_INLINK_DSCR
address_offset : 0x128 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

INLINK_DSCR INLINK_DSCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMA_INLINK_DSCR

DMA_INLINK_DSCR :
bits : 0 - 31 (32 bit)


SPI_INLINK_DSCR_BF0
address_offset : 0x12C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

INLINK_DSCR_BF0 INLINK_DSCR_BF0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMA_INLINK_DSCR_BF0

DMA_INLINK_DSCR_BF0 :
bits : 0 - 31 (32 bit)


SPI_INLINK_DSCR_BF1
address_offset : 0x130 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

INLINK_DSCR_BF1 INLINK_DSCR_BF1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMA_INLINK_DSCR_BF1

DMA_INLINK_DSCR_BF1 :
bits : 0 - 31 (32 bit)


OUT_EOF_BFR_DES_ADDR

SPI_OUT_EOF_BFR_DES_ADDR
address_offset : 0x134 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OUT_EOF_BFR_DES_ADDR OUT_EOF_BFR_DES_ADDR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMA_OUT_EOF_BFR_DES_ADDR

DMA_OUT_EOF_BFR_DES_ADDR :
bits : 0 - 31 (32 bit)


OUT_EOF_DES_ADDR

SPI_OUT_EOF_DES_ADDR
address_offset : 0x138 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OUT_EOF_DES_ADDR OUT_EOF_DES_ADDR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMA_OUT_EOF_DES_ADDR

DMA_OUT_EOF_DES_ADDR :
bits : 0 - 31 (32 bit)


SPI_OUTLINK_DSCR
address_offset : 0x13C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OUTLINK_DSCR OUTLINK_DSCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMA_OUTLINK_DSCR

DMA_OUTLINK_DSCR :
bits : 0 - 31 (32 bit)


CTRL2

SPI_CTRL2
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CTRL2 CTRL2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SETUP_TIME HOLD_TIME CK_OUT_LOW_MODE CK_OUT_HIGH_MODE MISO_DELAY_MODE MISO_DELAY_NUM MOSI_DELAY_MODE MOSI_DELAY_NUM CS_DELAY_MODE CS_DELAY_NUM

SETUP_TIME :
bits : 0 - 3 (4 bit)

HOLD_TIME :
bits : 4 - 7 (4 bit)

CK_OUT_LOW_MODE :
bits : 8 - 11 (4 bit)

CK_OUT_HIGH_MODE :
bits : 12 - 15 (4 bit)

MISO_DELAY_MODE :
bits : 16 - 17 (2 bit)

MISO_DELAY_NUM :
bits : 18 - 20 (3 bit)

MOSI_DELAY_MODE :
bits : 21 - 22 (2 bit)

MOSI_DELAY_NUM :
bits : 23 - 25 (3 bit)

CS_DELAY_MODE :
bits : 26 - 27 (2 bit)

CS_DELAY_NUM :
bits : 28 - 31 (4 bit)


SPI_OUTLINK_DSCR_BF0
address_offset : 0x140 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OUTLINK_DSCR_BF0 OUTLINK_DSCR_BF0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMA_OUTLINK_DSCR_BF0

DMA_OUTLINK_DSCR_BF0 :
bits : 0 - 31 (32 bit)


SPI_OUTLINK_DSCR_BF1
address_offset : 0x144 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OUTLINK_DSCR_BF1 OUTLINK_DSCR_BF1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMA_OUTLINK_DSCR_BF1

DMA_OUTLINK_DSCR_BF1 :
bits : 0 - 31 (32 bit)


DMA_RSTATUS

SPI_DMA_RSTATUS
address_offset : 0x148 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DMA_RSTATUS DMA_RSTATUS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMA_OUT_STATUS

DMA_OUT_STATUS :
bits : 0 - 31 (32 bit)


DMA_TSTATUS

SPI_DMA_TSTATUS
address_offset : 0x14C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DMA_TSTATUS DMA_TSTATUS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMA_IN_STATUS

DMA_IN_STATUS :
bits : 0 - 31 (32 bit)


CLOCK

SPI_CLOCK
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CLOCK CLOCK read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CLKCNT_L CLKCNT_H CLKCNT_N CLKDIV_PRE CLK_EQU_SYSCLK

CLKCNT_L :
bits : 0 - 5 (6 bit)

CLKCNT_H :
bits : 6 - 11 (6 bit)

CLKCNT_N :
bits : 12 - 17 (6 bit)

CLKDIV_PRE :
bits : 18 - 30 (13 bit)

CLK_EQU_SYSCLK :
bits : 31 - 31 (1 bit)


W1

SPI_W0
address_offset : 0x184 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

W1 W1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BUF

BUF :
bits : 0 - 31 (32 bit)


USER

SPI_USER
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USER USER read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DOUTDIN CS_HOLD CS_SETUP CK_I_EDGE CK_OUT_EDGE RD_BYTE_ORDER WR_BYTE_ORDER FWRITE_DUAL FWRITE_QUAD FWRITE_DIO FWRITE_QIO SIO USR_HOLD_POL USR_DOUT_HOLD USR_DIN_HOLD USR_DUMMY_HOLD USR_ADDR_HOLD USR_CMD_HOLD USR_PREP_HOLD USR_MISO_HIGHPART USR_MOSI_HIGHPART USR_DUMMY_IDLE USR_MOSI USR_MISO USR_DUMMY USR_ADDR USR_COMMAND

DOUTDIN :
bits : 0 - 0 (1 bit)

CS_HOLD :
bits : 4 - 4 (1 bit)

CS_SETUP :
bits : 5 - 5 (1 bit)

CK_I_EDGE :
bits : 6 - 6 (1 bit)

CK_OUT_EDGE :
bits : 7 - 7 (1 bit)

RD_BYTE_ORDER :
bits : 10 - 10 (1 bit)

WR_BYTE_ORDER :
bits : 11 - 11 (1 bit)

FWRITE_DUAL :
bits : 12 - 12 (1 bit)

FWRITE_QUAD :
bits : 13 - 13 (1 bit)

FWRITE_DIO :
bits : 14 - 14 (1 bit)

FWRITE_QIO :
bits : 15 - 15 (1 bit)

SIO :
bits : 16 - 16 (1 bit)

USR_HOLD_POL :
bits : 17 - 17 (1 bit)

USR_DOUT_HOLD :
bits : 18 - 18 (1 bit)

USR_DIN_HOLD :
bits : 19 - 19 (1 bit)

USR_DUMMY_HOLD :
bits : 20 - 20 (1 bit)

USR_ADDR_HOLD :
bits : 21 - 21 (1 bit)

USR_CMD_HOLD :
bits : 22 - 22 (1 bit)

USR_PREP_HOLD :
bits : 23 - 23 (1 bit)

USR_MISO_HIGHPART :
bits : 24 - 24 (1 bit)

USR_MOSI_HIGHPART :
bits : 25 - 25 (1 bit)

USR_DUMMY_IDLE :
bits : 26 - 26 (1 bit)

USR_MOSI :
bits : 27 - 27 (1 bit)

USR_MISO :
bits : 28 - 28 (1 bit)

USR_DUMMY :
bits : 29 - 29 (1 bit)

USR_ADDR :
bits : 30 - 30 (1 bit)

USR_COMMAND :
bits : 31 - 31 (1 bit)


USER1

SPI_USER1
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USER1 USER1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 USR_DUMMY_CYCLELEN USR_ADDR_BITLEN

USR_DUMMY_CYCLELEN :
bits : 0 - 7 (8 bit)

USR_ADDR_BITLEN :
bits : 26 - 31 (6 bit)


W2

SPI_W0
address_offset : 0x20C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

W2 W2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BUF

BUF :
bits : 0 - 31 (32 bit)


USER2

SPI_USER2
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USER2 USER2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 USR_COMMAND_VALUE USR_COMMAND_BITLEN

USR_COMMAND_VALUE :
bits : 0 - 15 (16 bit)

USR_COMMAND_BITLEN :
bits : 28 - 31 (4 bit)


MOSI_DLEN

SPI_MOSI_DLEN
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MOSI_DLEN MOSI_DLEN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 USR_MOSI_DBITLEN

USR_MOSI_DBITLEN :
bits : 0 - 23 (24 bit)


W3

SPI_W0
address_offset : 0x298 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

W3 W3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BUF

BUF :
bits : 0 - 31 (32 bit)


MISO_DLEN

SPI_MISO_DLEN
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MISO_DLEN MISO_DLEN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 USR_MISO_DBITLEN

USR_MISO_DBITLEN :
bits : 0 - 23 (24 bit)


SLV_WR_STATUS

SPI_SLV_WR_STATUS
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SLV_WR_STATUS SLV_WR_STATUS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SLV_WR_ST

SLV_WR_ST :
bits : 0 - 31 (32 bit)


W4

SPI_W0
address_offset : 0x328 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

W4 W4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BUF

BUF :
bits : 0 - 31 (32 bit)


PIN

SPI_PIN
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PIN PIN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CS0_DIS CS1_DIS CS2_DIS CK_DIS MASTER_CS_POL MASTER_CK_SEL CK_IDLE_EDGE CS_KEEP_ACTIVE

CS0_DIS :
bits : 0 - 0 (1 bit)

CS1_DIS :
bits : 1 - 1 (1 bit)

CS2_DIS :
bits : 2 - 2 (1 bit)

CK_DIS :
bits : 5 - 5 (1 bit)

MASTER_CS_POL :
bits : 6 - 8 (3 bit)

MASTER_CK_SEL :
bits : 11 - 13 (3 bit)

CK_IDLE_EDGE :
bits : 29 - 29 (1 bit)

CS_KEEP_ACTIVE :
bits : 30 - 30 (1 bit)


SLAVE

SPI_SLAVE
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SLAVE SLAVE read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SLV_RD_BUF_DONE SLV_WR_BUF_DONE SLV_RD_STA_DONE SLV_WR_STA_DONE TRANS_DONE INT_EN CS_I_MODE SLV_LAST_COMMAND SLV_LAST_STATE TRANS_CNT SLV_CMD_DEFINE SLV_WR_RD_STA_EN SLV_WR_RD_BUF_EN SLAVE_MODE SYNC_RESET

SLV_RD_BUF_DONE :
bits : 0 - 0 (1 bit)

SLV_WR_BUF_DONE :
bits : 1 - 1 (1 bit)

SLV_RD_STA_DONE :
bits : 2 - 2 (1 bit)

SLV_WR_STA_DONE :
bits : 3 - 3 (1 bit)

TRANS_DONE :
bits : 4 - 4 (1 bit)

INT_EN :
bits : 5 - 9 (5 bit)

CS_I_MODE :
bits : 10 - 11 (2 bit)

SLV_LAST_COMMAND :
bits : 17 - 19 (3 bit)

SLV_LAST_STATE :
bits : 20 - 22 (3 bit)

TRANS_CNT :
bits : 23 - 26 (4 bit)

SLV_CMD_DEFINE :
bits : 27 - 27 (1 bit)

SLV_WR_RD_STA_EN :
bits : 28 - 28 (1 bit)

SLV_WR_RD_BUF_EN :
bits : 29 - 29 (1 bit)

SLAVE_MODE :
bits : 30 - 30 (1 bit)

SYNC_RESET :
bits : 31 - 31 (1 bit)


W5

SPI_W0
address_offset : 0x3BC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

W5 W5 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BUF

BUF :
bits : 0 - 31 (32 bit)


SLAVE1

SPI_SLAVE1
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SLAVE1 SLAVE1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SLV_RDBUF_DUMMY_EN SLV_WRBUF_DUMMY_EN SLV_RDSTA_DUMMY_EN SLV_WRSTA_DUMMY_EN SLV_WR_ADDR_BITLEN SLV_RD_ADDR_BITLEN SLV_STATUS_READBACK SLV_STATUS_FAST_EN SLV_STATUS_BITLEN

SLV_RDBUF_DUMMY_EN :
bits : 0 - 0 (1 bit)

SLV_WRBUF_DUMMY_EN :
bits : 1 - 1 (1 bit)

SLV_RDSTA_DUMMY_EN :
bits : 2 - 2 (1 bit)

SLV_WRSTA_DUMMY_EN :
bits : 3 - 3 (1 bit)

SLV_WR_ADDR_BITLEN :
bits : 4 - 9 (6 bit)

SLV_RD_ADDR_BITLEN :
bits : 10 - 15 (6 bit)

SLV_STATUS_READBACK :
bits : 25 - 25 (1 bit)

SLV_STATUS_FAST_EN :
bits : 26 - 26 (1 bit)

SLV_STATUS_BITLEN :
bits : 27 - 31 (5 bit)


DATE

SPI_DATE
address_offset : 0x3FC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DATE DATE read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATE

DATE :
bits : 0 - 27 (28 bit)


SLAVE2

SPI_SLAVE2
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SLAVE2 SLAVE2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SLV_RDSTA_DUMMY_CYCLELEN SLV_WRSTA_DUMMY_CYCLELEN SLV_RDBUF_DUMMY_CYCLELEN SLV_WRBUF_DUMMY_CYCLELEN

SLV_RDSTA_DUMMY_CYCLELEN :
bits : 0 - 7 (8 bit)

SLV_WRSTA_DUMMY_CYCLELEN :
bits : 8 - 15 (8 bit)

SLV_RDBUF_DUMMY_CYCLELEN :
bits : 16 - 23 (8 bit)

SLV_WRBUF_DUMMY_CYCLELEN :
bits : 24 - 31 (8 bit)


SLAVE3

SPI_SLAVE3
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SLAVE3 SLAVE3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SLV_RDBUF_CMD_VALUE SLV_WRBUF_CMD_VALUE SLV_RDSTA_CMD_VALUE SLV_WRSTA_CMD_VALUE

SLV_RDBUF_CMD_VALUE :
bits : 0 - 7 (8 bit)

SLV_WRBUF_CMD_VALUE :
bits : 8 - 15 (8 bit)

SLV_RDSTA_CMD_VALUE :
bits : 16 - 23 (8 bit)

SLV_WRSTA_CMD_VALUE :
bits : 24 - 31 (8 bit)


W6

SPI_W0
address_offset : 0x454 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

W6 W6 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BUF

BUF :
bits : 0 - 31 (32 bit)


SLV_WRBUF_DLEN

SPI_SLV_WRBUF_DLEN
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SLV_WRBUF_DLEN SLV_WRBUF_DLEN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SLV_WRBUF_DBITLEN

SLV_WRBUF_DBITLEN :
bits : 0 - 23 (24 bit)


SLV_RDBUF_DLEN

SPI_SLV_RDBUF_DLEN
address_offset : 0x4C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SLV_RDBUF_DLEN SLV_RDBUF_DLEN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SLV_RDBUF_DBITLEN

SLV_RDBUF_DBITLEN :
bits : 0 - 23 (24 bit)


W7

SPI_W0
address_offset : 0x4F0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

W7 W7 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BUF

BUF :
bits : 0 - 31 (32 bit)


CACHE_FCTRL

SPI_CACHE_FCTRL
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CACHE_FCTRL CACHE_FCTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CACHE_REQ_EN CACHE_USR_CMD_4BYTE CACHE_FLASH_USR_CMD CACHE_FLASH_PES_EN

CACHE_REQ_EN :
bits : 0 - 0 (1 bit)

CACHE_USR_CMD_4BYTE :
bits : 1 - 1 (1 bit)

CACHE_FLASH_USR_CMD :
bits : 2 - 2 (1 bit)

CACHE_FLASH_PES_EN :
bits : 3 - 3 (1 bit)


CACHE_SCTRL

SPI_CACHE_SCTRL
address_offset : 0x54 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CACHE_SCTRL CACHE_SCTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 USR_SRAM_DIO USR_SRAM_QIO USR_WR_SRAM_DUMMY USR_RD_SRAM_DUMMY CACHE_SRAM_USR_RCMD SRAM_BYTES_LEN SRAM_DUMMY_CYCLELEN SRAM_ADDR_BITLEN CACHE_SRAM_USR_WCMD

USR_SRAM_DIO :
bits : 1 - 1 (1 bit)

USR_SRAM_QIO :
bits : 2 - 2 (1 bit)

USR_WR_SRAM_DUMMY :
bits : 3 - 3 (1 bit)

USR_RD_SRAM_DUMMY :
bits : 4 - 4 (1 bit)

CACHE_SRAM_USR_RCMD :
bits : 5 - 5 (1 bit)

SRAM_BYTES_LEN :
bits : 6 - 13 (8 bit)

SRAM_DUMMY_CYCLELEN :
bits : 14 - 21 (8 bit)

SRAM_ADDR_BITLEN :
bits : 22 - 27 (6 bit)

CACHE_SRAM_USR_WCMD :
bits : 28 - 28 (1 bit)


SRAM_CMD

SPI_SRAM_CMD
address_offset : 0x58 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SRAM_CMD SRAM_CMD read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SRAM_DIO SRAM_QIO SRAM_RSTIO

SRAM_DIO :
bits : 0 - 0 (1 bit)

SRAM_QIO :
bits : 1 - 1 (1 bit)

SRAM_RSTIO :
bits : 4 - 4 (1 bit)


W8

SPI_W0
address_offset : 0x590 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

W8 W8 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BUF

BUF :
bits : 0 - 31 (32 bit)


SRAM_DRD_CMD

SPI_SRAM_DRD_CMD
address_offset : 0x5C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SRAM_DRD_CMD SRAM_DRD_CMD read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CACHE_SRAM_USR_RD_CMD_VALUE CACHE_SRAM_USR_RD_CMD_BITLEN

CACHE_SRAM_USR_RD_CMD_VALUE :
bits : 0 - 15 (16 bit)

CACHE_SRAM_USR_RD_CMD_BITLEN :
bits : 28 - 31 (4 bit)


SRAM_DWR_CMD

SPI_SRAM_DWR_CMD
address_offset : 0x60 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SRAM_DWR_CMD SRAM_DWR_CMD read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CACHE_SRAM_USR_WR_CMD_VALUE CACHE_SRAM_USR_WR_CMD_BITLEN

CACHE_SRAM_USR_WR_CMD_VALUE :
bits : 0 - 15 (16 bit)

CACHE_SRAM_USR_WR_CMD_BITLEN :
bits : 28 - 31 (4 bit)


W9

SPI_W0
address_offset : 0x634 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

W9 W9 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BUF

BUF :
bits : 0 - 31 (32 bit)


SLV_RD_BIT

SPI_SLV_RD_BIT
address_offset : 0x64 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SLV_RD_BIT SLV_RD_BIT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SLV_RDATA_BIT

SLV_RDATA_BIT :
bits : 0 - 23 (24 bit)


W10

SPI_W0
address_offset : 0x6DC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

W10 W10 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BUF

BUF :
bits : 0 - 31 (32 bit)


W11

SPI_W0
address_offset : 0x788 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

W11 W11 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BUF

BUF :
bits : 0 - 31 (32 bit)


CTRL

SPI_CTRL
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CTRL CTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FCS_CRC_EN TX_CRC_EN WAIT_FLASH_IDLE_EN FASTRD_MODE FREAD_DUAL RESANDRES FREAD_QUAD WP_REG WRSR_2B FREAD_DIO FREAD_QIO RD_BIT_ORDER WR_BIT_ORDER

FCS_CRC_EN :
bits : 10 - 10 (1 bit)

TX_CRC_EN :
bits : 11 - 11 (1 bit)

WAIT_FLASH_IDLE_EN :
bits : 12 - 12 (1 bit)

FASTRD_MODE :
bits : 13 - 13 (1 bit)

FREAD_DUAL :
bits : 14 - 14 (1 bit)

RESANDRES :
bits : 15 - 15 (1 bit)

FREAD_QUAD :
bits : 20 - 20 (1 bit)

WP_REG :
bits : 21 - 21 (1 bit)

WRSR_2B :
bits : 22 - 22 (1 bit)

FREAD_DIO :
bits : 23 - 23 (1 bit)

FREAD_QIO :
bits : 24 - 24 (1 bit)

RD_BIT_ORDER :
bits : 25 - 25 (1 bit)

WR_BIT_ORDER :
bits : 26 - 26 (1 bit)


W12

SPI_W0
address_offset : 0x838 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

W12 W12 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BUF

BUF :
bits : 0 - 31 (32 bit)


W13

SPI_W0
address_offset : 0x8EC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

W13 W13 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BUF

BUF :
bits : 0 - 31 (32 bit)


W14

SPI_W0
address_offset : 0x9A4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

W14 W14 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BUF

BUF :
bits : 0 - 31 (32 bit)


W15

SPI_W0
address_offset : 0xA60 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

W15 W15 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BUF

BUF :
bits : 0 - 31 (32 bit)


CTRL1

SPI_CTRL1
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CTRL1 CTRL1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CS_HOLD_DELAY_RES CS_HOLD_DELAY

CS_HOLD_DELAY_RES :
bits : 16 - 27 (12 bit)

CS_HOLD_DELAY :
bits : 28 - 31 (4 bit)


TX_CRC

SPI_TX_CRC
address_offset : 0xC0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TX_CRC TX_CRC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TX_CRC_DATA

TX_CRC_DATA :
bits : 0 - 31 (32 bit)


EXT0

SPI_EXT0
address_offset : 0xF0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EXT0 EXT0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 T_PP_TIME T_PP_SHIFT T_PP_ENA

T_PP_TIME :
bits : 0 - 11 (12 bit)

T_PP_SHIFT :
bits : 16 - 19 (4 bit)

T_PP_ENA :
bits : 31 - 31 (1 bit)


EXT1

SPI_EXT1
address_offset : 0xF4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EXT1 EXT1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 T_ERASE_TIME T_ERASE_SHIFT T_ERASE_ENA

T_ERASE_TIME :
bits : 0 - 11 (12 bit)

T_ERASE_SHIFT :
bits : 16 - 19 (4 bit)

T_ERASE_ENA :
bits : 31 - 31 (1 bit)


EXT2

SPI_EXT2
address_offset : 0xF8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EXT2 EXT2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ST

ST :
bits : 0 - 2 (3 bit)


EXT3

SPI_EXT3
address_offset : 0xFC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EXT3 EXT3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INT_HOLD_ENA

INT_HOLD_ENA :
bits : 0 - 1 (2 bit)



Is something missing? Is something wrong? can you help correct it ? Please contact us at info@chipselect.org !

This website is sponsored by EmbeetleEmbeetle, an IDE designed from scratch for embedded software developers.