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I2C

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x4C0 byte (0x0)
mem_usage : registers
protection : not protected

Registers

SCL_LOW_PERIOD

SLAVE_ADDR

RXFIFO_ST

FIFO_CONF

DATA

INT_RAW

INT_CLR

INT_ENA

INT_STATUS

SDA_HOLD

SDA_SAMPLE

SCL_HIGH_PERIOD

CTR

SCL_START_HOLD

SCL_RSTART_SETUP

SCL_STOP_HOLD

SCL_STOP_SETUP

SCL_FILTER_CFG

SDA_FILTER_CFG

COMD0

COMD1

COMD2

COMD3

COMD4

COMD5

COMD6

COMD7

COMD8

COMD9

SR

COMD10

COMD11

COMD12

COMD13

COMD14

COMD15

TO

DATE


SCL_LOW_PERIOD

I2C_SCL_LOW_PERIOD
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SCL_LOW_PERIOD SCL_LOW_PERIOD read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PERIOD

PERIOD :
bits : 0 - 13 (14 bit)


SLAVE_ADDR

I2C_SLAVE_ADDR
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SLAVE_ADDR SLAVE_ADDR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SLAVE_ADDR ADDR_10BIT_EN

SLAVE_ADDR :
bits : 0 - 14 (15 bit)

ADDR_10BIT_EN :
bits : 31 - 31 (1 bit)


RXFIFO_ST

I2C_RXFIFO_ST
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RXFIFO_ST RXFIFO_ST read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RXFIFO_START_ADDR RXFIFO_END_ADDR TXFIFO_START_ADDR TXFIFO_END_ADDR

RXFIFO_START_ADDR :
bits : 0 - 4 (5 bit)

RXFIFO_END_ADDR :
bits : 5 - 9 (5 bit)

TXFIFO_START_ADDR :
bits : 10 - 14 (5 bit)

TXFIFO_END_ADDR :
bits : 15 - 19 (5 bit)


FIFO_CONF

I2C_FIFO_CONF
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FIFO_CONF FIFO_CONF read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RXFIFO_FULL_THRHD TXFIFO_EMPTY_THRHD NONFIFO_EN FIFO_ADDR_CFG_EN RX_FIFO_RST TX_FIFO_RST NONFIFO_RX_THRES NONFIFO_TX_THRES

RXFIFO_FULL_THRHD :
bits : 0 - 4 (5 bit)

TXFIFO_EMPTY_THRHD :
bits : 5 - 9 (5 bit)

NONFIFO_EN :
bits : 10 - 10 (1 bit)

FIFO_ADDR_CFG_EN :
bits : 11 - 11 (1 bit)

RX_FIFO_RST :
bits : 12 - 12 (1 bit)

TX_FIFO_RST :
bits : 13 - 13 (1 bit)

NONFIFO_RX_THRES :
bits : 14 - 19 (6 bit)

NONFIFO_TX_THRES :
bits : 20 - 25 (6 bit)


DATA

I2C_DATA
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DATA DATA read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FIFO_RDATA

FIFO_RDATA :
bits : 0 - 7 (8 bit)


INT_RAW

I2C_INT_RAW
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

INT_RAW INT_RAW read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RXFIFO_FULL_INT_RAW TXFIFO_EMPTY_INT_RAW RXFIFO_OVF_INT_RAW END_DETECT_INT_RAW SLAVE_TRAN_COMP_INT_RAW ARBITRATION_LOST_INT_RAW MASTER_TRAN_COMP_INT_RAW TRANS_COMPLETE_INT_RAW TIME_OUT_INT_RAW TRANS_START_INT_RAW ACK_ERR_INT_RAW RX_REC_FULL_INT_RAW TX_SEND_EMPTY_INT_RAW

RXFIFO_FULL_INT_RAW :
bits : 0 - 0 (1 bit)

TXFIFO_EMPTY_INT_RAW :
bits : 1 - 1 (1 bit)

RXFIFO_OVF_INT_RAW :
bits : 2 - 2 (1 bit)

END_DETECT_INT_RAW :
bits : 3 - 3 (1 bit)

SLAVE_TRAN_COMP_INT_RAW :
bits : 4 - 4 (1 bit)

ARBITRATION_LOST_INT_RAW :
bits : 5 - 5 (1 bit)

MASTER_TRAN_COMP_INT_RAW :
bits : 6 - 6 (1 bit)

TRANS_COMPLETE_INT_RAW :
bits : 7 - 7 (1 bit)

TIME_OUT_INT_RAW :
bits : 8 - 8 (1 bit)

TRANS_START_INT_RAW :
bits : 9 - 9 (1 bit)

ACK_ERR_INT_RAW :
bits : 10 - 10 (1 bit)

RX_REC_FULL_INT_RAW :
bits : 11 - 11 (1 bit)

TX_SEND_EMPTY_INT_RAW :
bits : 12 - 12 (1 bit)


INT_CLR

I2C_INT_CLR
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

INT_CLR INT_CLR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RXFIFO_FULL_INT_CLR TXFIFO_EMPTY_INT_CLR RXFIFO_OVF_INT_CLR END_DETECT_INT_CLR SLAVE_TRAN_COMP_INT_CLR ARBITRATION_LOST_INT_CLR MASTER_TRAN_COMP_INT_CLR TRANS_COMPLETE_INT_CLR TIME_OUT_INT_CLR TRANS_START_INT_CLR ACK_ERR_INT_CLR RX_REC_FULL_INT_CLR TX_SEND_EMPTY_INT_CLR

RXFIFO_FULL_INT_CLR :
bits : 0 - 0 (1 bit)

TXFIFO_EMPTY_INT_CLR :
bits : 1 - 1 (1 bit)

RXFIFO_OVF_INT_CLR :
bits : 2 - 2 (1 bit)

END_DETECT_INT_CLR :
bits : 3 - 3 (1 bit)

SLAVE_TRAN_COMP_INT_CLR :
bits : 4 - 4 (1 bit)

ARBITRATION_LOST_INT_CLR :
bits : 5 - 5 (1 bit)

MASTER_TRAN_COMP_INT_CLR :
bits : 6 - 6 (1 bit)

TRANS_COMPLETE_INT_CLR :
bits : 7 - 7 (1 bit)

TIME_OUT_INT_CLR :
bits : 8 - 8 (1 bit)

TRANS_START_INT_CLR :
bits : 9 - 9 (1 bit)

ACK_ERR_INT_CLR :
bits : 10 - 10 (1 bit)

RX_REC_FULL_INT_CLR :
bits : 11 - 11 (1 bit)

TX_SEND_EMPTY_INT_CLR :
bits : 12 - 12 (1 bit)


INT_ENA

I2C_INT_ENA
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

INT_ENA INT_ENA read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RXFIFO_FULL_INT_ENA TXFIFO_EMPTY_INT_ENA RXFIFO_OVF_INT_ENA END_DETECT_INT_ENA SLAVE_TRAN_COMP_INT_ENA ARBITRATION_LOST_INT_ENA MASTER_TRAN_COMP_INT_ENA TRANS_COMPLETE_INT_ENA TIME_OUT_INT_ENA TRANS_START_INT_ENA ACK_ERR_INT_ENA RX_REC_FULL_INT_ENA TX_SEND_EMPTY_INT_ENA

RXFIFO_FULL_INT_ENA :
bits : 0 - 0 (1 bit)

TXFIFO_EMPTY_INT_ENA :
bits : 1 - 1 (1 bit)

RXFIFO_OVF_INT_ENA :
bits : 2 - 2 (1 bit)

END_DETECT_INT_ENA :
bits : 3 - 3 (1 bit)

SLAVE_TRAN_COMP_INT_ENA :
bits : 4 - 4 (1 bit)

ARBITRATION_LOST_INT_ENA :
bits : 5 - 5 (1 bit)

MASTER_TRAN_COMP_INT_ENA :
bits : 6 - 6 (1 bit)

TRANS_COMPLETE_INT_ENA :
bits : 7 - 7 (1 bit)

TIME_OUT_INT_ENA :
bits : 8 - 8 (1 bit)

TRANS_START_INT_ENA :
bits : 9 - 9 (1 bit)

ACK_ERR_INT_ENA :
bits : 10 - 10 (1 bit)

RX_REC_FULL_INT_ENA :
bits : 11 - 11 (1 bit)

TX_SEND_EMPTY_INT_ENA :
bits : 12 - 12 (1 bit)


INT_STATUS

I2C_INT_STATUS
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

INT_STATUS INT_STATUS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RXFIFO_FULL_INT_ST TXFIFO_EMPTY_INT_ST RXFIFO_OVF_INT_ST END_DETECT_INT_ST SLAVE_TRAN_COMP_INT_ST ARBITRATION_LOST_INT_ST MASTER_TRAN_COMP_INT_ST TRANS_COMPLETE_INT_ST TIME_OUT_INT_ST TRANS_START_INT_ST ACK_ERR_INT_ST RX_REC_FULL_INT_ST TX_SEND_EMPTY_INT_ST

RXFIFO_FULL_INT_ST :
bits : 0 - 0 (1 bit)

TXFIFO_EMPTY_INT_ST :
bits : 1 - 1 (1 bit)

RXFIFO_OVF_INT_ST :
bits : 2 - 2 (1 bit)

END_DETECT_INT_ST :
bits : 3 - 3 (1 bit)

SLAVE_TRAN_COMP_INT_ST :
bits : 4 - 4 (1 bit)

ARBITRATION_LOST_INT_ST :
bits : 5 - 5 (1 bit)

MASTER_TRAN_COMP_INT_ST :
bits : 6 - 6 (1 bit)

TRANS_COMPLETE_INT_ST :
bits : 7 - 7 (1 bit)

TIME_OUT_INT_ST :
bits : 8 - 8 (1 bit)

TRANS_START_INT_ST :
bits : 9 - 9 (1 bit)

ACK_ERR_INT_ST :
bits : 10 - 10 (1 bit)

RX_REC_FULL_INT_ST :
bits : 11 - 11 (1 bit)

TX_SEND_EMPTY_INT_ST :
bits : 12 - 12 (1 bit)


SDA_HOLD

I2C_SDA_HOLD
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SDA_HOLD SDA_HOLD read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TIME

TIME :
bits : 0 - 9 (10 bit)


SDA_SAMPLE

I2C_SDA_SAMPLE
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SDA_SAMPLE SDA_SAMPLE read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TIME

TIME :
bits : 0 - 9 (10 bit)


SCL_HIGH_PERIOD

I2C_SCL_HIGH_PERIOD
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SCL_HIGH_PERIOD SCL_HIGH_PERIOD read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PERIOD

PERIOD :
bits : 0 - 13 (14 bit)


CTR

I2C_CTR
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CTR CTR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SDA_FORCE_OUT SCL_FORCE_OUT SAMPLE_SCL_LEVEL MS_MODE TRANS_START TX_LSB_FIRST RX_LSB_FIRST CLK_EN

SDA_FORCE_OUT :
bits : 0 - 0 (1 bit)

SCL_FORCE_OUT :
bits : 1 - 1 (1 bit)

SAMPLE_SCL_LEVEL :
bits : 2 - 2 (1 bit)

MS_MODE :
bits : 4 - 4 (1 bit)

TRANS_START :
bits : 5 - 5 (1 bit)

TX_LSB_FIRST :
bits : 6 - 6 (1 bit)

RX_LSB_FIRST :
bits : 7 - 7 (1 bit)

CLK_EN :
bits : 8 - 8 (1 bit)


SCL_START_HOLD

I2C_SCL_START_HOLD
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SCL_START_HOLD SCL_START_HOLD read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TIME

TIME :
bits : 0 - 9 (10 bit)


SCL_RSTART_SETUP

I2C_SCL_RSTART_SETUP
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SCL_RSTART_SETUP SCL_RSTART_SETUP read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TIME

TIME :
bits : 0 - 9 (10 bit)


SCL_STOP_HOLD

I2C_SCL_STOP_HOLD
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SCL_STOP_HOLD SCL_STOP_HOLD read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TIME

TIME :
bits : 0 - 13 (14 bit)


SCL_STOP_SETUP

I2C_SCL_STOP_SETUP
address_offset : 0x4C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SCL_STOP_SETUP SCL_STOP_SETUP read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TIME

TIME :
bits : 0 - 9 (10 bit)


SCL_FILTER_CFG

I2C_SCL_FILTER_CFG
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SCL_FILTER_CFG SCL_FILTER_CFG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SCL_FILTER_THRES SCL_FILTER_EN

SCL_FILTER_THRES :
bits : 0 - 2 (3 bit)

SCL_FILTER_EN :
bits : 3 - 3 (1 bit)


SDA_FILTER_CFG

I2C_SDA_FILTER_CFG
address_offset : 0x54 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SDA_FILTER_CFG SDA_FILTER_CFG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SDA_FILTER_THRES SDA_FILTER_EN

SDA_FILTER_THRES :
bits : 0 - 2 (3 bit)

SDA_FILTER_EN :
bits : 3 - 3 (1 bit)


COMD0

I2C_COMD0
address_offset : 0x58 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

COMD0 COMD0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 COMMAND0 COMMAND0_DONE

COMMAND0 :
bits : 0 - 13 (14 bit)

COMMAND0_DONE :
bits : 31 - 31 (1 bit)


COMD1

I2C_COMD1
address_offset : 0x5C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

COMD1 COMD1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 COMMAND1 COMMAND1_DONE

COMMAND1 :
bits : 0 - 13 (14 bit)

COMMAND1_DONE :
bits : 31 - 31 (1 bit)


COMD2

I2C_COMD2
address_offset : 0x60 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

COMD2 COMD2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 COMMAND2 COMMAND2_DONE

COMMAND2 :
bits : 0 - 13 (14 bit)

COMMAND2_DONE :
bits : 31 - 31 (1 bit)


COMD3

I2C_COMD3
address_offset : 0x64 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

COMD3 COMD3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 COMMAND3 COMMAND3_DONE

COMMAND3 :
bits : 0 - 13 (14 bit)

COMMAND3_DONE :
bits : 31 - 31 (1 bit)


COMD4

I2C_COMD4
address_offset : 0x68 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

COMD4 COMD4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 COMMAND4 COMMAND4_DONE

COMMAND4 :
bits : 0 - 13 (14 bit)

COMMAND4_DONE :
bits : 31 - 31 (1 bit)


COMD5

I2C_COMD5
address_offset : 0x6C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

COMD5 COMD5 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 COMMAND5 COMMAND5_DONE

COMMAND5 :
bits : 0 - 13 (14 bit)

COMMAND5_DONE :
bits : 31 - 31 (1 bit)


COMD6

I2C_COMD6
address_offset : 0x70 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

COMD6 COMD6 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 COMMAND6 COMMAND6_DONE

COMMAND6 :
bits : 0 - 13 (14 bit)

COMMAND6_DONE :
bits : 31 - 31 (1 bit)


COMD7

I2C_COMD7
address_offset : 0x74 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

COMD7 COMD7 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 COMMAND7 COMMAND7_DONE

COMMAND7 :
bits : 0 - 13 (14 bit)

COMMAND7_DONE :
bits : 31 - 31 (1 bit)


COMD8

I2C_COMD8
address_offset : 0x78 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

COMD8 COMD8 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 COMMAND8 COMMAND8_DONE

COMMAND8 :
bits : 0 - 13 (14 bit)

COMMAND8_DONE :
bits : 31 - 31 (1 bit)


COMD9

I2C_COMD9
address_offset : 0x7C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

COMD9 COMD9 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 COMMAND9 COMMAND9_DONE

COMMAND9 :
bits : 0 - 13 (14 bit)

COMMAND9_DONE :
bits : 31 - 31 (1 bit)


SR

I2C_SR
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SR SR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ACK_REC SLAVE_RW TIME_OUT ARB_LOST BUS_BUSY SLAVE_ADDRESSED BYTE_TRANS RXFIFO_CNT TXFIFO_CNT SCL_MAIN_STATE_LAST SCL_STATE_LAST

ACK_REC :
bits : 0 - 0 (1 bit)

SLAVE_RW :
bits : 1 - 1 (1 bit)

TIME_OUT :
bits : 2 - 2 (1 bit)

ARB_LOST :
bits : 3 - 3 (1 bit)

BUS_BUSY :
bits : 4 - 4 (1 bit)

SLAVE_ADDRESSED :
bits : 5 - 5 (1 bit)

BYTE_TRANS :
bits : 6 - 6 (1 bit)

RXFIFO_CNT :
bits : 8 - 13 (6 bit)

TXFIFO_CNT :
bits : 18 - 23 (6 bit)

SCL_MAIN_STATE_LAST :
bits : 24 - 26 (3 bit)

SCL_STATE_LAST :
bits : 28 - 30 (3 bit)


COMD10

I2C_COMD10
address_offset : 0x80 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

COMD10 COMD10 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 COMMAND10 COMMAND10_DONE

COMMAND10 :
bits : 0 - 13 (14 bit)

COMMAND10_DONE :
bits : 31 - 31 (1 bit)


COMD11

I2C_COMD11
address_offset : 0x84 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

COMD11 COMD11 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 COMMAND11 COMMAND11_DONE

COMMAND11 :
bits : 0 - 13 (14 bit)

COMMAND11_DONE :
bits : 31 - 31 (1 bit)


COMD12

I2C_COMD12
address_offset : 0x88 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

COMD12 COMD12 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 COMMAND12 COMMAND12_DONE

COMMAND12 :
bits : 0 - 13 (14 bit)

COMMAND12_DONE :
bits : 31 - 31 (1 bit)


COMD13

I2C_COMD13
address_offset : 0x8C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

COMD13 COMD13 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 COMMAND13 COMMAND13_DONE

COMMAND13 :
bits : 0 - 13 (14 bit)

COMMAND13_DONE :
bits : 31 - 31 (1 bit)


COMD14

I2C_COMD14
address_offset : 0x90 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

COMD14 COMD14 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 COMMAND14 COMMAND14_DONE

COMMAND14 :
bits : 0 - 13 (14 bit)

COMMAND14_DONE :
bits : 31 - 31 (1 bit)


COMD15

I2C_COMD15
address_offset : 0x94 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

COMD15 COMD15 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 COMMAND15 COMMAND15_DONE

COMMAND15 :
bits : 0 - 13 (14 bit)

COMMAND15_DONE :
bits : 31 - 31 (1 bit)


TO

I2C_TO
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TO TO read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TIME_OUT_REG

TIME_OUT_REG :
bits : 0 - 19 (20 bit)


DATE

I2C_DATE
address_offset : 0xF8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DATE DATE read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATE

DATE :
bits : 0 - 31 (32 bit)



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