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EFUSE

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x920 byte (0x0)
mem_usage : registers
protection : not protected

Registers

BLK0_RDATA0

BLK0_RDATA4

STATUS

CMD

INT_RAW

INT_ST

INT_ENA

INT_CLR

DAC_CONF

DEC_STATUS

BLK0_RDATA5

BLK0_RDATA6

BLK0_WDATA0

DATE

BLK0_WDATA1

BLK0_WDATA2

BLK0_WDATA3

BLK0_WDATA4

BLK0_WDATA5

BLK0_WDATA6

BLK1_RDATA0

BLK1_RDATA1

BLK0_RDATA1

BLK1_RDATA2

BLK1_RDATA3

BLK1_RDATA4

BLK1_RDATA5

BLK1_RDATA6

BLK1_RDATA7

BLK2_RDATA0

BLK2_RDATA1

BLK2_RDATA2

BLK2_RDATA3

BLK2_RDATA4

BLK2_RDATA5

BLK2_RDATA6

BLK2_RDATA7

BLK3_RDATA0

BLK3_RDATA1

BLK0_RDATA2

BLK3_RDATA2

BLK3_RDATA3

BLK3_RDATA4

BLK3_RDATA5

BLK3_RDATA6

BLK3_RDATA7

BLK1_WDATA0

BLK1_WDATA1

BLK1_WDATA2

BLK1_WDATA3

BLK1_WDATA4

BLK1_WDATA5

BLK1_WDATA6

BLK1_WDATA7

BLK2_WDATA0

BLK2_WDATA1

BLK0_RDATA3

BLK2_WDATA2

BLK2_WDATA3

BLK2_WDATA4

BLK2_WDATA5

BLK2_WDATA6

BLK2_WDATA7

BLK3_WDATA0

BLK3_WDATA1

BLK3_WDATA2

BLK3_WDATA3

BLK3_WDATA4

BLK3_WDATA5

BLK3_WDATA6

BLK3_WDATA7

CLK

CONF


BLK0_RDATA0

EFUSE_BLK0_RDATA0
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BLK0_RDATA0 BLK0_RDATA0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RD_EFUSE_RD_DIS RD_FLASH_CRYPT_CNT

RD_EFUSE_RD_DIS :
bits : 16 - 19 (4 bit)

RD_FLASH_CRYPT_CNT :
bits : 20 - 26 (7 bit)


BLK0_RDATA4

EFUSE_BLK0_RDATA4
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BLK0_RDATA4 BLK0_RDATA4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RD_CK8M_FREQ RD_ADC_VREF RD_SDIO_DREFH RD_SDIO_DREFM RD_SDIO_DREFL RD_XPD_SDIO_REG RD_SDIO_TIEH RD_SDIO_FORCE

RD_CK8M_FREQ :
bits : 0 - 7 (8 bit)

RD_ADC_VREF :
bits : 8 - 12 (5 bit)

RD_SDIO_DREFH :
bits : 8 - 9 (2 bit)

RD_SDIO_DREFM :
bits : 10 - 11 (2 bit)

RD_SDIO_DREFL :
bits : 12 - 13 (2 bit)

RD_XPD_SDIO_REG :
bits : 14 - 14 (1 bit)

RD_SDIO_TIEH :
bits : 15 - 15 (1 bit)

RD_SDIO_FORCE :
bits : 16 - 16 (1 bit)


STATUS

EFUSE_STATUS
address_offset : 0x100 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

STATUS STATUS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DEBUG

DEBUG :
bits : 0 - 31 (32 bit)


CMD

EFUSE_CMD
address_offset : 0x104 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CMD CMD read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 READ_CMD PGM_CMD

READ_CMD :
bits : 0 - 0 (1 bit)

PGM_CMD :
bits : 1 - 1 (1 bit)


INT_RAW

EFUSE_INT_RAW
address_offset : 0x108 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

INT_RAW INT_RAW read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 READ_DONE_INT_RAW PGM_DONE_INT_RAW

READ_DONE_INT_RAW :
bits : 0 - 0 (1 bit)

PGM_DONE_INT_RAW :
bits : 1 - 1 (1 bit)


INT_ST

EFUSE_INT_ST
address_offset : 0x10C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

INT_ST INT_ST read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 READ_DONE_INT_ST PGM_DONE_INT_ST

READ_DONE_INT_ST :
bits : 0 - 0 (1 bit)

PGM_DONE_INT_ST :
bits : 1 - 1 (1 bit)


INT_ENA

EFUSE_INT_ENA
address_offset : 0x110 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

INT_ENA INT_ENA read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 READ_DONE_INT_ENA PGM_DONE_INT_ENA

READ_DONE_INT_ENA :
bits : 0 - 0 (1 bit)

PGM_DONE_INT_ENA :
bits : 1 - 1 (1 bit)


INT_CLR

EFUSE_INT_CLR
address_offset : 0x114 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

INT_CLR INT_CLR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 READ_DONE_INT_CLR PGM_DONE_INT_CLR

READ_DONE_INT_CLR :
bits : 0 - 0 (1 bit)

PGM_DONE_INT_CLR :
bits : 1 - 1 (1 bit)


DAC_CONF

EFUSE_DAC_CONF
address_offset : 0x118 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DAC_CONF DAC_CONF read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DAC_CLK_DIV DAC_CLK_PAD_SEL

DAC_CLK_DIV :
bits : 0 - 7 (8 bit)

DAC_CLK_PAD_SEL :
bits : 8 - 8 (1 bit)


DEC_STATUS

EFUSE_DEC_STATUS
address_offset : 0x11C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DEC_STATUS DEC_STATUS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DEC_WARNINGS

DEC_WARNINGS :
bits : 0 - 11 (12 bit)


BLK0_RDATA5

EFUSE_BLK0_RDATA5
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BLK0_RDATA5 BLK0_RDATA5 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RD_SPI_PAD_CONFIG_CLK RD_SPI_PAD_CONFIG_Q RD_SPI_PAD_CONFIG_D RD_INST_CONFIG RD_FLASH_CRYPT_CONFIG

RD_SPI_PAD_CONFIG_CLK :
bits : 0 - 4 (5 bit)

RD_SPI_PAD_CONFIG_Q :
bits : 5 - 9 (5 bit)

RD_SPI_PAD_CONFIG_D :
bits : 10 - 14 (5 bit)

RD_INST_CONFIG :
bits : 20 - 27 (8 bit)

RD_FLASH_CRYPT_CONFIG :
bits : 28 - 31 (4 bit)


BLK0_RDATA6

EFUSE_BLK0_RDATA6
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BLK0_RDATA6 BLK0_RDATA6 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RD_CODING_SCHEME RD_CONSOLE_DEBUG_DISABLE RD_DISABLE_SDIO_HOST RD_ABS_DONE_0 RD_ABS_DONE_1 RD_DISABLE_JTAG RD_DISABLE_DL_ENCRYPT RD_DISABLE_DL_DECRYPT RD_DISABLE_DL_CACHE RD_KEY_STATUS

RD_CODING_SCHEME :
bits : 0 - 1 (2 bit)

RD_CONSOLE_DEBUG_DISABLE :
bits : 2 - 2 (1 bit)

RD_DISABLE_SDIO_HOST :
bits : 3 - 3 (1 bit)

RD_ABS_DONE_0 :
bits : 4 - 4 (1 bit)

RD_ABS_DONE_1 :
bits : 5 - 5 (1 bit)

RD_DISABLE_JTAG :
bits : 6 - 6 (1 bit)

RD_DISABLE_DL_ENCRYPT :
bits : 7 - 7 (1 bit)

RD_DISABLE_DL_DECRYPT :
bits : 8 - 8 (1 bit)

RD_DISABLE_DL_CACHE :
bits : 9 - 9 (1 bit)

RD_KEY_STATUS :
bits : 10 - 10 (1 bit)


BLK0_WDATA0

EFUSE_BLK0_WDATA0
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BLK0_WDATA0 BLK0_WDATA0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WR_DIS RD_DIS FLASH_CRYPT_CNT

WR_DIS :
bits : 0 - 15 (16 bit)

RD_DIS :
bits : 16 - 19 (4 bit)

FLASH_CRYPT_CNT :
bits : 20 - 26 (7 bit)


DATE

EFUSE_DATE
address_offset : 0x1FC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DATE DATE read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATE

DATE :
bits : 0 - 31 (32 bit)


BLK0_WDATA1

EFUSE_BLK0_WDATA1
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BLK0_WDATA1 BLK0_WDATA1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WIFI_MAC_CRC_LOW

WIFI_MAC_CRC_LOW :
bits : 0 - 31 (32 bit)


BLK0_WDATA2

EFUSE_BLK0_WDATA2
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BLK0_WDATA2 BLK0_WDATA2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WIFI_MAC_CRC_HIGH

WIFI_MAC_CRC_HIGH :
bits : 0 - 23 (24 bit)


BLK0_WDATA3

EFUSE_BLK0_WDATA3
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BLK0_WDATA3 BLK0_WDATA3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CHIP_VER_DIS_APP_CPU CHIP_VER_DIS_BT CHIP_VER_32PAD CHIP_VER_DIS_CACHE SPI_PAD_CONFIG_HD CHIP_VER_PKG CHIP_CPU_FREQ_LOW CHIP_CPU_FREQ_RATED CHIP_VER_REV1

CHIP_VER_DIS_APP_CPU :
bits : 0 - 0 (1 bit)

CHIP_VER_DIS_BT :
bits : 1 - 1 (1 bit)

CHIP_VER_32PAD :
bits : 2 - 2 (1 bit)

CHIP_VER_DIS_CACHE :
bits : 3 - 3 (1 bit)

SPI_PAD_CONFIG_HD :
bits : 4 - 8 (5 bit)

CHIP_VER_PKG :
bits : 9 - 11 (3 bit)

CHIP_CPU_FREQ_LOW :
bits : 12 - 12 (1 bit)

CHIP_CPU_FREQ_RATED :
bits : 13 - 13 (1 bit)

CHIP_VER_REV1 :
bits : 15 - 15 (1 bit)


BLK0_WDATA4

EFUSE_BLK0_WDATA4
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BLK0_WDATA4 BLK0_WDATA4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CK8M_FREQ ADC_VREF SDIO_DREFH SDIO_DREFM SDIO_DREFL XPD_SDIO_REG SDIO_TIEH SDIO_FORCE

CK8M_FREQ :
bits : 0 - 7 (8 bit)

ADC_VREF :
bits : 8 - 12 (5 bit)

SDIO_DREFH :
bits : 8 - 9 (2 bit)

SDIO_DREFM :
bits : 10 - 11 (2 bit)

SDIO_DREFL :
bits : 12 - 13 (2 bit)

XPD_SDIO_REG :
bits : 14 - 14 (1 bit)

SDIO_TIEH :
bits : 15 - 15 (1 bit)

SDIO_FORCE :
bits : 16 - 16 (1 bit)


BLK0_WDATA5

EFUSE_BLK0_WDATA5
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BLK0_WDATA5 BLK0_WDATA5 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SPI_PAD_CONFIG_CLK SPI_PAD_CONFIG_Q SPI_PAD_CONFIG_D INST_CONFIG FLASH_CRYPT_CONFIG

SPI_PAD_CONFIG_CLK :
bits : 0 - 4 (5 bit)

SPI_PAD_CONFIG_Q :
bits : 5 - 9 (5 bit)

SPI_PAD_CONFIG_D :
bits : 10 - 14 (5 bit)

INST_CONFIG :
bits : 20 - 27 (8 bit)

FLASH_CRYPT_CONFIG :
bits : 28 - 31 (4 bit)


BLK0_WDATA6

EFUSE_BLK0_WDATA6
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BLK0_WDATA6 BLK0_WDATA6 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CODING_SCHEME CONSOLE_DEBUG_DISABLE DISABLE_SDIO_HOST ABS_DONE_0 ABS_DONE_1 DISABLE_JTAG DISABLE_DL_ENCRYPT DISABLE_DL_DECRYPT DISABLE_DL_CACHE KEY_STATUS

CODING_SCHEME :
bits : 0 - 1 (2 bit)

CONSOLE_DEBUG_DISABLE :
bits : 2 - 2 (1 bit)

DISABLE_SDIO_HOST :
bits : 3 - 3 (1 bit)

ABS_DONE_0 :
bits : 4 - 4 (1 bit)

ABS_DONE_1 :
bits : 5 - 5 (1 bit)

DISABLE_JTAG :
bits : 6 - 6 (1 bit)

DISABLE_DL_ENCRYPT :
bits : 7 - 7 (1 bit)

DISABLE_DL_DECRYPT :
bits : 8 - 8 (1 bit)

DISABLE_DL_CACHE :
bits : 9 - 9 (1 bit)

KEY_STATUS :
bits : 10 - 10 (1 bit)


BLK1_RDATA0

EFUSE_BLK1_RDATA0
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BLK1_RDATA0 BLK1_RDATA0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BLK1_DOUT0

BLK1_DOUT0 :
bits : 0 - 31 (32 bit)


BLK1_RDATA1

EFUSE_BLK1_RDATA1
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BLK1_RDATA1 BLK1_RDATA1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BLK1_DOUT1

BLK1_DOUT1 :
bits : 0 - 31 (32 bit)


BLK0_RDATA1

EFUSE_BLK0_RDATA1
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BLK0_RDATA1 BLK0_RDATA1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RD_WIFI_MAC_CRC_LOW

RD_WIFI_MAC_CRC_LOW :
bits : 0 - 31 (32 bit)


BLK1_RDATA2

EFUSE_BLK1_RDATA2
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BLK1_RDATA2 BLK1_RDATA2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BLK1_DOUT2

BLK1_DOUT2 :
bits : 0 - 31 (32 bit)


BLK1_RDATA3

EFUSE_BLK1_RDATA3
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BLK1_RDATA3 BLK1_RDATA3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BLK1_DOUT3

BLK1_DOUT3 :
bits : 0 - 31 (32 bit)


BLK1_RDATA4

EFUSE_BLK1_RDATA4
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BLK1_RDATA4 BLK1_RDATA4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BLK1_DOUT4

BLK1_DOUT4 :
bits : 0 - 31 (32 bit)


BLK1_RDATA5

EFUSE_BLK1_RDATA5
address_offset : 0x4C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BLK1_RDATA5 BLK1_RDATA5 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BLK1_DOUT5

BLK1_DOUT5 :
bits : 0 - 31 (32 bit)


BLK1_RDATA6

EFUSE_BLK1_RDATA6
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BLK1_RDATA6 BLK1_RDATA6 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BLK1_DOUT6

BLK1_DOUT6 :
bits : 0 - 31 (32 bit)


BLK1_RDATA7

EFUSE_BLK1_RDATA7
address_offset : 0x54 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BLK1_RDATA7 BLK1_RDATA7 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BLK1_DOUT7

BLK1_DOUT7 :
bits : 0 - 31 (32 bit)


BLK2_RDATA0

EFUSE_BLK2_RDATA0
address_offset : 0x58 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BLK2_RDATA0 BLK2_RDATA0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BLK2_DOUT0

BLK2_DOUT0 :
bits : 0 - 31 (32 bit)


BLK2_RDATA1

EFUSE_BLK2_RDATA1
address_offset : 0x5C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BLK2_RDATA1 BLK2_RDATA1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BLK2_DOUT1

BLK2_DOUT1 :
bits : 0 - 31 (32 bit)


BLK2_RDATA2

EFUSE_BLK2_RDATA2
address_offset : 0x60 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BLK2_RDATA2 BLK2_RDATA2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BLK2_DOUT2

BLK2_DOUT2 :
bits : 0 - 31 (32 bit)


BLK2_RDATA3

EFUSE_BLK2_RDATA3
address_offset : 0x64 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BLK2_RDATA3 BLK2_RDATA3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BLK2_DOUT3

BLK2_DOUT3 :
bits : 0 - 31 (32 bit)


BLK2_RDATA4

EFUSE_BLK2_RDATA4
address_offset : 0x68 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BLK2_RDATA4 BLK2_RDATA4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BLK2_DOUT4

BLK2_DOUT4 :
bits : 0 - 31 (32 bit)


BLK2_RDATA5

EFUSE_BLK2_RDATA5
address_offset : 0x6C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BLK2_RDATA5 BLK2_RDATA5 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BLK2_DOUT5

BLK2_DOUT5 :
bits : 0 - 31 (32 bit)


BLK2_RDATA6

EFUSE_BLK2_RDATA6
address_offset : 0x70 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BLK2_RDATA6 BLK2_RDATA6 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BLK2_DOUT6

BLK2_DOUT6 :
bits : 0 - 31 (32 bit)


BLK2_RDATA7

EFUSE_BLK2_RDATA7
address_offset : 0x74 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BLK2_RDATA7 BLK2_RDATA7 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BLK2_DOUT7

BLK2_DOUT7 :
bits : 0 - 31 (32 bit)


BLK3_RDATA0

EFUSE_BLK3_RDATA0
address_offset : 0x78 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BLK3_RDATA0 BLK3_RDATA0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BLK3_DOUT0

BLK3_DOUT0 :
bits : 0 - 31 (32 bit)


BLK3_RDATA1

EFUSE_BLK3_RDATA1
address_offset : 0x7C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BLK3_RDATA1 BLK3_RDATA1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BLK3_DOUT1

BLK3_DOUT1 :
bits : 0 - 31 (32 bit)


BLK0_RDATA2

EFUSE_BLK0_RDATA2
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BLK0_RDATA2 BLK0_RDATA2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RD_WIFI_MAC_CRC_HIGH

RD_WIFI_MAC_CRC_HIGH :
bits : 0 - 23 (24 bit)


BLK3_RDATA2

EFUSE_BLK3_RDATA2
address_offset : 0x80 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BLK3_RDATA2 BLK3_RDATA2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BLK3_DOUT2

BLK3_DOUT2 :
bits : 0 - 31 (32 bit)


BLK3_RDATA3

EFUSE_BLK3_RDATA3
address_offset : 0x84 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BLK3_RDATA3 BLK3_RDATA3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BLK3_DOUT3 RD_ADC1_TP_LOW RD_ADC1_TP_HIGH RD_ADC2_TP_LOW RD_ADC2_TP_HIGH

BLK3_DOUT3 :
bits : 0 - 31 (32 bit)

RD_ADC1_TP_LOW :
bits : 0 - 6 (7 bit)

RD_ADC1_TP_HIGH :
bits : 7 - 15 (9 bit)

RD_ADC2_TP_LOW :
bits : 16 - 22 (7 bit)

RD_ADC2_TP_HIGH :
bits : 23 - 31 (9 bit)


BLK3_RDATA4

EFUSE_BLK3_RDATA4
address_offset : 0x88 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BLK3_RDATA4 BLK3_RDATA4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BLK3_DOUT4

BLK3_DOUT4 :
bits : 0 - 31 (32 bit)


BLK3_RDATA5

EFUSE_BLK3_RDATA5
address_offset : 0x8C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BLK3_RDATA5 BLK3_RDATA5 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BLK3_DOUT5

BLK3_DOUT5 :
bits : 0 - 31 (32 bit)


BLK3_RDATA6

EFUSE_BLK3_RDATA6
address_offset : 0x90 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BLK3_RDATA6 BLK3_RDATA6 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BLK3_DOUT6

BLK3_DOUT6 :
bits : 0 - 31 (32 bit)


BLK3_RDATA7

EFUSE_BLK3_RDATA7
address_offset : 0x94 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BLK3_RDATA7 BLK3_RDATA7 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BLK3_DOUT7

BLK3_DOUT7 :
bits : 0 - 31 (32 bit)


BLK1_WDATA0

EFUSE_BLK1_WDATA0
address_offset : 0x98 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BLK1_WDATA0 BLK1_WDATA0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BLK1_DIN0

BLK1_DIN0 :
bits : 0 - 31 (32 bit)


BLK1_WDATA1

EFUSE_BLK1_WDATA1
address_offset : 0x9C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BLK1_WDATA1 BLK1_WDATA1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BLK1_DIN1

BLK1_DIN1 :
bits : 0 - 31 (32 bit)


BLK1_WDATA2

EFUSE_BLK1_WDATA2
address_offset : 0xA0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BLK1_WDATA2 BLK1_WDATA2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BLK1_DIN2

BLK1_DIN2 :
bits : 0 - 31 (32 bit)


BLK1_WDATA3

EFUSE_BLK1_WDATA3
address_offset : 0xA4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BLK1_WDATA3 BLK1_WDATA3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BLK1_DIN3

BLK1_DIN3 :
bits : 0 - 31 (32 bit)


BLK1_WDATA4

EFUSE_BLK1_WDATA4
address_offset : 0xA8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BLK1_WDATA4 BLK1_WDATA4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BLK1_DIN4

BLK1_DIN4 :
bits : 0 - 31 (32 bit)


BLK1_WDATA5

EFUSE_BLK1_WDATA5
address_offset : 0xAC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BLK1_WDATA5 BLK1_WDATA5 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BLK1_DIN5

BLK1_DIN5 :
bits : 0 - 31 (32 bit)


BLK1_WDATA6

EFUSE_BLK1_WDATA6
address_offset : 0xB0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BLK1_WDATA6 BLK1_WDATA6 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BLK1_DIN6

BLK1_DIN6 :
bits : 0 - 31 (32 bit)


BLK1_WDATA7

EFUSE_BLK1_WDATA7
address_offset : 0xB4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BLK1_WDATA7 BLK1_WDATA7 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BLK1_DIN7

BLK1_DIN7 :
bits : 0 - 31 (32 bit)


BLK2_WDATA0

EFUSE_BLK2_WDATA0
address_offset : 0xB8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BLK2_WDATA0 BLK2_WDATA0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BLK2_DIN0

BLK2_DIN0 :
bits : 0 - 31 (32 bit)


BLK2_WDATA1

EFUSE_BLK2_WDATA1
address_offset : 0xBC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BLK2_WDATA1 BLK2_WDATA1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BLK2_DIN1

BLK2_DIN1 :
bits : 0 - 31 (32 bit)


BLK0_RDATA3

EFUSE_BLK0_RDATA3
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BLK0_RDATA3 BLK0_RDATA3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RD_CHIP_VER_DIS_APP_CPU RD_CHIP_VER_DIS_BT RD_CHIP_VER_32PAD RD_CHIP_VER_DIS_CACHE RD_SPI_PAD_CONFIG_HD RD_CHIP_VER_PKG RD_CHIP_CPU_FREQ_LOW RD_CHIP_CPU_FREQ_RATED RD_CHIP_VER_REV1

RD_CHIP_VER_DIS_APP_CPU :
bits : 0 - 0 (1 bit)

RD_CHIP_VER_DIS_BT :
bits : 1 - 1 (1 bit)

RD_CHIP_VER_32PAD :
bits : 2 - 2 (1 bit)

RD_CHIP_VER_DIS_CACHE :
bits : 3 - 3 (1 bit)

RD_SPI_PAD_CONFIG_HD :
bits : 4 - 8 (5 bit)

RD_CHIP_VER_PKG :
bits : 9 - 11 (3 bit)

RD_CHIP_CPU_FREQ_LOW :
bits : 12 - 12 (1 bit)

RD_CHIP_CPU_FREQ_RATED :
bits : 13 - 13 (1 bit)

RD_CHIP_VER_REV1 :
bits : 15 - 15 (1 bit)


BLK2_WDATA2

EFUSE_BLK2_WDATA2
address_offset : 0xC0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BLK2_WDATA2 BLK2_WDATA2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BLK2_DIN2

BLK2_DIN2 :
bits : 0 - 31 (32 bit)


BLK2_WDATA3

EFUSE_BLK2_WDATA3
address_offset : 0xC4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BLK2_WDATA3 BLK2_WDATA3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BLK2_DIN3

BLK2_DIN3 :
bits : 0 - 31 (32 bit)


BLK2_WDATA4

EFUSE_BLK2_WDATA4
address_offset : 0xC8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BLK2_WDATA4 BLK2_WDATA4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BLK2_DIN4

BLK2_DIN4 :
bits : 0 - 31 (32 bit)


BLK2_WDATA5

EFUSE_BLK2_WDATA5
address_offset : 0xCC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BLK2_WDATA5 BLK2_WDATA5 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BLK2_DIN5

BLK2_DIN5 :
bits : 0 - 31 (32 bit)


BLK2_WDATA6

EFUSE_BLK2_WDATA6
address_offset : 0xD0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BLK2_WDATA6 BLK2_WDATA6 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BLK2_DIN6

BLK2_DIN6 :
bits : 0 - 31 (32 bit)


BLK2_WDATA7

EFUSE_BLK2_WDATA7
address_offset : 0xD4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BLK2_WDATA7 BLK2_WDATA7 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BLK2_DIN7

BLK2_DIN7 :
bits : 0 - 31 (32 bit)


BLK3_WDATA0

EFUSE_BLK3_WDATA0
address_offset : 0xD8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BLK3_WDATA0 BLK3_WDATA0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BLK3_DIN0

BLK3_DIN0 :
bits : 0 - 31 (32 bit)


BLK3_WDATA1

EFUSE_BLK3_WDATA1
address_offset : 0xDC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BLK3_WDATA1 BLK3_WDATA1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BLK3_DIN1

BLK3_DIN1 :
bits : 0 - 31 (32 bit)


BLK3_WDATA2

EFUSE_BLK3_WDATA2
address_offset : 0xE0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BLK3_WDATA2 BLK3_WDATA2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BLK3_DIN2

BLK3_DIN2 :
bits : 0 - 31 (32 bit)


BLK3_WDATA3

EFUSE_BLK3_WDATA3
address_offset : 0xE4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BLK3_WDATA3 BLK3_WDATA3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BLK3_DIN3 ADC1_TP_LOW ADC1_TP_HIGH ADC2_TP_LOW ADC2_TP_HIGH

BLK3_DIN3 :
bits : 0 - 31 (32 bit)

ADC1_TP_LOW :
bits : 0 - 6 (7 bit)

ADC1_TP_HIGH :
bits : 7 - 15 (9 bit)

ADC2_TP_LOW :
bits : 16 - 22 (7 bit)

ADC2_TP_HIGH :
bits : 23 - 31 (9 bit)


BLK3_WDATA4

EFUSE_BLK3_WDATA4
address_offset : 0xE8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BLK3_WDATA4 BLK3_WDATA4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BLK3_DIN4

BLK3_DIN4 :
bits : 0 - 31 (32 bit)


BLK3_WDATA5

EFUSE_BLK3_WDATA5
address_offset : 0xEC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BLK3_WDATA5 BLK3_WDATA5 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BLK3_DIN5

BLK3_DIN5 :
bits : 0 - 31 (32 bit)


BLK3_WDATA6

EFUSE_BLK3_WDATA6
address_offset : 0xF0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BLK3_WDATA6 BLK3_WDATA6 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BLK3_DIN6

BLK3_DIN6 :
bits : 0 - 31 (32 bit)


BLK3_WDATA7

EFUSE_BLK3_WDATA7
address_offset : 0xF4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BLK3_WDATA7 BLK3_WDATA7 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BLK3_DIN7

BLK3_DIN7 :
bits : 0 - 31 (32 bit)


CLK

EFUSE_CLK
address_offset : 0xF8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CLK CLK read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CLK_SEL0 CLK_SEL1 CLK_EN

CLK_SEL0 :
bits : 0 - 7 (8 bit)

CLK_SEL1 :
bits : 8 - 15 (8 bit)

CLK_EN :
bits : 16 - 16 (1 bit)


CONF

EFUSE_CONF
address_offset : 0xFC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CONF CONF read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OP_CODE FORCE_NO_WR_RD_DIS

OP_CODE :
bits : 0 - 15 (16 bit)

FORCE_NO_WR_RD_DIS :
bits : 16 - 16 (1 bit)



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